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8 : : H Responses -> : : : S: to Disks, Displays, 8 : : ATM, Etc USOO5867649A United States Patent (19) 11 Patent Number: 5,867,649 Larson (45) Date of Patent: Feb. 2, 1999 54) DANCE/MULTITUDE CONCURRENT Algorithms for Scalable Synchronization on Shaved COMPUTATION Memory Multiprocessors, J. Mollor-Crumley, ACM Trans actions on Computer Systems, vol. 9, No. 1, Feb. 1991. 75 Inventor: Brian Ralph Larson, Mpls., Minn. Verification of Sequential and Concurrent Programs, Apt. & 73 Assignee: Multitude Corporation, Bayport, Olderog; Springer-Verlag, 1991. Minn. The Science of Programming, D. Gries Springer-Verlag, 1981. 21 Appl. No.: 589,933 Computer Architecture R. Karin Prentice-Hall (1989) (CPT. 5). 22 Filed: Jan. 23, 1996 The Design and Analysis of Parallel Algorithms, S. Akl, (51) Int. Cl." ...................................................... G06F 15/16 Prentice-Hall, 1989. 52 U.S. Cl. ......................................................... 395/200.31 Executing Temporal Logic Programs, B.C. Moszkowski, 58 Field of Search ....................... 364/DIG. 1 MS File, Cambridge University Press, Copyright 1986, pp. 1-125. 364/DIG. 2 MS File: 395/377, 376, 379, 382, 385, 390, 391,561, 800, 705, 706, Primary Examiner Robert B. Harrell 712, 200.31, 800.28, 800.3, 800.36; 340/825.8 Attorney, Agent, or Firm-Haugen and Nikolai, P.A. 56) References Cited 57 ABSTRACT U.S. PATENT DOCUMENTS This invention computes by constructing a lattice of States. 4,814,978 3/1989 Dennis .................................... 395/377 Every lattice of States corresponding to correct execution 4,833,468 5/1989 Larson et al. 340/825.8 Satisfies the temporal logic formula comprising a Definitive 5,029,080 7/1991 Otsuki ..................................... 395/377 Axiomatic Notation for Concurrent Execution (DANCE) program. This invention integrates into a State-lattice com OTHER PUBLICATIONS putational model: a polymorphic, Strong type System; Reference Manual for the ADA Programming Language, US Visibility-limiting domains, first-order assertions, and logic Dept. of Defense, Jul. 1980. for proving a program correctness. This invention includes Communicating Sequential Processes, C.A.R. Hoare, Special hardware means for elimination of cache coherency Comm. of the ACM, Aug. 1978, vol. 21, No. 8. among other things, necessary to construct State-lattices An Optimum Algorithm for Mutual Exclusion in Computer concurrently. The model of computation for the DANCE Networks, Glen Ricant et al. Comm. of the ACM, Jan. 1981, language consisting of four, interrelated, logical Systems vol. 21, No. 1. describing State-lattices, types, domains, and assertions. A An Algorithm for Mutual Exclusion in Decentralized Sys fifth logical System interrelates the other four Systems allow tems, M. Maekawa, CAM Transactions on Computer Sys ing proofs of program correctness. The method of the tems, vol. 3, No. 2, May 1985. present invention teaches programs as temporal formulas The Information Structure of Distributed Mutual Exclusion Satisfied by lattices of States corresponding to correct execu Algorithms, Sanders, ACM Transactions on Computer Sys tion. State-lattices that are short and bushy allow application tems, vol. 5, No. 3, Aug. 1987. of many processors Simultaneously thus reducing execution A Tree-Based Algorithm for Distributed Mutal Exclusion, time. K. Raymond, ACM Transactions on Computer Systems, vol. 2, #1, Feb. 1989. 7 Claims, 41 Drawing Sheets g 2 O Xx 8X 8X 8X recests G 8. responses 8: &: als x 8X 3. :S& 8 8. s & : controller 8 : : H responses-> : : : s: to disks, displays, 8 : : ATM, etc. x: 8Xas X asX s 8. U.S. Patent Feb. 2, 1999 Sheet 1 of 41 5,867,649 1 O1 initial state - time 1 O3 1 O2 final state Figure 1 Prior Art U.S. Patent Feb. 2, 1999 Sheet 2 of 41 5,867,649 initial state(s) 1 O1 time 1 O3 1 O2 Nb O final state(s) Figure 2 Prior Art U.S. Patent Feb. 2, 1999 Sheet 3 of 41 5,867,649 waiting barrier ) 204 barrier barrier Figure 3 Prior Art U.S. Patent Feb. 2, 1999 Sheet 4 of 41 5,867,649 a=NL b-NIL Figure 4 U.S. Patent Feb. 2, 1999 Sheet S of 41 5,867,649 1 O1/1 O2 () time Figure 5 Prior Art U.S. Patent Feb. 2, 1999 Sheet 6 of 41 5,867,649 Figure 6 U.S. Patent Feb. 2, 1999 Sheet 7 of 41 5,867,649 Figure 7 U.S. Patent Feb. 2, 1999 Sheet 8 of 41 5,867,649 end (i)=end(k) Figure 8 U.S. Patent Feb. 2, 1999 Sheet 9 of 41 5,867,649 Figure 9 U.S. Patent Feb. 2, 1999 Sheet 10 of 41 5,867,649 C 1 O1 () () 1 O3 to C 1 O3 make W true On each Subinterval () () () OGo? Figure 10 U.S. Patent Feb. 2, 1999 Sheet 11 of 41 5,867,649 start(i) evaluate expression, e, using values of variables in first state of the Subinterval X:= e to be made true Over this interval the value of X at the end of the Subinterval becomes the Value evaluated Figure 11 U.S. Patent Feb. 2, 1999 Sheet 12 of 41 5,867,649 elements in queue Figure 12 Prior Art U.S. Patent Feb. 2, 1999 Sheet 13 of 41 5,867,649 Figure 13 Prior Art U.S. Patent Feb. 2, 1999 Sheet 14 of 41 5,867,649 Figure 14 Prior Art U.S. Patent Feb. 2, 1999 Sheet 15 of 41 5,867,649 101 unsorted employees=Johnson, Swenson, Anderson, Larson, Carlson, Jackson, Henderson, and Peterson Sorted employees= nil, nil, nil, nil, nil, nil, nil, nil number of employees=8 Figure 15 U.S. Patent Feb. 2, 1999 Sheet 16 of 41 5,867,649 103 orig=Johnson, Swenson, AnderSon, Larson, 35 Carlson, Jackson, HenderSon, PeterSon final=nil, nil, nil, nil, nil, nil, nil, nil low = 1, high = 8 Figure 16 U.S. Patent Feb. 2, 1999 Sheet 17 0f 41 5,867,649 1 O1 51 54 57 6 1 O2 Figure 17 U.S. Patent Feb. 2, 1999 Sheet 18 of 41 5,867,649 81 82-107 O O O Figure 18 U.S. Patent Feb. 2, 1999 Sheet 19 of 41 5,867,649 . 105 ( to { Figure 19 U.S. Patent Feb. 2, 1999 Sheet 20 of 41 5,867,649 53 unsolted employeeses Johnson, Swenson, Anderson, Larson, Carlson, Jackson, lenderson, and Peterson) sorted enjoy ccse inil, inil, ini, iii, nil, ini, nil, nil inct of left|ployeesri 8 is , in 8 a=Johnson, Swcinson, Anderson, Larson, Carlson, Jackson, lencierson, Peterson int cr = nil, nil, hit, in it, nil, inil, nil, ini) low-index = 1, high index is 8, its 4 a 1N?t-2 a.2)-Y (t=3 a.3) (l=4 a.4) a ?t-5 a.5) (t ta7 at 7-Y/-8 at Jolins Swet still VAthleson Larso CSOI Lenian Peter Spin 3 sills 100 socialUSS 100 S it: 3 sSss GskipTo", 92 yess 3 C s.S.) isS-7 hold=Johnson, Carlson, Jacksoil, Ancierson, 1 elderson, Larson, Peterson, Swenson) ks: (5 3 terra Johnson, Carlson, Jackson, Anderson, enclerson, Larson, Peterson, Swenson pivots G - -s- ows 5 low-7 high a 5 60 final 6) is arson fight 8 8.-- or r / N ls a =Y?t-2 a 2- LS)N (.7 it 7) (10 ato) Johnson Carson Peterson SWCIn 5O1 on35 were ) hold 1.5-Carlson, Anderson, told 7.8= Peterson, Swenson k a 7 enderson, Jackson, Johnson k = 4 Figure 20 U.S. Patent Feb. 2, 1999 Sheet 21 of 41 5,867,649 53 iter1.5) = Carlson, Anderson, iter(7.8)=Peterson, Swenso Henderson, Jackson, Johnson) pivot = 7 pivot = 4 final/=Peterson 60 44 final(5)=Johnson) final8)=Swenso 65 final(7.8)= 1 11 Peterson, Swenson) hold 1.3)=Anderson, Henderson, Carlson k=1 53 iter1.3)=Anderson, Henderson, Carlson pivot=1 60 final1=Anderson Figure 21 U.S. Patent Feb. 2, 1999 Sheet 22 of 41 5,867,649 111 hold2.3=Carlson, Henderson) k=3 53 iter2.3=Carlson, Henderson) pivot=3 54 60 low = 2 final3)=Henderson high=2 44 final2=Carlson) 65 final2.3= Carlson, Henderson) 65 final 1.3= Anderson, Carlson, Henderson) 65 final 1.5)= Anderson, Carlson, Henderson, Jackson, Johnson 65 final1.8)=Anderson, Carlson, Henderson, Jackson, Johnson, Henderson, Larson, Peterson, Swenson) 1 O2 Sorted employees 1.8)=Anderson, Carlson, Henderson, Jackson, Johnson, Henderson, Larson, Peterson, Swenson) Figure 22 U.S. Patent Feb. 2, 1999 Sheet 23 of 41 5,867,649 Figure 22A XXXX K S& KXXX proCeSSOrS Figure 23 U.S. Patent Feb. 2, 1999 Sheet 24 of 41 5,867,649 request G &&. recuests & responses & XXXX: &N& memory response € X controller reCueStS X responses to disks, displays, X2XYXX ATM. etc X W vw. &SAAAAYA Figure 24 physical address RAM address Figure 25 U.S. Patent Feb. 2, 1999 Sheet 25 of 41 5,867,649 CT-I-O-------- an as C. low addresses E::::::::::::::::ECSOSE:E::::::::::::: Main Memory Word 17 bits 3 bits 64 bits Figure 27 U.S. Patent Feb. 2, 1999 Sheet 26 of 41 5,867,649 segmentedaddress User Segment Table range error Oriolin effective virtual address Figure 28 U.S. Patent Feb. 2, 1999 Sheet 27 of 41 5,867,649 effective virtual address Page Table range error oridin physical address Figure 29 U.S. Patent Feb. 2, 1999 Sheet 28 of 41 5,867,649 free-list head array he Pool Figure 30 U.S. Patent Feb. 2, 1999 Sheet 29 of 41 5,867,649 segment length | | || segment origin ecurity level equirements page Size OS-only Orotected ead-only global, spread, shared, or private Figure 31 U.S. Patent Feb. 2, 1999 Sheet 30 of 41 5,867,649 requirements security level page size 5 bits OS-only Orotected ead-only global, Spread, Shared, or private 2 bits Figure 32 U.S.
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