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AMS Designer Migration, Usability, and Performance Improvements

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AMS Designer Migration, Usability, and Performance Improvements AMS Designer Migration, Usability, and Performance Improvements Cadence Design Systems Indu Jain, Tina Najibi, Lei Song, Junwei Hou, Vijay Setia, Poonam Singhal Presented at AMS Designer from SpectreVerilog: Migration and Usability Improvements Indu Jain Tina Najibi Lei Song Junwei Hou Vijay Setia Poonam Singhal which is becoming critical as more and more ABSTRACT digital IP adheres to that standard. Furthermore, whereas in the 90s almost all mixed-signal design was created by Analog designers in the Virtuoso ® AMS Designer (AMSD) contains a Virtuoso ® Analog Design Environment (ADE), wide breadth of state of the art features today an increasing number of digital designers exceeding those of other solutions such as and verification engineers are required to run SpectreVerilog. In spite of this, many customers mixed-signal full chip simulations on the continue to use SpectreVerilog, as the migration command line. This is an area where path from SpectreVerilog to AMSD contains a SpectreVerilog is rarely, if ever, used and in fact number of barriers and ease of use issues. This was not created to meet this need. paper will discuss the solutions to barriers such as PDK conversion, design modifications and AMS Designer (AMSD), on the other hand, was verilog text usage. Additionally, this session will created to meet the demands of full chip present performance gains as well as usability simulations on the command line as well as the and debugability improvements. The demands of Analog designers in ADE. AMSD is introduction of a new netlister in the AMSD flow a feature and language rich simulator, built on (the OSS netlister) and a new simulator flow the NC technology using the latest language makes these solutions possible. Additionally standards. there have been key performance improvements in the AMSD simulator itself. The final section So why are some customers still using of the paper will walk the participants through SpectreVerilog and not the acknowledged better the greatly simplified migration process and will solution, AMSD? There are a number of present the specific performance improvements migration barriers that makes it difficult for a compared to SpectreVerilog. This new designer to migrate to AMSD. This paper will methodology will enable customers to quickly walk through the issues and solutions. The paper move to the feature and language rich AMSD will also discuss another important topic – with minimal effort, thereby greatly increasing usability and debugability and how these issues designer productivity. Depending on a number of are solved. In the final section an example will factors, defined in the paper, the migration to be presented using SpectreVerilog and then AMSD can be cut down from a month to less AMSD, demonstrating the greatly simplified than a day. Designer productivity is further path to using AMSD. bolstered by the improvements in usability, debugability and performance. All of these will be presented in the paper along with a PDK ISSUES performance comparison. The first task a new AMSD user faces is PDK conversion. AMSD’s cell based netlister INTRODUCTION (amsdirect) requires that specific AMSD information (ams simInfos and ams specific SpectreVerilog has been widely used since the netlist procedures) be created in the PDK. A early 1990s and for the most part, it performs the conversion toolbox is available to convert the tasks an Analog designer needs. However, spectre views in a PDK to ams simInfos. For the SpectreVerilog is starting to run out of steam. most part this tool works fine, although there SpectreVerilog does not support the new could be cases that require manual intervention. languages such as Verilog-AMS and VHDL- All spectre-specific netlist procedures need to be AMS and does not support key functionality manually rewritten for AMSD. This can take such as bi-directional ports. Verilog-XL does time, especially if the original author of the not support the latest Verilog 2001 standard, spectre netlist procedures is no longer available. Debugging the ams simInfos and netlist SpectreVerilog config will not work for AMSD procedures can also be time consuming, with the cell based netlister. This issue is solved especially if the issue is not discovered until the with OSS, as the same SpectreVerilog config elaborator or simulator either fails or gets works for AMSD without requiring any changes. incorrect results. Once the ams simInfos and netlist procedures have been added and A second difference is in the netlisted line itself. debugged, the designer is ready to use AMSD. The Spectre netlister ignores the CDF parameter However, the amount of time to complete the type. Regardless of whether a parameter type is PDK conversion can often take days to rarely string or float, it is printed as a number without months depending on a number of factors quotes. The AMSD cell based netlister prints ranging from the number of custom netlist the values according to the CDF parameter type. procedures that need to be written to something Floats are printed without quotes and strings are as simple as lack of write access to the PDK. printed with quotes. This presents another The PDK conversion step can therefore be a migration issue as many CDF parameter types migration barrier for some customers. are strings, which works for Spectre, but then fails for AMS, as the cell based netlister prints To address this issue, an OSS netlister for these numbers in quotes. This problem has two AMSD was created. The OSS netlister uses the issues. The first issue is the fact that there may standard spectre views and netlist procedures and be no warning when this happens. The AMSD is the same netlister used for Virtuoso ® Spectre simulator can take the value of the quoted string ® Circuit Simulator, Virtuoso ® UltraSim Full- to be the parameter value. For example, chip Simulator or SpectreVerilog.. If the PDK depending on how it is used, a quoted zero (“0”) works for Spectre or SpectreVerilog, it will work has the value of 560. So the AMSD simulator for AMS. The OSS netlister completely could use the value of 560 when the designer eliminates the PDK conversion step thereby intended the value to be 0. Depending on where eliminating much of the initial setup and debug that value is used, this can result in hard to time. debug, incorrect results. The second issue is the task of correcting all the parameter types once LIBRARY SETUP ISSUES the problem is discovered. This problem is fixed with the OSS netlister, in that it will not place The AMSD cell based netlister creates the netlist quotes around numbers, ignoring the CDF for each cell within the 5X library structure. parameter type, as does the Spectre netlister. Often, the library is read only and the designer can not write into it. This can be resolved by The goal of the OSS netlister is to ensure that the using temporary (explicit TMP, AllLibs, implicit same PDK, cds.lib, config, CDF and design that TMP) directories. Using explicit TMP or works for Spectre or SpectreVerilog will work AllLibs requires modification of the cds.lib file for AMS without any design or library changes. and is another step needed for AMS that is not needed for SpectreVerilog. INCLUDING VERILOG The OSS netlister does not write into the library, Including Verilog text libraries or directories is instead the netlist is written as one file in the another area that makes it difficult to migrate to netlist directory, and therefore does not need AMSD. Verilog is included in the TMP directories of any kind. This results in one SpectreVerilog flow using the library file (-v) less minor setup step. and library directory (-y) options. This works fine with Verilog-XL, but does not work NETLISTING DIFFERENCES efficiently with the ncvlog, ncelab and ncsim (3- step) flow. There are several ways in which text In addition to PDK conversion and minor can be included in the 3-step flow, but these changes to the cds.lib to account for TMP differ with how text is included in the directories, there are a few netlisting differences SpectreVerilog flow. that the designer may need to resolve when using the cell based netlister for AMSD. The first This problem is solved with the integration of the difference is the config itself. A designer needs NC-Verilog ® Simulator (1 step) that works with to create a new config for AMSD, as the the OSS netlister. Ncverilog uses the –y/-v options as does SpectreVerilog. First, there is a concentrated effort within the AMSD simulator itself to improve error DEBUGGING messages to more clearly explain the issue and what can be done to fix it. Second, ADE now When everything works, it usually does not contains an ‘Error Explanation’ GUI. This GUI matter where the files are located or what format will provide additional information for most they are in. It doesn’t matter if there is one netlist error mnemonics. For a group of mnemonics file or hundreds of netlist files. However, when more information for an ADE designer is there is an problem, and the designer feels he presented followed by the ‘nchelp’ output. For needs to look at the netlist file to debug that other mnemonics, the ‘nchelp’ output is problem, these factors all become important. provided. Along the same lines, another benefit of the OSS netlister is the fact that since it is the With the cell based netlister, the actual netlists same netlister that is used for SpectreVerilog, the (one netlist per cell) (vams files) are created messages that it prints should be familiar. within the lib/cell/view structure itself. If something goes wrong, there is no ‘one place’ to PERFORMANCE check the netlist file. This is somewhat made IMPROVEMENTS easier in ADE with the fact that all these separate netlist files are concatenated into one file – AMSD uses Verilog-AMS connect modules for however, this is not the file that is actually more flexible and accurate analog-digital simulated and it may contain name clashes interface modeling.
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