Hornetella ORG1408 GPS Receiver Module

HORNETELLA (ORG1408) GPS RECEIVER MODULE

DatasheetDATASHEET

OriginGPS.comO r i g i n GPS . c o m HORNETELLADatasheet (ORG1408) OriginGPS.comO r i g i n GPS . c o m

GPS RECEIVER MODULE Page 1 of 32 Hotnetella – ORG1408 Datasheet Revision 2.1 June 5, 2016 DATASHEET

INDEX 1. SCOPE ...... 5 2. DISCLAIMER ...... 5 3. SAFETY INFORMATION ...... 5 4. ESD SENSITIVITY ...... 5 5. CONTACT INFORMATION ...... 5 6. RELATED DOCUMENTATION...... 5 7. REVISION HISTORY ...... 5 8. GLOSSARY ...... 6 9. ABOUT HORNET FAMILY ...... 7 10. ABOUT MICRO HORNET MODULE ...... 7 11. ABOUT ORIGINGPS ...... 7 12. DESCRIPTION...... 8 12.1. FEATURES ...... 8 12.2. ARCHITECTURE...... 9 13. ELECTRICAL SPECIFICATIONS ...... 10 13.1. ABSOLUTE MAXIMUM RATINGS ...... 11 13.2. RECOMMENDED OPERATING CONDITIONS ...... 12 14. PERFORMANCE ...... 13 14.1. ACQUISITION TIME ...... 13 14.1.1. HOT START ...... 13 14.1.2. WARM START ...... 13 14.1.3. COLD START ...... 13 14.1.4. AIDED START ...... 13 14.2. SENSITIVITY ...... 13 14.3. ACCURACY ...... 14 14.4. DYNAMIC CONSTRAINS ...... 14 15. POWER MANAGEMENT ...... 15 15.1. POWER CONSUMPTION...... 15 15.2. POWER STATES ...... 15 15.2.1. FULL POWER ACQUISITION...... 15 15.2.2. FULL POWER TRACKING...... 15 15.2.3. CPU ONLY ...... 15 15.2.4. STANDBY ...... 15 15.2.5. HIBERNATE ...... 15 15.3. BASIC POWER SAVING MODE...... 15 15.4. SELF MANAGED POWER SAVING MODES ...... 16 15.4.1. ADAPTIVE TRICKLE POWER (ATP™) ...... 16 15.4.2. PUSH TO FIX (PTF™) ...... 16 15.4.3. ADVANCED POWER MANAGEMENT (APM™) ...... 17 16. EXTENDED FEATURES ...... 18 16.1. ALMANAC BASED POSITIONING (ABP™) ...... 18 16.2. ACTIVE JAMMER DETECTOR AND REMOVER ...... 18 16.3. CLIENT GENERATED EXTENDED EPHEMERIS (CGEE™) ...... 18 16.4. SERVER GENERATED EXTENDED EPHEMERIS (SGEE™) ...... 18 17. INTERFACE...... 19 17.1. PAD ASSIGNMENT...... 19 17.2. POWER SUPPLY ...... 19 17.2.2. GROUND...... 19 17.3. CONTROL INTERFACE ...... 21 17.3.1. ON_OFF ...... 21 17.3.2. WAKEUP ...... 21 17.3.3. RESET...... 21 17.3.4. 1PPS...... 21 17.4. DATA INTERFACE...... 22 17.4.1. UART...... 22

Page 2 of 32 Hotnetella – ORG1408 Datasheet Revision 2.1 June 5, 2016

17.4.2. SPI...... 22 17.4.3. I2C ...... 22 17.4.4. SMART SENSORS DATA INTERFACE ...... 22 17.4.5. DEAD RECKONING I2C INTERFACE...... 22 17.4.6. EIT INPUT ...... 22 17.4.7. DATA STORAGE SUPPORT ...... 22 17.4.8. RF INPUT ...... 22 18. TYPICAL APPLICATION CIRCUIT...... 24 19. RECOMMENDED PCB LAYOUT ...... 25 19.1. FOOTPRINT...... 25 20. DESIGN CONSIDERATIONS ...... 25 21. OPERATION ...... 26 21.1. STARTING THE MODULE ...... 26 21.2. VERIFYING THE MODULE HAS STARTED ...... 27 21.3. SHUTTING DOWN THE MODULE ...... 27 22. HANDLING INFORMATION...... 28 22.1. PRODUCT PACKAGING AND DELIVERY ...... 28 22.2. ASSEMBLY ...... 29 22.3. REWORK ...... 30 22.4. ESD SENSITIVITY ...... 30 22.5. SAFETY INFORMATION ...... 30 22.5. DISPOSAL INFORMATION ...... 30 23. MECHANICAL SPECIFICATIONS ...... 31 24. COMPLIANCE ...... 31 25. ORDERING INFORMATION ...... 32

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TABLE INDEX TABLE 1 – RELATED DOCUMENTATION ...... 5 TABLE 2 – REVISION HISTORY ...... 5 TABLE 3 – ABSOLUTE MAXIMUM RATINGS ...... 11 TABLE 4 – RECOMMENDED OPERATING CONDITIONS ...... 12 TABLE 5 – ACQUISITION TIME ...... 13 TABLE 6 – SENSITIVITY ...... 13 TABLE 7 – ACCURACY ...... 14 TABLE 8 – DYNAMIC CONSTRAINS ...... 14 TABLE 9 – POWER CONSUMPTION ...... 15 TABLE 10 – PIN-OUT ...... 19 TABLE 11 – HOST INTERFACE SELECT ...... 22 TABLE 12 – HARDWARE OPTIONS...... 26 TABLE 13 – START-UP TIMING ...... 27 TABLE 14 – CARRIER DIMENSIONS ...... 28 TABLE 15 – REEL DIMENSIONS ...... 29 TABLE 16 –MECHANICAL SUMMARY ...... 31 TABLE 17 – FIRMWARE OPTIONS...... 32 TABLE 18 – HARDWARE OPTIONS...... 32

FIGURE INDEX FIGURE 1 – ORG1408 ARCHITECTURE ...... 9 FIGURE 2 – SiRFstarIV™ GSD4e GPS SoC BLOCK DIAGRAM...... 10 FIGURE 3 – ATP™ TIMING ...... 16 FIGURE 4 – PTF™ TIMING ...... 16 FIGURE 5 – APM™ TIMING ...... 17 FIGURE 6 – ACTIVE JAMMER DETECTOR FREQUENCY PLOT ...... 18 FIGURE 7 – ON_OFF TIMING ...... 21 FIGURE 8 – FOOTPRINT ...... 25 FIGURE 9 –STARTUP TIMING ...... 26 FIGURE 10 – HOST PCB...... 26 FIGURE 11 – MODULE POSITION ...... 28 FIGURE 12 – REEL ...... 29 FIGURE 13 – RECOMMENDED SOLDERING PROFILE ...... 29 FIGURE 14 – MECHANICAL DRAWING ...... 31

Page 4 of 32 Hotnetella – ORG1408 Datasheet Revision 2.1 June 5, 2016

1. SCOPE This document describes the features and specifications of Hornetella ORG1408 GPS receiver module. 2. DISCLAIMER All trademarks are properties of their respective owners. Performance characteristics listed in this document do not constitute a warranty or guarantee of product performance. OriginGPS assumes no liability or responsibility for any claims or damages arising out of the use of this document, or from the use of integrated circuits based on this document. OriginGPS assumes no liability or responsibility for unintentional inaccuracies or omissions in this document. OriginGPS reserves the right to make changes in its products, specifications and other information at any time without notice. OriginGPS reserves the right to conduct, from time to time, and at its sole discretion, firmware upgrades. As long as those FW improvements have no material change on end customers, PCN may not be issued. OriginGPS navigation products are not recommended to use in life saving or life sustaining applications. 3. SAFETY INFORMATION Improper handling and use can cause permanent damage to the product. 4. ESD SENSITIVITY This product is ESD sensitive device and must be handled with care. 5. CONTACT INFORMATION Support - [email protected] or Online Form Marketing and sales - [email protected] Web – www.origingps.com 6. RELATED DOCUMENTATION № DOCUMENT NAME 1 Hornetella – ORG1418 Evaluation Kit Datasheet 2 Spider and Hornet - NMEA Protocol Reference Manual for CSR® based receivers 3 Spider and Hornet - One Socket Protocol Reference Manual for CSR® based receivers 4 Spider and Hornet - Host Interface Application Note 5 Spider and Hornet - Low Power Modes Application Note 6 Spider and Hornet - Jammer Detector and Remover Application Note TABLE 1 – RELATED DOCUMENTATION 7. REVISION HISTORY REVISION DATE CHANGE DESCRIPTION A00 June 1, 2011 First release 2.0 May 5, 2016 Format update 2.1 June 5, 2016 Power Modes update TABLE 2 – REVISION HISTORY

Page 5 of 32 Hotnetella – ORG1408 Datasheet Revision 2.1 June 5, 2016

8. GLOSSARY A-GNSS Assisted GNSS BPF Band Pass Filter CE European Community conformity mark CGEE™ Client Generated Extended Ephemeris CMOS Complementary Metal-Oxide Semiconductor COMPASS PRC GNSS (same as BDS BeiDou-2 Navigation Satellite System) EGNOS European Geostationary Navigation Overlay Service EMC Electro-Magnetic Compatibility ESD Electro-Static Discharge EVB Evaluation Board EVK Evaluation Kit FCC Federal Communications Commission GALILEO EU GNSS GLONASS Global Navigation Satellite System GNSS Global Navigation Satellite System GPS Global Positioning System I2C Inter-Integrated Circuit IC Integrated Circuit ISO International Organization for Standardization LDO Low Dropout regulator LGA Land Grid Array LNA Low Noise Amplifier MSAS Multi-functional Satellite Augmentation System MSL Moisture Sensitivity Level NFZ™ Noise-Free Zones System NMEA National Marine Electronics Association MEMS MicroElectroMechanical Systems PCB Printed Circuit Board PPS Pulse Per Second QZSS Quasi-Zenith Satellite System REACH Registration, Evaluation, Authorisation and Restriction of Chemical substances RF Radio Frequiency RHCP Right-Hand Circular Polarized RoHS Restriction of Hazardous Substances directive ROM Read-Only Memory RTC Real-Time Clock SAW Surface Acoustic Wave SBAS Satellite-Based Augmentation Systems SGEE™ Server Generated Extended Ephemeris SIP System In Package SMD Surface Mounted Device SMT Surface-Mount Technology SOC System On Chip SPI Serial Peripheral Interface TCXO Temperature-Compensated Crystal Oscillator TTFF Time To First Fix TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter WAAS Wide Area Augmentation System

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9. ABOUT HORNET FAMILY OriginGPS GNSS receiver modules have been designed to address markets where size, weight, stand-alone operation, highest level of integration, power consumption and design flexibility - all are very important. OriginGPS’ Hornet family breaks size barrier, offering the industry’s smallest fully-integrated, highly-sensitive GPS and GNSS modules with integrated antennas or on-board RF connectors. Hornet family features OriginGPS' proprietary NFZ™ technology for high sensitivity and noise immunity even under marginal signal condition, commonly found in urban canyons, under dense foliage or when the receiver’s position in space rapidly changes. Hornet family enables the shortest TTM (Time-To-Market) with minimal design risks. Just connect power supply on a single layer PCB. 10. ABOUT HORNETELLA MODULE ORG1408 GPS receiver module of ORG14XX series has been designed to address markets where stand alone operation, high level of integration, power consumption and design flexibility are very important. ORG1408 GPS receiver module is a successor of the OriginGPS ORG1308 module. Featuring OriginGPS proprietary Noise-Free Zone System™ technology the ORG1408 module offers the ultimate in high sensitivity GPS performance combined with high immunity. The ORG14XX series module is miniature multi-channel receiver that continuously tracks all satellites in view and provides accurate positioning data in industry’s standard NMEA-0183 format. The ORG14XX series module is complete SiP (System-in-Package) featuring advanced miniature packaging technology and an ultra small footprint designed to commit unique integration features for high volume, low power and cost sensitive applications. The ORG14XX series module incorporates new SiRFstarIV™ GPS processor. Internal ARM CPU core and sophisticated firmware keep GPS payload off the host and allow integration in low resources embedded solutions. The revolutionary SiRFstarIV™ architecture is optimized for how people really use location-aware products: often indoors with periods of unobstructed sky view when moving from place to place. This new architecture can detect changes in context, temperature, and satellite signals to achieve a state of near continuous availability by maintaining and opportunistically updating its internal fine time, frequency, and ephemeris data while consuming mere microwatts of battery power.

11. ABOUT ORIGINGPS OriginGPS is a world leading designer, manufacturer and supplier of miniature positioning modules, antenna modules and antenna solutions. OriginGPS modules introduce unparalleled sensitivity and noise immunity by incorporating Noise Free Zone system (NFZ™) proprietary technology for faster position fix and navigation stability even under challenging satellite signal conditions. Founded in 2006, OriginGPS is specializing in development of unique technologies that miniaturize RF modules, thereby addressing the market need for smaller wireless solutions.

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12. DESCRIPTION 12.1. FEATURES Stand alone operation OriginGPS Noise Free Zone System (NFZ™) technology Integrated SAW Filter, Voltage Regulator, I/O Buffers, TCXO and RTC 50Ω antenna input through miniature coaxial connector Active or passive antenna support SiRFstarIV™ GSD4e GPS processor L1 (1575MHz) frequency, C/A code 48 track verification channels Navigation sensitivity: -160dBm Tracking sensitivity: -163dBm for indoor fixes Fast TTFF: < 33s under cold start conditions < 1s under hot start conditions Multipath mitigation and indoor tracking Active jammer remover: tracks up to 8 CW interferers and removes jammers up to 80dB-Hz SBAS (WAAS, EGNOS, MSAS) support1 Almanac Based Positioning (ABP™)1 Client Generated Extended Ephemeris (CGEE™) and Server Generated Extended Ephemeris (SGEE™) for very fast TTFFs are supported through SiRFInstantFix™ and SiRFInstantFixII™ Assisted GPS (A-GPS) support Automatic and user programmable power saving scenarios: ATP™, PTF™, APM™ Low power consumption: <10mW during ATP™ ARM7 109MHz baseband CPU Smart sensor I2C master interface1 UART host interface, SPI optionally2 Programmable UART protocol and messages rate Selectable NMEA or OSP (SiRF Binary) communication standards Single voltage supply: wide input range 2V - 6V with UVLO Separate antenna DC bias supply Small footprint: 17mm x 17mm Surface Mount Device (SMD) Industrial operating temperature range: -400 to 850C Pb-Free RoHS compliant

Notes: 1. Available in module with Premium firmware only 2. Different ordering codes for SPI

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12.2. ARCHITECTURE

VANT VCC VTX 1.8 – 6V 2 – 6V 1.8 – 5V

V1V8

ON/OFF Regulator Pulse ON OFF Generator

1.8V

Power WAKEUP Management RF Power RESET

GSD4e GPS Processor POR BB Power Load WAKEUP Switch HOST

VTX Connector GPS Search / Track ROM / RAM WAKEUP Correlator Embedded Engine

SAW Filter LNA Processor s

Subsystem r UART / SPI

/ 1PPS I Sample RAM

DR I2C Serial Flash / EEPROM

EIT Accelerometer

Gyroscope

ORG1408 RTC Magnetometer TCXO

Pressure Sensor FIGURE 1 – ORG1408 ARCHITECTURE Antenna Connector Signals at 1575 MHz from the GPS satellites are being delivered from receiving antenna through W.FL® standard miniature coaxial connector. Load Switch Load switch provides control over DC bias voltage supply for active antenna. When module is in Hibernate state no voltage is being supplied to antenna, thereby saving power. Band-Pass SAW Filter Band-pass SAW filter eliminates inter-modulated out-of-band signals that may corrupt GPS receiver performance. Voltage Regulator Voltage regulator provides stable supply for GPS processor over wide input voltage range. The design of this section was optimized for low ripple, low quiescent current and high PSRR. TCXO (Temperature Compensated Crystal Oscillator) This highly stable 16.369 MHz oscillator controls the down conversion process in RF block of the GPS processor. Highest characteristics of this component are important factors in sensitivity, fast TTFF and navigation stability. RTC (Real Time Clock) crystal This miniature component with very tight specifications is necessary for maintaining Hot Start and Warm Start capabilities. RF Shield RF enclosure avoids external interference to compromise sensitive circuitry inside the receiver. RF shield also blocks module’s internal high frequency emissions from being radiated.

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SiRFstarIV™ GSD4e GPS SoC SiRFstarIV™ GSD4e is full SoC built on a low-power RF CMOS single-die, incorporating GPS RF, baseband, integrated navigation solution software and ARM® processor.

FIGURE 2 – SiRFstarIV™ GSD4e GPS SoC BLOCK DIAGRAM SiRFstarIV™ GSD4e is a navigation processor built on a low-power RF CMOS single-die, incorporating the baseband, integrated navigation solution software, ARM7 processor that form a complete stand alone or assisted-GPS engine. SiRFstarIV™ GSD4e GPS processor includes the following units: GPS RF core incorporating LNA, down converter, fractional-N synthesizer and ADC block with selectable 2 and 4-bit quantization GPS DSP core incorporating more than twice the clock speed and more than double the RAM capacity relative to predecessor - market benchmarking SiRFStarIII™ GPS processor ARM7 microprocessor system incorporating 109MHz CPU and interrupt controller ROM block as code storage for PVT applications RAM block for data cache RTC block UART block SPI block Power control block for internal voltage domains management

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13. ELECTRICAL SPECIFICATIONS 13.1. ABSOLUTE MAXIMUM RATINGS Stresses exceeding Absolute Maximum Ratings may damage the device.

Parameter Symbol Min Max Units

Power Supply Voltage VCC - 6.5 V

Antenna Supply Voltage VANT - 10 V

Antenna Supply Current IANT - 200 mA

TX Buffer Supply Voltage VTX - 5.5 V

TX Buffer Source/Sink Current ITX -10 10 mA

I/O Voltage VIO -0.3 3.6 V

I/O Source/Sink Current IIO -2 2 mA

1.8V Source Current I1V8 - 20 mA

fIN = 1560MHz÷1590MHz - 10 dBm RF Input Power PRF_IN fIN <1560MHz, >1590MHz - 15 dBm

ESD Rating All pads V(ESD) -2 2 kV

Power Dissipation PD - 200 mW

0 Storage temperature TST -55 125 C

0 Lead temperature (10 sec. @ 1mm from case) TLEAD - 260 C

TABLE 3 – ABSOLUTE MAXIMUM RATINGS

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13.2. RECOMMENDED OPERATING CONDITIONS Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

Parameter Symbol Mode / Pad Test Conditions Min Typ Max Units 2.0 3.3 6.0 V

Power Supply Voltage VCC VCC VCC falling 1.8 1.9 V

VCC rising 1.9 2.0 V Acquisition 33 43 mA Power Supply Current Tracking -130dBm (Outdoor) 7 33 mA 1 (Without antenna supply ICC CPU only VCC = 2V 14 mA 0 current) Standby1 TAMB = 25 C 0.1 mA Hibernate 30 50 µA

1.8V Output Voltage V1V8 V1V8 1.77 1.80 1.83 V

1.8V Output Current I1V8 V1V8 20 mA

TX Buffer Supply Voltage VTX VTX 1.80 5 V

TX Buffer Supply Current ITX VTX 1 10 mA

Antenna Supply Voltage VANT VANT 1.8 6.0 V

Antenna Supply Current IANT VANT 150 mA

Input Voltage Low State VIL UART/SPI/GPIO 0.45 V

Input Voltage Low State VIL ON_OFF 0.3 V

Input Voltage High State VIH UART/SPI/GPIO 1.26 3.6 V

Input Voltage High State VIH ON_OFF 1.0 3.6 V Output Voltage Low State VOL UART/SPI/GPIO IOL = 4mA 0.4 V

Output Voltage High State VOH UART IOH = -4mA VTX–0.4 V

Output Voltage High State VOH SPI / GPIO IOH = -4mA 1.35 1.71 1.8 V Input Leakage Current IIN(leak) UART/SPI/GPIO VIN = 1.8V or 0V -10 10 µA

Input Leakage Current IIN(leak) ON_OFF VIN = 1.8V or 0V -0.2 0.2 µA

Output Leakage Current IOUT(leak) UART/SPI/GPIO VIN = 1.8V or 0V -10 10 µA

Input Capacitance CIN UART 4 10 pF

Input Capacitance CIN SPI / GPIO 5 pF

Input Impedance ZIN RF Input f0 = 1575.5 MHz 50 Ω

Input Return Loss RLIN RF Input f0 = 1575.5 MHz -8 dB 3 0 Operating Temperature TAMB -40 25 85 C 0 0 % Relative Humidity RH -40 C ≤TAMB≤+85 C 5 95

TABLE 4 – RECOMMENDED OPERATING CONDITIONS

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Notes: 1. Transitional states of ATP™ low power mode 3. Operation below -300C to -400C is accepted, but TTFF may increase 14. PERFORMANCE 14.1. ACQUISITION TIME TTFF (Time To First Fix) – is the period of time from the module’s power-up till position estimation. 14.1.1. HOT START Hot Start results either from a software reset after a period of continuous navigation or a return from a short idle period that was preceded by a period of continuous navigation. During Hot Start all critical data (position, velocity, time, and satellite ephemeris) is valid to the specified accuracy and available in RAM.

14.1.2. WARM START Warm Start typically results from user-supplied position and time initialization data or continuous RTC operation with an accurate last known position available in RAM. In this state position and time data are present and valid, but satellite ephemeris data validity has expired. 14.1.3. COLD START Cold Start occurs when satellite ephemeris data, position and time data are unknown. 14.1.4. AIDED START Aided Start is a method of effectively reducing TTFF by making every start Hot or Warm.

1 OPERATION VALUE UNIT Hot Start < 1 s

Aided Start < 10 s

Warm Start < 32 s Cold Start < 35 s

Signal Reacquisition < 1 s

TABLE 5 – ACQUISITION TIME 14.2. SENSITIVITY

OPERATION VALUE UNIT

Tracking -163 dBm Navigation -161 dBm

Aided Start -156 dBm

Cold Start -148 dBm

TABLE 6 – SENSITIVITY Notes: 1. Module is static under signal conditions of -130dBm and ambient temperature of +25°C.

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14.3. ACCURACY

Method Accuracy Units Test Conditions < 2.5 M -130 dBm (Outdoor), Static CEP (50%) < 2 M -130 dBm (Outdoor), SBAS, Static Horizontal < 5 M -130 dBm (Outdoor), Static 2dRMS (95%) < 4 M -130 dBm (Outdoor), SBAS, Static Position < 4 M -130 dBm (Outdoor), Static VEP (50%) < 3 M -130 dBm (Outdoor), SBAS, Static Vertical <7.5 m -130 dBm (Outdoor), Static 2dRMS (95%) < 6 m -130 dBm (Outdoor), SBAS, Static

Velocity Horizontal 50% < 0.01 m/s -130 dBm (Outdoor), 30 m/s

Heading 50% < 0.01 0 -130 dBm (Outdoor), 30 m/s

Time 1 PPS < 1 µs -130 dBm (Outdoor)

TABLE 7 – ACCURACY

14.4. DYNAMIC CONSTRAINS

PARAMETER3 MAXIMUM

Velocity 515 m/s 1,000 knots Acceleration 4g Altitude 18,288 m 60,000 ft.

TABLE 8 – DYNAMIC CONSTRAINS

Notes: 1. Module is 24-hrs. static under signal conditions of -130dBm and ambient temperature of +25°C. 2. Speed over ground ≤ 30m/s. 3. Standard dynamic constrains according to regulatory limitations.

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15. POWER MANAGEMENT 15.1. POWER CONSUMPTION

Operation Mode Power Consumption Acquisition 66mW

Tracking 10-66mW

Hibernate 50µW TABLE 9 – POWER CONSUMPTION 15.2. POWER STATES 15.2.1. FULL POWER ACQUISITION ORG1408 module stays in Full Power Acquisition state until a reliable position solution is made. 15.2.2. FULL POWER TRACKING Full Power Tracking state is entered after a reliable position solution is achieved. During this state the processing is less intense compared to Full Power Acquisition, therefore power consumption is lower. Full Power Tracking state with navigation update rate at 5Hz consumes more power compared to default 1Hz navigation. 15.2.3. CPU ONLY CPU Only is the transitional state of ATP™ power saving mode when the RF and DSP sections are partially powered off. This state is entered when the satellites measurements have been acquired, but navigation solution still needs to be computed.

15.2.4. STANDBY Standby is the transitional state of ATP™ power saving mode when RF and DSP sections are completely powered off and baseband clock is stopped. 15.2.5. HIBERNATE ORG1408 module boots into Hibernate state after power supply applied, drawing only 9μA. When Hibernate state is following Full Power Tracking state current consumption is about 14μA. During this state RF, DSP and baseband sections are completely powered off leaving only RTC and Battery-Backed RAM running. Module will perform Hot Start if stayed in Hibernate state less than 4 hours from last valid position solution.

15.3. BASIC POWER SAVING MODE Basic power saving mode is elaborating host in straightforward way for controlling transfers between Full Power and Hibernate states. Current profile of this mode has no hidden cycles of satellite data refresh. Host may condition transfers by tracking duration, accuracy, satellites in-view or other parameters.

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15.4. SELF MANAGED POWER SAVING MODES Hornetella module has several self-managed power saving modes tailored for different use cases. These modes provide several levels of power saving with degradation level of position accuracy. Initial operation in Full Power state is a prerequisite for accumulation of satellite data determining location, fine time and calibration of reference clocks. 15.4.1. ADAPTIVE TRICKLE POWER (ATP™) ATP™ is best suited for applications that require navigation solutions at a fixed rate as well as low power consumption and an ability to track weak signals. This power saving mode provides the most accurate position among self-managed modes. In this mode module is intelligently cycled between Full Power state, CPU Only state consuming 14mA and Standby state consuming 90μA, therefore optimizing current profile for low power operation.

FIGURE 3 – ATP™ TIMING

15.4.2. PUSH TO FIX (PTF™) PTF™ is best suited for applications that require infrequent navigation solutions. In this mode ORG1408 module is mostly in Hibernate state, drawing < 15µA of current, waking up for satellite ephemeris data refresh in fixed periods of time. PTF™ period can be anywhere between 10 seconds and 2 hours. Host can initiate an instant position report by toggle the ON_OFF pad to wake up the module. During fix trial ORG1408 will stay in Full Power state until good position solution is estimated or pre-configured timeout for it has expired.

FIGURE 4 – PTF™ TIMING

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15.4.3. ADVANCED POWER MANAGEMENT (APM™) APM™ is used for AGPS. It allows power savings while ensuring that the Quality of the Solution (QoS) in maintained when signals level drop. In APM™ mode the module is intelligently cycled between Full Power and Hibernate states. In addition to setting the position report interval, a QoS specification is available that sets allowable error estimates and selects priorities between position report interval and more power saving. The user may select between Duty Cycle Priority for more power saving and Time Between Fixes (TBF) priority with defined or undefined maximum horizontal error. TBF range is from 10s to 180s between fixes, Power Duty Cycle range is between 5% to 100%. Maximum position error is configurable between 1 to 160m. The number of APM™ fixes is configurable up to 255 or set to continuous.

1. GPS signal level drops (e.g. user walks indoors) 2. Lower signal results in longer ON time. To maintain Duty Cycle Priority, OFF time is increased. 3. Lower signal means missed fix. To maintain future TBFs, the module goes info Full Power state until signal levels improve. FIGURE 5 – APM™ TIMING

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16. EXTENDED FEATURES 16.1. ALMANAC BASED POSITIONING (ABP™) With ABP™ mode enabled, the user can get shorter Cold Start TTFF as tradeoff with position accuracy. When no sufficient ephemeris data is available to calculate an accurate solution, a coarse solution will be provided where the position is calculated based on one or more of the GPS satellites, having their states derived from the almanac data. Data source for ABP™ may be either stored factory almanac, broadcasted or pushed almanac. 16.2. ACTIVE JAMMER DETECTOR AND REMOVER Jamming Detector is embedded DSP software that detects interference signals in GPS L1 band. Jamming Remover is another DPS software that sort-out Jamming Detector output mitigating up to 8 interference signals of Continuous Wave (CW) type up to 80dB-Hz each.

FIGURE 6 – ACTIVE JAMMER DETECTOR FREQUENCY PLOT 16.3. CLIENT GENERATED EXTENDED EPHEMERIS (CGEE™) CGEE™ feature allows shorter TTFFs by providing predicted (synthetic) ephemeris files created within a lost host system from previously received satellite ephemeris data. The prediction process requires good receipt of broadcast ephemeris data for all satellites. EE files created this way are good for up to 3 days and then expire. CGEE™ feature requires avoidance of power supply removal. CGEE™ data files are stored and managed by host. 16.4. SERVER GENERATED EXTENDED EPHEMERIS (SGEE™) SGEE™ enables shorter TTFFs by fetching Extended Ephemeris (EE) file downloaded from web server. Host is initiating periodic network sessions of EE file downloads, storage and provision to module. There is an SOW based one-time NRE charge for set-up, access to OriginGPS EE distribution server and end-end testing for re-distribution purposes, or there is a per-unit charge for each module within direct SGEE™ deployment. EE files are provided with look-ahead of 1, 3, 7, 14 or 31 days.

Page 18 of 32 Hotnetella – ORG1408 Datasheet Revision 2.1 June 5, 2016

17. INTERFACE 17.1. PAD ASSIGNMENT

Pad Number Pad Name Pad Description Direction Default Notes 1 RX UART Receive Input High 1.8 – 3.6V 2 TX UART Transmit Output High High state voltage level is set by VTX 3 VTX TX Buffer Power Power 1.8 – 5.0V 4 SCK SPI Clock Input Low 5 nSE SPI Chip Select Input High 1.8 – 3.6V 6 SDO SPI Data Out Output High 7 VANT Active Antenna Bias Output Leave floating for passive antenna 8 VCC System Power Power 2 - 6V 9 V1V8 1.8V Source Power Voltage source. Do not power this pad. 10 GND System Ground Power 11 GND System Ground Power 12 GND System Ground Power 13 GND System Ground Power 14 GND System Ground Power 15 WAKEUP Power Status Output Low 1.8V compatible 16 nRESET Asynchronous Reset Input High Do not drive 17 ON_OFF Power State Control Input Low 1.8 – 3.6V 2 18 DR_SDA Master I C SDA Bi-dir High 1.8V compatible 2 19 DR_SCL Master I C SCL Output High 20 EIT External Interrupt Input High 1.8 – 3.6V 21 1PPS UTC Time Mark Output Low 1.8V compatible 22 SDI SPI Data In Input High 1.8 – 3.6V

TABLE 10 – PIN-OUT

17.2. POWER SUPPLY The ORG1408 module requires only one power source, which can be unregulated, i.e supplied directly from a battery, since the module has internal regulators. 17.2.1 Main power VCC power input is for main power supply. VCC power supply range is 2 to 6V DC. It is recommended to keep the VCC power supply on all the time in order to maintain the non-volatile RTC and RAM active for fastest possible TTFF. When the VCC is powered off, settings are reset to factory default, and the receiver performs Cold Start on next power up. Power supply current consumption varies according to the processor load and satellite acquisition. Typical ICC current is 33mA during acquisition. Peak ICC current is 50 mA. Typical ICC current in Hibernate state is 50µA. Voltage ripple below 50mVP-P allowed for frequency between 100KHz and 3MHz.

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Voltage ripple below 15mVP-P allowed for frequency above 3MHz. Higher voltage ripple may compromise the ORG1408 module performance. 17.2.2 TX power VTX power input is for integrated data output level shifter between 1.8V GPS processor domain and host. VTX power supply range is 1.8 to 3.6V DC according to required TX output voltage swing. Typical ITX current is 1mA and varies with input load of host. VTX may be externally connected to VCC, while module and host I/O are in same voltage domain. VTX may be externally connected to V1V8, while host I/O is in 1.8V voltage domain. Data output level shifter is internally controlled by GPS processor and automatically turned off during low power states. 17.2.3 Antenna power VANT power input is for active antenna bias through integrated low-loss load switch. VANT power supply range is 1.8 to 10V DC according to antenna DC requirements. Maximum IANT current is 150mA. Load switch is internally controlled by GPS processor and antenna bias automatically turned off during low power states. VANT may be externally connected to VCC, while module and antenna are in same voltage domain. When using passive antenna, do not apply voltage on this input. 17.2.4 1.8V power source V1V8 power supply provides regulated 1.8V voltage source for peripheral components, like MEMS sensors connected to DR I2C bus. Maximum I1V8 continuous output current is 20mA. 17.2.5 Ground Single Ground pad should be connected to the main Ground with shortest possible trace or via.

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17.3. HOST CONTROL INTERFACE 17.3.1. ON_OFF input ON_OFF input is used to switch ORG1408 between different power states: . While in Hibernate state, ON_OFF pulse will initiate transfer into Full Power state. . While in ATP™ mode, ON_OFF pulse will initiate transfer into Full Power state. . While in PTF™ mode, ON_OFF pulse will initiate one PTF™ request. . While in Full Power state, ON_OFF pulse will initiate orderly shutdown into Hibernate state.

FIGURE 7 – ON_OFF TIMING ON_OFF detector set requires a rising edge and high logic level that persists for at least 100µs. ON_OFF detector reset requires ON_OFF asserted to low logic level for at least 100µs. Recommended ON_OFF Low-High-Low pulse length is 100ms. ON_OFF pulses with less than 1s intervals are not recommended. Multiple switch bounce pulses are recommended to be filtered out. Pull-down resistor of 10kΩ-33kΩ is recommended to avoid accidental power mode change. ON_OFF input is tolerable up to 3.6V. Do not drive high permanently or pull-up this input. This line must be connected to host. 17.3.2. WAKEUP output WAKEUP output from ORG1408 is used to indicate power state. A low logic level indicates that the module is in one of its low-power states - Hibernate or Standby. A high logic level indicates that the module is in Full Power state. In addition WAKEUP output can be used to control auxiliary devices, like Enable of external LNA or Load Switch of active antenna DC bias. Wakeup output is LVCMOS 1.8V compatible. Do not connect if not in use. 17.3.3. RESET̅̅̅̅̅̅̅̅ Power-on-Reset (POR) sequence is generated internally. In addition, external reset is available through RESET̅̅̅̅̅̅̅̅ pad. Resetting ORG1408 clears the state machine of self-managed power saving modes to default. RESET̅̅̅̅̅̅̅̅ signal should be applied for at least 1µs. RESET̅̅̅̅̅̅̅̅ input is active low and has internal pull-up resistor of 86kΩ to internal 1.2V domain. Do not drive this input high. Do not connect if not in use. 17.3.4. 1PPS Pulse-Per-Second (PPS) output provides a pulse signal for timing purposes. PPS output starts when position solution has been obtained using 5 or more GPS satellites. PPS output stops when 3D position solution is lost. Pulse length (high state) is 200ms with rising edge is less than 30ns synchronized to UTC epoch. The correspondent UTC time message is generated and put into output FIFO 300ms after the PPS signal. The exact time between PPS and UTC time message delivery depends on message rate, message queue and communication baud rate. 1PPS output is LVCMOS 1.8V compatible. Do not connect if not in use.

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17.4. DATA INTERFACE ORG1408 module has 3 types of interface ports to connect to host - UART, SPI or I2C – all multiplexed on a shared set of pads. At system reset host port interface lines are disabled, so no conflict occurs. Logic values on CTS̅̅̅̅̅ and RTS̅̅̅̅̅ are read by the module during startup and define host port type. External resistor of 10kΩ is recommended. Pull-up resistor is referenced to 1.8V.

PORT TYPE CTS̅̅̅̅̅ RTS̅̅̅̅̅ UART External pull-up Internal pull-up SPI (default) Internal pull-down Internal pull-up I2C Internal pull-down External pull-down TABLE 11 – HOST INTERFACE SELECT 17.4.1. UART UART host interface features are: . TX used for GPS data reports. Output logic high voltage level is LVCMOS 1.8V compatible. . RX used for receiver control. Input logic high voltage level is 1.45V, tolerable up to 3.6V. . UART flow control using CTS̅̅̅̅̅ and RTS̅̅̅̅̅ lines is disabled by default. Can be turned on by sending OSP Message ID 178, Sub ID 2 input command. 17.4.2. SPI SPI host interface features are: . Slave SPI Mode 1, supports clock up to 6.8MHz. . RX and TX have independent 2-byte idle patterns of ‘0xA7 0xB4’. . TX and RX each have independent 1024 byte FIFO buffers. . TX FIFO is disabled when empty and transmits its idle pattern until re-enabled. . RX FIFO detects a software specified number of idle pattern repeats and then disables FIFO input until the idle pattern is broken. . FIFO buffers can generate an interrupt at any fill level. . SPI detects synchronization errors and can be reset by software. . Output is LVCMOS 1.8V compatible. Inputs are tolerable up to 3.6V. 17.4.3. I2C I2C host interface features are: . I2C Multi-Master Mode - module initiates clock and data, operating speed 400kbps. . I2C address ‘0x60’ for RX and ‘0x62’ for TX. . Individual transmit and receive FIFO length of 64 bytes. . I2C host interface mode can be switched slave (Multi-master default), clock rate can be switched 100KHz (default 400KHz), address can be changed (default 0x62 for TX FIFO and 0x60 for RX FIFO) by sending OSP Message ID 178, Sub ID 2 input command. . SCL and SDA are pseudo open-drain lines, therefore require external pull-up resistors of 2.2kΩ to 1.8V, or 3.3kΩ to 3.3V.

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17.4.4. Smart Sensors Data Interface The ORG14XX module master mode I²C interface provides optional support for Dead Reckoning (DR) and optional code patch upload. This bus has 2 lines, DR_SCL and DR_SDA, both are pseudo open-drain and require external pull-up resistors. Discrete EIT input is optionally used to wake up the module from Hibernate state. 17.4.5. Dead Reckoning (DR) I²C Interface The DR I²C interface supports required sensor instruments for dead reckoning applications such as gyros, accelerometers, compasses or other sensors that can operate with an I²C bus. The ORG14XX module acts as the I2C Master and the sensor devices function in Slave mode. This provides a very low latency data pipe for the critical sensor data so that it can be used in the Navigation Library and Kalman filter to enhance navigation performance. The MEMS algorithms perform a sensor data fusion with the GPS signal measurements. GPS measurements can be used to calibrate the MEMS sensors during periods of GPS navigation. The MEMS sensors can augment GPS measurements, and can be more accurate than GPS under degraded GPS signal conditions and certain dynamics. DR I²C interface supports:  Common sensor formats  Typical data lengths (command + in/data out) of several bytes  Standard I²C bus maximum data rate 400kbps  Minimum data rate 100kbps In current Premium firmware implementation, MEMS sensors integration provides a pseudo “position pinning” feature to prevent position wander and heading instability. 17.4.6. EIT input The EIT (External Interrupt) input is optionally used by external sensors to provide a discrete interrupt to the module when a change of state is detected. The input is either a level triggered or an edge triggered programmable for high/ low level or rising/falling edge. The input is disabled during initial power-up or reset. EIT interrupt input logic high state is 1.8 to 3.6V. Do not connect to this input if the feature is not in use. 17.4.7. Data Storage Support The DR I²C interface is available at boot-up for uploading data from a serial EEPROM. Firmware updates may be provided from time to time to address ROM firmware issues as a method of performance improvement. The DR I²C interface also supports serial flash devices used to store ARM7TDMI patch loads, including optional:  FIFO support  ARM7TDMI dedication to I²C interface during serial flash read or write 17.4.8. RF input The module supports active and passive antennas. The antenna input impedance is 50Ω. DC bias voltage for active antennas is provided via VANT pad. Recommended active antenna NF ≤ 1.8 dB, net gain excluding cable loss 10dB ≤ G ≤ 25dB. Leave VANT pad floating while using passive antenna. Contact OriginGPS for passive antenna selection.

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18. TYPICAL APPLICATION CIRCUIT

UART Host Interface – ordering codes R01, R02

Vcc Vant

FB1

ASSEMBLE FERRITE BEAD FOR ACTIVE ANTENNA

1K @ 100MHz

9 3 8 7

R4 100R V1V8 VTX VCC VANT 1PPS_GPS 18 19 DR_SDA C1 20 DR_SCL EIT 18pF 21 1PPS R1 0R ON_OFF 17 1PPS ON_OFF_GPS ON_OFF U1 R2 0R WAKEUP 15 WAKEUP_GPS WAKEUP 5 R3 0R nRESET 16 SE 4 nRESET_GPS RESET SCK 6 SDO 22 SDI R5 100R TX_GPS 2 TX TX 1 RX R6 220R GND1 GND2 GND3 GND4 GND5 RX RX_GPS

10 11 12 13 14 TX HAS LEVEL TRANSLATOR AS SET BY VTX

INPUTS ARE 3.6V TOLERANT

SPI Host Interface – ordering code R03

Vcc Vant

FB1

ASSEMBLE FERRITE BEAD FOR ACTIVE ANTENNA

1K @ 100MHz

9 3 8 7

R4 100R V1V8 VTX VCC VANT 1PPS_GPS 18 19 DR_SDA C1 20 DR_SCL EIT 18pF 21 1PPS R1 0R ON_OFF 17 1PPS ON_OFF_GPS ON_OFF U1 R5 220R SPI_CS R2 0R WAKEUP 15 WAKEUP_GPS WAKEUP 5 R6 220R SPI_CLK R3 0R nRESET 16 SE 4 nRESET_GPS RESET SCK 6 R7 100R SPI_DO SDO 22 SDI R8 220R SPI_DI 2 TX 1 GND1 GND2 GND3 GND4 GND5 RX SDO HAS LEVEL TRANSLATOR AS SET BY VTX

10 11 12 13 14 INPUTS ARE 3.6V TOLERANT

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19. RECOMMENDED PCB LAYOUT 19.1. FOOTPRINT TOP VIEW

0.669 16.99 0.596 15.14

0.050 1.27 12 11

0.490

0.669 0.669 12.45 0.033 16.99 16.99 0.84

22 1

0.042 0.050 1.07 1.27 inch millimeter FIGURE 8 – FOOTPRINT Ground paddle at the middle should be connected to main Ground plane by multiple vias. Ground paddle at the middle must be solder masked. Silk print of module’s outline is highly recommended for SMT visual inspection.

20. DESIGN CONSIDERATIONS Keep out of signal or switching power traces and vias under the ORG1408 GPS module. Signal traces to/from ORG1408 GPS module should have minimum length. Recommended distance from adjacent active components is 3mm. In case of adjacent high speed components, like CPU or memory, high frequency components, like transmitters, clock resonators or oscillators, metal planes, like LCD or battery enclosures, please contact OriginGPS for more precise, application specific recommendations.

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21. OPERATION When power is first applied, ORG41408 goes into a Hibernate state while integrated RTC starts and internal Finite State Machine (FSM) sequences though to “Ready-to-Start” state. Host is not required to control external master nRESET since module’s internal reset circuitry handles detection of power application. While in “Ready-to-Start” state, ORG1418 awaits a pulse to the ON_OFF input. Since integrated RTC startup times are variable, host is required either to wait for a fixed interval or to monitor a short Low-High-Low pulse on WAKEUP output that indicates FSM “Ready-to-Start” state. Another option is to repeat a pulse on the ON_OFF input every second until the module starts by either detecting a stable logic high level on WAKEUP output or neither generation of UART messages. 21.1. STARTING THE MODULE Module start-up procedure depends upon the chosen ordering option. Boot Option 01 Boot Option 02 Boot Option 03 Ordering code ORG1408-xx01 ORG1408-xx02 ORG1408-xx03 Power On State Full Power Hibernate Hibernate Host Interface UART UART SPI Interface settings on power 4,800 bps 8-N-1 4,800 bps 8-N-1 Slave Data format on power NMEA NMEA NMEA Table 12: Hardware options 01 ordering code: . The module has integrated power-up circuit that automatically asserts ON_OFF pulse 1 sec. after FSM indicates “Ready-to-Start” condition. 02 and 03 ordering codes: . A pulse on the ON_OFF input will command the module to start. . Since integrated RTC startup times are variable, detection of when the module is ready to accept an ON_OFF pulse requires the host to either wait for a fixed interval of 1 sec., or to monitor a pulse on module WAKEUP output that indicates FSM “Ready-to-Start”. . Optionally, a pulse on the ON_OFF input can be asserted every second until the module starts by indicating logic high level on WAKEUP output.

FIGURE 9 – START-UP TIMING

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Note: 1. If power provided through dual supply, assign 1.8V LDO with low quiescent current for Hibernate state and 1.8V DC-DC with high efficiency for Full Power state.

SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT

fRTC RTC frequency 25°C -20 ppm 32768 +20 ppm Hz

tRTC RTC tick 25°C 30.5176 µs

∆T1 RTC startup time 300 ms

∆T0 Power stabilization 6·tRTC+∆T1 7·tRTC+∆T1 8·tRTC+∆T1 µs

∆T6 WAKEUP pulse RTC running 10 tRTC

∆TLOW ON_OFF low 3 tRTC

∆THIGH ON_OFF high 3 tRTC

∆T3 Startup sequencing After ON_OFF 1024 tRTC

- ON_OFF to WAKEUP high After ON_OFF 6 tRTC

∆T5 ON_OFF to ARM start After ON_OFF 2130 tRTC

1 ∆T7 Main power source start WAKEUP high 0 30 300 tRTC

TABLE 13 – START-UP TIMING 21.2. VERIFYING THE MODULE HAS STARTED The ORG14XX module WAKEUP output will go logic high indicating the GPS processor has started. System activity indication depends upon the chosen ordering option. 01 and 02 ordering codes:  When active, the module will output NMEA messages at the 4800bps.  First NMEA message after power-up is ‘$PSRF150,1*3E’. 03 ordering code:  Since the module is SPI slave, there is no possible indication of system “ready” through SPI data interface.  The host must initiate SPI connection approximately 1 sec. after WAKEUP output goes high. 21.3. SHUTTING DOWN THE MODULE Transferring the ORG14XX series module into Hibernate state can be initiated in two ways: . By a pulse on the ON_OFF input when the ORG14XX module in Full Power state. . By serial message MID205 (OSP™) or $PSRF117 (NMEA). . Last message before Hibernate state is ‘$PSRF150,1*3F’. The orderly shutdown may take anywhere from 10ms to 900ms to complete, depending upon operation in progress and messages pending, and hence is dependent upon serial interface speed and controls.

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22. HANDLING INFORMATION 22.1. Product Packaging and Delivery

FEED DIRECTION

figure 10 - Carrier

ORG1408 A0 18.00 ± 0.1 B0 18.00 ± 0.1 K0 03.60 ± 0.1 F 14.20 ± 0.1 P1 24.00 ± 0.1 S0 28.40 ± 0.1 W 32.0 0.3 Table 14: Carrier dimensions [mm]

Carrier material: Conductive Polystyrene

Feed direction

Figure 11: Module position

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Figure 12: Reel

ØA 330.00 ± 0.85 ØN 60.00 ± 0.5 W1 33.00 ± 0.5 W2 39.00 ± 0.5 Table 15: Reel dimensions [mm] Reel material: Antistatic Plastic Each reel contains 250 or 500 modules.

22.2. ASSEMBLY The module supports automatic pick-and-place assembly and reflow soldering processes. Reflow soldering of the module on the component side of the motherboard PCB according to standard IPC/JEDEC J-STD-020D for LGA SMD. Suggested solder paste stencil is 5 mil to ensure sufficient solder volume.

FIGURE 13 – RECOMMENDED SOLDERING PROFILE

Page 29 of 32 Hotnetella – ORG1408 Datasheet Revision 2.1 June 5, 2016

Suggested peak reflow temperature is 250°C for 10 sec. for Pb-Free solder paste. Absolute Maximum reflow temperature is 260°C for 10 sec. 22.3. REWORK If localized heating is required to rework or repair the module, precautionary methods are required to avoid exposure to solder reflow temperatures that can result in permanent damage to the device. 22.4. ESD SENSITIVITY This product is ESD sensitive device and must be handled with care. 22.5. SAFETY INFORMATION Improper handling and use can cause permanent damage to the product. Avoid cleaning process in ultrasonic degreaser, since ultrasonic vibrations may cause performance degradation or destruction of internal circuitry. 22.6. DISPOSAL INFORMATION This product must not be treated as household waste. For more detailed information about recycling electronic components contact your local waste management authority.

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23. MECHANICAL SPECIFICATIONS The ORG14XX series module has advanced ultra-miniature packaging and a LGA SMD footprint. The ORG14XX series module PCB footprint size is 17mm x 17mm. The ORG1408 module is surface mount device packaged on a miniature printed circuit board with a metallic RF enclosure featuring miniature RF connector. There are 22 surface mount connection pads with a base metal of copper and an Electroless Nickel / Immersion Gold (ENIG) finish. The ORG14XX series module has been designed and packaged for automated pick and place assembly and reflow soldering processes. TOP VIEW SIDE VIEW BOTTOM VIEW

0.669 ± 0.008 0.669 ± 0.008 17.0 ± 0.2 17.0 ± 0.2 0.603

15.32

11 12

. 0

Ø 0.165 ± 0.008 0

7 5

4.2 ± 0.2 7

0 0 1 22 Pad 1 marking 0.025 inch 0.64 millimeter

FIGURE 14 – MECHANICAL DRAWING

Dimensions Length Width Height Weight mm 17.0 ± 0.2 17.0 ± 0.2 2.2 ± 0.1 gr 1.4 inch 0.669 ± 0.008 0.669 ± 0.008 0.088 ± 0.004 oz 0.1 TABLE 16 – MECHANICAL SUMMARY 24. COMPLIANCE The following standards are applied on the ORG14XX series modules production: . IPC-6011/6012 Class2 for PCB manufacturing . IPC-A-600 Class2 for PCB inspection . IPC-A-610D Class2 for SMT acceptability The ORG14XX series modules are being manufactured ISO 9001:2000 accredited facilities. The ORG14XX series modules are designed and being manufactured and handled to comply with and according with Pb-Free/RoHS Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment. The ORG14XX series modules comply with the following EMC standards: . EU CE EN55022:06+A1(07), Class B . US FCC 47CFR Part 15:09, Subpart B, Class B

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25. ORDERING INFORMATION ORG 1408 – R01 -TR XXX TR TR = Tape & Reel

Packaging option AD1 = Through Hole Adaptor UAR = Demo Board {

Firmware/Hardware option

Standard Series TRPremium = Tape & SeriesReel Ordering code ORG1408Packaging -optionR01 AD1ORG1408 = Through-PM Hole01 Adaptor Internal Switch Mode support  UAR = Demo Board Jammer Remover   ™ ™ CGEE and SGEE Firmware/Hardware option  ATP™, PTF™, APM™   Firmware SBAS (WAAS/EGNOS) {  Features MEMS sensors  support ABP™ support 

Table 17: Firmware options

Boot Option 01 Boot Option 02 Boot Option 03 Ordering code ORG1408-xx01 ORG1408-xx02 ORG1408-xx03 Power On State Full Power Hibernate Hibernate Host Interface UART UART SPI Interface settings on power 4,800 bps 4,800 bps Slave Data format on power NMEA NMEA NMEA Table 18: Hardware options

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