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TAS5751M SLASEC1B –MARCH 2016–REVISED MAY 2018 TAS5751M - Digital Input Audio Power Amplifier with EQ and 3-Band AGL 1 Features 2 Applications

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TAS5751M SLASEC1B –MARCH 2016–REVISED MAY 2018 TAS5751M - Digital Input Audio Power Amplifier with EQ and 3-Band AGL 1 Features 2 Applications Product Order Technical Tools & Support & Folder Now Documents Software Community TAS5751M SLASEC1B –MARCH 2016–REVISED MAY 2018 TAS5751M - Digital Input Audio Power Amplifier with EQ and 3-Band AGL 1 Features 2 Applications 1• Audio Input/Output • LCD TV, LED TV – One-Stereo Serial Audio Input • Low-Cost Audio Equipment – Supports 44.1-kHz and 48-kHz Sample Rates (LJ/RJ/I²S) 3 Description – Supports 3-Wire I²S Mode (no MCLK required) The TAS5751M device is an efficient, digital-input audio amplifier for driving stereo speakers configured – Automatic Audio Port Rate Detection as a bridge tied load (BTL). In parallel bridge tied – Supports BTL and PBTL Configuration load (PBTL) in can produce higher power by driving the parallel outputs into a single lower impedance – POUT = 25 W at 10% THD+N load. One serial data input allows processing of up to – PVDD = 20 V, 8 Ω, 1 kHz two discrete audio channels and seamless integration • Audio/PWM Processing to most digital audio processors and MPEG – Independent Channel Volume Controls With decoders. The device accepts a wide range of input Gain of 24 dB to Mute in 0.125-dB Steps data and data rates. A fully programmable data path routes these channels to the internal speaker drivers. – Programmable Three-Band Automatic Gain Limiting (AGL) The TAS5751M device is a slave-only device – 20 Programmable Biquads for Speaker EQ receiving all clocks from external sources. The TAS5751M device operates with a PWM carrier and Other Audio-Processing Features between a 384-kHz switching rate and a 288-kHz • General Features switching rate, depending on the input sample rate. – 106-dB SNR, A-Weighted, Referenced to Full Oversampling combined with a fourth-order noise Scale (0 dB) shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz. – I²C Serial Control Interface w/ two Addresses – Thermal, Short-Circuit, and Undervoltage Device Information(1) Protection PART NUMBER PACKAGE BODY SIZE (NOM) – Up to 90% Efficient TAS5751M HTSSOP (48) 12.50 mm × 6.10 mm – AD, BD, and Ternary Modulation (1) For all available packages, see the orderable addendum at – PWM Level Meter the end of the data sheet. Power vs PVDD 45 Simplified Block Diagram RL = 4 Ω DVDD AVDD PVDD 40 RL = 8 Ω Power-On Reset Internal Regulation and Power Distribution Internal Voltage Supplies 35 (POR) MCLK Monitoring and Watchdog Digital to PWM Open Loop Stereo 30 Converter Stereo PWM Amplifier (DPC) Serial Audio Port Sensing & Protection AMP_OUT_A MCLK (SAP) AMP_OUT_B Digital Audio Sample Rate 2 Ch. PWM 25 LRCK Temperature Sample Rate Processor Converter Modulator Short Circuits SCLK Auto-Detect (DAP) (SRC) PVDD Voltage Noise Shaping 20 SDIN PLL Output Current AMP_OUT_C Click & Pop AMP_OUT_D Suppression Fault Notification Output Power (W) 15 10 5 Internal Register/State Machine Interface Current Sourcing Limit EVM Thermal Limit I²C Control Port 0 8 12 16 20 24 PVDD (V) SCL SDA DR_SD PDN RST 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TAS5751M SLASEC1B –MARCH 2016–REVISED MAY 2018 www.ti.com Table of Contents 1 Features .................................................................. 1 7.2 Functional Block Diagram ....................................... 17 2 Applications ........................................................... 1 7.3 Audio Signal Processing Overview ......................... 18 3 Description ............................................................. 1 7.4 Feature Description................................................. 19 4 Revision History..................................................... 2 7.5 Device Functional Modes........................................ 22 7.6 Programming........................................................... 23 5 Pin Configuration and Functions ......................... 3 7.7 Register Maps......................................................... 34 6 Specifications......................................................... 5 8 Application and Implementation ........................ 52 6.1 Absolute Maximum Ratings ...................................... 5 8.1 Application Information............................................ 52 6.2 ESD Ratings ............................................................ 5 8.2 Typical Applications ............................................... 53 6.3 Recommended Operating Conditions....................... 5 6.4 Thermal Characteristics ............................................ 6 9 Power Supply Recommendations...................... 58 6.5 Electrical Characteristics........................................... 6 10 Layout................................................................... 59 6.6 Speaker Amplifier Characteristics............................ 7 10.1 Layout Guidelines ................................................. 59 6.7 Protection Characteristics ......................................... 7 10.2 Layout Example .................................................... 60 6.8 Master Clock Characteristics .................................... 7 11 Device and Documentation Support ................. 62 6.9 I²C Interface Timing Requirements ........................... 8 11.1 Trademarks ........................................................... 62 6.10 Serial Audio Port Timing Requirements.................. 8 11.2 Electrostatic Discharge Caution............................ 62 6.11 Typical Characteristics.......................................... 10 11.3 Glossary ................................................................ 62 7 Detailed Description ............................................ 17 12 Mechanical, Packaging, and Orderable 7.1 Overview ................................................................. 17 Information ........................................................... 62 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2016) to Revision B Page • Added PVDD to the Absolute Maximum Ratings table .......................................................................................................... 5 • Moved the units values From the MAX value column to the UNITS column in the I²C Interface Timing Requirements table ........................................................................................................................................................................................ 8 • Changed text "Multiplex channel 2 to AMP_OUT_D" To: Multiplex channel 2 to AMP_OUT_D" in the Functions column of Table 21 .............................................................................................................................................................. 49 Changes from Original (March 2016) to Revision A Page • Moved from Product Preview to Production Data release. ................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: TAS5751M TAS5751M www.ti.com SLASEC1B –MARCH 2016–REVISED MAY 2018 5 Pin Configuration and Functions DCA Package 48-Pin HTSSOP With PowerPAD™ Top View BSTRP_B 1 48 BSTRP_C AMP_OUT_B 2 47 AMP_OUT_C AMP_OUT_B 3 46 AMP_OUT_C PGND 4 45 PGND PGND 5 44 PGND AMP_OUT_A 6 43 AMP_OUT_D PVDD 7 42 PVDD PVDD 8 41 PVDD BSTRP_A 9 40 BSTRP_D SSTIMER 10 39 GVDD_REG PBTL 11 38 AVDD_REG NC 12 37 NC PowerPAD NC 13 36 NC PLL_GND 14 35 AGND PLL_FLTM 15 34 DGND PLL_FLTP 16 33 DVDD AVDD_REF 17 32 TEST AVDD 18 31 RST ADR/FAULT 19 30 NC MCLK 20 29 SCL OSC_RES 21 28 SDA OSC_GND 22 27 SDIN DVDD_REG 23 26 SCLK PDN 24 25 LRCLK Not to scale Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if ADR/FAULT 19 DI/DO pulled to AVDD. Also, if configured to be a fault output by the methods described in the Fault Indication section, this terminal will be pulled low when an internal fault occurs. Ground reference for analog circuitry (NOTE: This terminal should be connected to the AGND 35 P system ground) AMP_OUT_A 6 2 AMP_OUT_B 3 AO Speaker amplifier outputs 46 AMP_OUT_C 47 AMP_OUT_D 43 AVDD 18 P Power supply for internal analog circuitry Internal power supply (NOTE: This terminal is provided as a connection point for filtering AVDD_REF 17 P capacitors for this supply and must not be used to power any external circuitry) Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a AVDD_REG 38 P connection point for filtering capacitors for this supply and must not be used to power any external circuitry) BSTRP_A 9 BSTRP_B 1 Connection points to for the bootstrap capacitors, which are used to create a power P BSTRP_C 48 supply for the gate drive for the high-side device BSTRP_D 40 Ground reference for digital circuitry (NOTE: This terminal should be connected to the DGND 34 P system ground) DVDD 33 P Power supply for the internal digital circuitry (1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output Copyright © 2016–2018, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TAS5751M TAS5751M SLASEC1B –MARCH 2016–REVISED MAY 2018 www.ti.com Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a DVDD_REG 23 P connection point for filtering
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