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Design and Evaluation of an Auto-Memoization Processor

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Design and Evaluation of an Auto-Memoization Processor DESIGN AND EVALUATION OF AN AUTO-MEMOIZATION PROCESSOR Tomoaki TSUMURA Ikuma SUZUKI Yasuki IKEUCHI Nagoya Inst. of Tech. Toyohashi Univ. of Tech. Toyohashi Univ. of Tech. Gokiso, Showa, Nagoya, Japan 1-1 Hibarigaoka, Tempaku, 1-1 Hibarigaoka, Tempaku, [email protected] Toyohashi, Aichi, Japan Toyohashi, Aichi, Japan [email protected] [email protected] Hiroshi MATSUO Hiroshi NAKASHIMA Yasuhiko NAKASHIMA Nagoya Inst. of Tech. Academic Center for Grad. School of Info. Sci. Gokiso, Showa, Nagoya, Japan Computing and Media Studies Nara Inst. of Sci. and Tech. [email protected] Kyoto Univ. 8916-5 Takayama Yoshida, Sakyo, Kyoto, Japan Ikoma, Nara, Japan [email protected] [email protected] ABSTRACT for microprocessors, and it made microprocessors faster. But now, the interconnect delay is going major and the This paper describes the design and evaluation of main memory and other storage units are going relatively an auto-memoization processor. The major point of this slower. In near future, high clock rate cannot achieve good proposal is to detect the multilevel functions and loops microprocessor performance by itself. with no additional instructions controlled by the compiler. Speedup techniques based on ILP (Instruction-Level This general purpose processor detects the functions and Parallelism), such as superscalar or SIMD, have been loops, and memoizes them automatically and dynamically. counted on. However, the effect of these techniques has Hence, any load modules and binary programs can gain proved to be limited. One reason is that many programs speedup without recompilation or rewriting. have little distinct parallelism, and it is pretty difficult for We also propose a parallel execution by multiple compilers to come across latent parallelism. Another rea- speculative cores and one main memoing core. While main son is the limitations caused by other processor resources, core executes a memoizable region, speculative cores exe- for example, memory throughput. Even if the compilers cute the same region simultaneously. The speculative exe- can extract parallelism, the memory throughput restricts the cution uses predicted inputs. This can omit the execution issue width. Therefore, microprocessors are under the pres- of instruction regions whose inputs show monotonous in- sure of necessity of novel speedup techniques. crease or decrease, and may effectively use surplus cores Meanwhile, in the software field, memoization[1] is in coming many-core era. a widely used programming technique for speedup. It is The result of the experiment with GENEsYs: genetic storing the results of functions for later reuse, and avoids algorithm programs shows that our auto-memoization pro- recomputing them. As a speedup technique, memoization cessor gains significantly large speedup, up to 7.1-fold and has no relation to parallelism of programs. It depends upon 1.6-fold on average. Another result with SPEC CPU95 value locality, especially input values of functions. There- suite benchmarks shows that the auto-memoization with fore, memoization has a potential for breaking through the three speculative cores achieves up to 2.9-fold speedup stone wall the speedup techniques based on ILP have run for 102.swim and 1.4-fold on average. It also shows that into. the parallel execution by speculative cores reduces cache Memoization brings a good result on expensive func- misses just like pre-fetching. tions, but it requires being rewritten of target programs. KEY WORDS The traditional load-modules or binaries cannot enjoy memoization, computational-reuse, speculative multi- memoization. Furthermore, the effectiveness of memo- threading, CAM ization is influenced much by programmers. Rewriting programs using memoization occasionally makes the pro- grams slower. Memoization costs a certain measure of 1 Introduction overhead because it is implemented by software. We propose an auto-memoization processor which As semiconductors goes smaller, microprocessors are com- makes traditional load-modules faster without any software ing to the crossroads of speedup techniques. So far, the la- assist. There is no need to rewrite or recompile target pro- tency of microprocessors have been controlled by the gate grams. Our processor detects functions and loop iterations latencies. Hence, transistor scaling provided higher clock dynamically, and memoize them automatically. On-chip 551-051 245 functions loops Processor Core reuse func: : ALU test : : Memo : .LL3: Buf store return %x : main: : MemoTblL2RB : ba .LL3 call func : write : : Memoize back engine reuse test Figure 1. Memoizable Instruction Regions. write back D2$ D1$ Registers ternary CAM (Contents Addressable Memory) stores the inputs and outputs. The rest of this paper is organized as follows. The Figure 2. Structure of Auto-Memoization Processor. next section describes the design and behavior of auto- memoization processor, and Section 3 presents parallel ex- ecution model with speculative cores. Section 4 shows the result of experiments to evaluate the processor. After a Strictly speaking, the variable which is read and has not brief discussion of related work in Section 5, we conclude been written in the function is one of the inputs. If there this paper in Section 6 showing our future work. is a write access to a variable prior to read, the variable is not an input. Referring a variable can be observed as a read access to a register or main memory. Hence, the processor 2 Auto-Memoization Processor can hook the read accesses and detect variable references. Now, there is an exception. There is no need to treat 2.1 Outline function-local variables as inputs, even if they are referred in the function. That is to say, the processor need to dis- Our auto-memoization processor memoize all functions tinguish the accesses to local variables from the accesses to and loops. Figure 1 shows the memoizable instruction re- non-local variables. Generally, the operating system spec- gions. A region between the instruction with a callee label ifies the upper limit of the data/stack size statically. Our and return instruction is detected as a memoizable func- processor tells global variables from local variables by this tion. A region between a back branch instruction and its boundary, and tells parent-local variables from local vari- branch target is detected as a memoizable loop iteration. ables by the value of the stack pointer just before current This processor detects these memoizable regions automat- function is called. On the other hand, there is no way to ically and memoizes them. know local variables from non-local variables for loops. Figure 2 shows the structure of auto-memoization Therefore in loops, all referred variables are treated as in- processor. Memoization system consists of memoization puts. engine and memo table: MemoTbl. Processor core has Outputs can be also detected in a similar way. The also MemoBuf: a small writing buffer for MemoTbl. En- variables assigned in the instruction region are the outputs tering to the memoizable region, the processor refers to of the region, but the local variables are excluded. the MemoTbl (reuse test) and compares current inputs with former inputs which are stored in MemoTbl. If the current input set matches with one of the stored input sets on the 2.3 Memo Tables MemoTbl, the memoization engine write backs the stored outputs to cache and registers. This omits the execution of MemoBuf: Through the execution of an instruction re- the region and reduce whole execution time. gion, the processor stores the addresses and the values of If the current input set does not match with any past inputs/outputs to MemoBuf. Note that the memoizable re- input sets, processor stores the inputs and the outputs of the gions in programs are usually nested. Figure 3 shows a region into MemoBuf while executing the region as usual. simple example. A function B is called in another function At the end of the region, the memoization engine stores the A, and B uses global variables g, h as its inputs. When B contents of MemoBuf into MemoTbl for future reuse. is directly called, g and h are inputs only for B. When A is called, these variables g, h are inputs not only for B but also 2.2 Inputs / Outputs of Memoizable Region A. That is, the processor should memorize inputs/outputs of nested regions simultaneously. We make the depth of For memoing instruction regions, processor need to recog- MemoBuf six, and each MemoBuf line can store the one of nize what are the inputs and outputs of the regions dynam- the nested instruction regions. At the end of a region, the ically. The inputs of a function are not only its arguments corresponding line is popped from MemoBuf and copied but also the variables which are referred to in the function. into MemoTbl. 246 int main(){ Input tree int g = 4; main() int h = 2; PC/Reg.----1000 addr1 00110000 addr2 0121---- addr3 33------ int a = A( 3 ); g h } A() 3 02--22-- addr3 33------ addr4 int A(int x){ return B( x*2 ); B() 6 } int B(int x){ int b = x; PC/Reg. ----1000 7 04:33------ if( x > 3 ) b += g; 5 02:0121---- else cache b += h; 1 3 00:00110000 return b; } 2 00 FF ----1000 addr1 01 Figure 3. Nested functions.: The global variables g, h 4 02 00 00110000 addr2 should be treated as inputs not only for B but also A. 03 02 02--22-- addr3 6 04 02 0121---- addr3 05 8 06 04 33------ E Input tree: A series of inputs for a certain instruction re- Output gion can be represented as a sequence of the tuples each select of which contains an address and a value. In one instruc- CAM RAM tion region, the series of input addresses sometimes branch MemoTbl off from each other. For example, after a branch instruc- tion, what address will be referred next relies on whether Figure 4.
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