INA1620 Hi-Fidelity Audio Op Amplifier with Integrated Thin-Film

1 • • • • 2 • • • • • • • • • • • • 1 1 • INA1620 High-Quality Audio Analog Professional High-Fidelity Available Wide Short-Circuit and-Click Low-Power Low High High High 32 Wide – Ultra-low Ultra-low Integrated Matched Applications Features 119 intellectual An R4C R1C GND VCC VEE INA1620 MHz NC Quiescent IMPORTANT Open-Loop Capacitive-Load Slew dB Supply Gain Test and (G THD+N to Total Noise: in Noise: High-Fidelity 4mm X 4mm QFN EMI R4A R1A Rate: Bandwidth property and 1 k 1 k 1 k 1 k 1 = 0.004% Shutdown Digital Small Package Simplified Thin-Film Audio

Protection (HiFi) Range: +1000) Harmonic Filters Current:

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32 Operational this + Channel R3A R2A Ω Now Order Noise: Ω Load) data > /Ch) disclaimers. R3C R2C 600 OUT B OUT A EN NC sheet Pop- and pF Documents Technical addresses EMI Amplifier PRODUCTION Filters than operation allowing channel. of The audio create are mW – 2.8-nV/ amplifier. distortion, resistor The 3 device channels, crosstalk, The or eliminate (1) INA1620 119.2 availability, PART ± out 2 Amplitude (dBc) Description For at matched INA1620 œ œ œ œ œ INA1620 INA1620 5 output 180 160 140 120 100 œ œ œ œ V the circuits. 80 60 40 20 of With µ is √ all 0 NUMBER dB DATA. a to A. Software Tools & Hz pairs shutdown 5 1k 5 20k 15k 10k 5k 0 end the specified The available The click-and-pop to ± even high FFT: warranty, large and Shutdown at 18 noise power. of Integrated a amplifiers operates to integrates amplifier 1 has INA1620 the and V output standby 1 when freedom kHz Device -133.6 dBc (Second Harmonic) (SeconddBc -133.6 within on packages, number data kHz, density SBOS859B WQFN changes, a from mode. EMI The only unique and sheet. mode PACKAGE Community Support & overdriven current, achieves 32- over 0.004% – noise also to Information (24) 4 filtering current Frequency (Hz) Frequency 2.6 integrated 40 see with drives from – Thin-Film Ω of precision-matched use be MARCH ° is a internal C mA Load, the has very in specifically very when an to dual switched interactions package safety-critical and of a that a on-chip +125 2018 or ultra-low a very 32- wide supply 50 high-performance thin-film audio 4.00 shutdown overloaded. layout (1) BODY transitioning can – is Ω REVISED ° mW Resistors C. low, option mm typically supply load from with designed be operational current SIZE THD+N applications, for × INA1620 resistors between addendum 4.00 used thin-film JULY at normal a (NOM) lowest mode, range 150- This low- mm less into 2018 per C005 of to to INA1620 SBOS859B –MARCH 2018–REVISED JULY 2018 www.ti.com

Table of Contents

1 Features ...... 1 8 Application and Implementation ...... 20 2 Applications ...... 1 8.1 Application Information...... 20 3 Description ...... 1 8.2 Typical Application ...... 24 4 Revision History...... 2 8.3 Other Application Examples...... 27 5 Pin Configuration and Functions ...... 3 9 Power Supply Recommendations...... 28 6 Specifications...... 4 10 Layout...... 28 6.1 Absolute Maximum Ratings ...... 4 10.1 Layout Guidelines ...... 28 6.2 ESD Ratings...... 4 10.2 Layout Example ...... 28 6.3 Recommended Operating Conditions...... 4 11 Device and Documentation Support ...... 29 6.4 Thermal Information...... 4 11.1 Device Support...... 29 6.5 Electrical Characteristics: ...... 5 11.2 Documentation Support ...... 29 6.6 Typical Characteristics...... 7 11.3 Receiving Notification of Documentation Updates 29 7 Detailed Description ...... 15 11.4 Community Resources...... 29 7.1 Overview ...... 15 11.5 Trademarks ...... 30 7.2 Functional Block Diagram ...... 15 11.6 Electrostatic Discharge Caution...... 30 7.3 Feature Description...... 15 11.7 Glossary ...... 30 7.4 Device Functional Modes...... 18 12 Mechanical, Packaging, and Orderable Information ...... 30

4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2018) to Revision A Page

• First release of production-data data sheet ...... 1

5 Pin Configuration and Functions

RTW Package 24-Pin QFN Top View IN+ A IN+ A IN- R2B R2A R1A R1B

24 23 22 21 20 19

R1C 1 18 R2C

VCC 2 17 OUT A

GND 3 16 EN Thermal Pad

NC 4 15 NC

VEE 5 14 OUT B

R4C 6 13 R3C

7 8 9 10 11 12 R4B R4A IN- B IN- R3B R3A IN+ B IN+

Pin Functions PIN I/O DESCRIPTION NAME NO. GND 3 — Connect to ground EN 16 I Shutdown (logic low), enable (logic high) IN+ A 22 I Noninverting input, channel A IN- A 21 I Inverting input, channel A IN+ B 9 I Noninverting input, channel B IN- B 10 I Inverting input, channel B NC 4 — No internal connection NC 15 — No internal connection OUT A 17 O Output, channel A OUT B 14 O Output, channel B R1A 24 — Resistor pair 1, end point A R1B 23 — Resistor pair 1, center point R1C 1 — Resistor pair 1, end point C R2A 19 — Resistor pair 2, end point A R2B 20 — Resistor pair 2, center point R2C 18 — Resistor pair 2, end point C R3A 12 — Resistor pair 3, end point A R3B 11 — Resistor pair 3, center point R3C 13 — Resistor pair 3, end point C R4A 7 — Resistor pair 4, end point A R4B 8 — Resistor pair 4, center point R4C 6 — Resistor pair 4, end point C V+ 2 — Positive (highest) power supply V– 5 — Negative (lowest) power supply Thermal pad Exposed thermal die pad on underside; connect thermal die pad to V–.

6 Specifications

6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT

Supply voltage, VS = (V+) – (V–) 40 Voltage Input voltage (signal inputs, enable, ground) (V–) – 0.5 (V+) + 0.5 V Input differential voltage ±0.5 Input current (all pins except power-supply and resistor pins) ±10 mA Current Through each resistor 30 Output short-circuit(2) Continuous

Operating, TA –55 125

Temperature Junction, TJ 150 °C

Storage, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.

6.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Single-supply 4 36 Supply voltage, (V+) – (V–) V Dual-supply ±2 ±18 Current per resistor 15 mA Specified temperature –40 125 °C

6.4 Thermal Information INA1620 THERMAL METRIC(1) RTW (QFN) UNIT 24 PINS

RθJA Junction-to-ambient thermal resistance 33.7 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 26.5 °C/W

RθJB Junction-to-board thermal resistance 13.1 °C/W

ψJT Junction-to-top characterization parameter 0.3 °C/W

ψJB Junction-to-board characterization parameter 13.1 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 3.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: at TA = 25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO PERFORMANCE

G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 2 kΩ, 0.000025% 80-kHz measurement bandwidth –132 dB

G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 600 Ω, 0.000025% 80-kHz measurement bandwidth –132 dB

Total harmonic distortion + G = 1, f = 1 kHz, P = 10 mW, R = 128 Ω, 0.000071% THD+N OUT L noise 80-kHz measurement bandwidth –123 dB

G = 1, f = 1 kHz, POUT = 10 mW, RL = 32 Ω, 0.000158% 80-kHz measurement bandwidth –116 dB

G = 1, f = 1 kHz, POUT = 10 mW, RL = 16 Ω, 0.000224% 80-kHz measurement bandwidth –113 dB SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz), 0.000018%

G = 1, VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth –135 dB IMD Intermodulation distortion CCIF twin-tone (19 kHz and 20 kHz), G = 1, 0.000032% VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth –130 dB FREQUENCY RESPONSE G = 1000 32 GBW Gain-bandwidth product MHz G = 1 8 SR Slew rate G = –1 10 V/μs (1) Full-power bandwidth VO = 1 VP 1.6 MHz Overload recovery time G = –10 300 ns Channel separation (dual) f = 1 kHz 140 dB EMI filter corner frequency 500 MHz NOISE

Input voltage noise f = 20 Hz to 20 kHz 2.1 μVPP f = 10 Hz 6.5 (2) en Input voltage noise density f = 100 Hz 3.5 nV/√Hz f = 1 kHz 2.8 f = 10 Hz 1.6 In Input current noise density pA/√Hz f = 1 kHz 0.8 OFFSET VOLTAGE ±0.1 ±1 VOS Input offset voltage mV TA = –40°C to 125°C ±1.2 (2) dVOS/dT Input offset voltage drift TA = –40°C to 125°C -0.5 ±2.5 μV/°C PSRR Power-supply rejection ratio 0.1 3 μV/V INPUT BIAS CURRENT 1.2 2 I Input bias current μA B (2) TA = –40°C to 125°C 2.2 ±10 ±100 I Input offset current nA OS (2) TA = –40°C to 125°C ±140 INPUT VOLTAGE RANGE

VCM Common-mode voltage range (V–) + 1.5 (V+) – 1 V (V–) + 1.5 V ≤ V ≤ (V+) – 1 V, T = –40°C to 125°C, V CMRR Common-mode rejection ratio CM A S 108 127 dB = ±18 V

(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate. (2) Specified by design and characterization.

Electrical Characteristics: (continued) at TA = 25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT IMPEDANCE Differential 60k || 0.8 Ω || pF Common-mode 500M || 0.9 Ω || pF OPEN-LOOP GAIN

(V–) + 2 V ≤ VO ≤ (V+) – 2 V, RL = 32 Ω, VS = ± 5 V 114 120 AOL Open-loop voltage gain dB (V–) + 1.5 V ≤ VO ≤ (V+) – 1.5 V, RL = 600 Ω, VS = ± 18 V 120 136 OUTPUT No load 800 Positive rail RL = 600 Ω 1000 VO Voltage output swing from rail mV No load 800 Negative rail RL = 600 Ω 1000

IOUT Output current Figure 38 mA

ZO Open-loop output impedance Figure 40 Ω

ISC Short-circuit current VS = ±18 V +145 / –130 mA

CLOAD Capacitive load drive Figure 24 pF ENABLE PIN 0.82 V Logic high threshold V IH (2) TA = –40°C to 125°C 0.95 0.78 V Logic low threshold V IL (2) TA = –40°C to 125°C 0.65

IIH Input current VEN = 1.8 V 1.5 μA RESISTOR PAIRS Resistors in same pair 0.004% 0.02% Resistor ratio matching(3) (2) TA = –40°C to 125°C 0.023% Resistor ratio matching Resistors in same pair ±0.07 ±0.15 ppm/°C temperature coefficient Individual resistor value 0.84 1 1.15 kΩ Individual resistor temperature 2 20 ppm/°C coefficient POWER SUPPLY 2.6 3.3 Quiescent current VEN = 2 V, IOUT = 0 A mA I T = –40°C to 125°C(2) 4.2 Q (per channel) A VEN = 0 V, IOUT = 0 A 5 10 μA (3) Resistor ratio matching refers to the matching between the two 1-kΩ resistors in each resistor pair. There are four pairs on each INA1620: RXA, RXB, RXC and RXD, where X is the terminal connection number. See Resistor Tolerance for more details.

6.6 Typical Characteristics at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)

20 22 18 20 16 18 14 16 ) 14 12 % 12 10 10 8 Amplifiers (%) Amplifiers Amplifiers ( Amplifiers 8 6 6 4 4 2 2 0 0 0 0 -1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 100 200 300 400 500 600 700 800 900 -1.5 -1.4 -1.3 -1.2 -1.1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -900 -800 -700 -600 -500 -400 -300 -200 -100 1000

-1000 D027 D030 VOS (mV) VOS Drift (mV/èC) 9818 channels 50 channels

Figure 1. Input Offset Voltage Histogram Figure 2. Input Offset Voltage Drift Histogram 300 œ60 œ62 200 VCM = -16.5 V œ64 œ66 100 œ68

V) V) V = 17 V (µV)

( 0 œ70 OS OS OS V

V œ72 œ100 œ74 œ76 œ200 œ78 œ300 œ80 œ75 œ50 œ25 0 25 50 75 100 125 150 œ20 œ10 0 10 20

Temperature (°C) C001 VCM (V) C001 4 typical units

Figure 3. Input Offset Voltage vs Temperature Figure 4. Input Offset Voltage vs Common-Mode Voltage

100 10

10 1

+31

-31 Current Current Noise Spectral Density (pA/√Hz)

Voltage Voltage Noise Spectral Density (nV/√Hz) 1 0.1 1 10 100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M

Frequency (Hz) C307 Frequency (Hz) C306

Figure 5. Input Voltage Noise Spectral Density vs Frequency Figure 6. Input Current Noise Spectral Density vs Frequency

Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted) 1000

Source Resistor Noise Contribution 100

10 Total Noise 50 50 nV/div

1 Voltage Noise Contribution

Current Noise Contribution 0.1 Time (2 s/div) Voltage Noise Spectral Density (nV/√Hz) 10 100 1k 10k 100k 1M

C017 Source Resistance ( ) C302

Figure 7. 0.1-Hz to 10-Hz Noise Figure 8. Voltage Noise vs Source Resistance 18 140 225

16 120 VS = ±15V

) ) 14

P 100 180 12 80 10 60 135 8 Phase Phase (º) Gain Gain (dB) 40 6 VS = ±5V Output Output Amplitude (V 4 20 90

2 VS = ±2V 0

0 œ20 45 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M 100M

Frequency (Hz) C303 Frequency (Hz) C005

Figure 9. Maximum Output Voltage vs Frequency Figure 10. Open-Loop Gain and Phase vs Frequency 5.0 5.0 4.0 4.0 V = ±2 V S V = ±2 V 3.0 3.0 S 2.0 2.0 1.0 1.0 0.0 0.0 (µV/V) (µV/V) VS = ±18 V OL OL OL VS = ±18 V

A œ1.0 A œ1.0 œ2.0 œ2.0 œ3.0 œ3.0 œ4.0 œ4.0 œ5.0 œ5.0 œ75 œ50 œ25 0 25 50 75 100 125 150 œ75 œ50 œ25 0 25 50 75 100 125 150

Temperature (°C) C001 Temperature (°C) C001 600-Ω load 2-kΩ load

Figure 11. Open-Loop Gain vs Temperature Figure 12. Open-Loop Gain vs Temperature

Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted) 40

G = +10 0.01 -80 (dB) Noise + Distortion Harmonic Total G = -1, 600- Load G = -1 G = -1, 2k- Load G = +1 G = -1, 10k- Load G = +1, 600- Load 20 0.001 G = +1, 2k- Load -100 G = +1, 10k- Load Gain Gain (dB) 0 0.0001 -120

-20 Total Harmonic Distortion + Noise (%) 0.00001 -140 100 1k 10k 100k 1M 10M 20 200 2k 20k

Frequency (Hz) C004 Frequency (Hz) C004

3.5 VRMS, 80-kHz measurement bandwidth

Figure 13. Closed-Loop Gain vs Frequency Figure 14. THD+N Ratio vs Frequency

0.1 -60 (dB) Noise + Distortion Harmonic Total 0.1 -60 (dB) Noise + Distortion Harmonic Total G = -1, 128- Load G = -1, 32- Load G = -1, 16- Load 0.01 -80 0.01 -80 G = +1, 128- Load Inverting G = +1, 32- Load G = +1, 16- Load 0.001 -100 0.001 -100

0.0001 -120 0.0001 Noninverting -120

2k- Load

Total Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) 600- Load 0.00001 -140 0.00001 -140 20 200 2k 20k 0.01 0.1 1 10

Frequency (Hz) C004 Output Amplitude (VRMS) C004 10 mW, 80-kHz measurement bandwidth 1 kHz, 80-kHz measurement bandwidth

Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N Ratio vs Output Amplitude

0.1 -60 (dB) Noise + Distortion Harmonic Total 0.1 -60 2k- Load

32- Load (dB) Distortion Intermodulation

0.01 Inverting -80 0.01 -80

SMPTE 0.001 -100 0.001 -100

Noninverting 0.0001 -120 0.0001 -120 128- Load CCIF 32- Load Intermodulation Distortion (%)

Total Total Harmonic Distortion + Noise (%) 16- Load 0.00001 -140 0.00001 -140 0.01 0.1 1 10 0.001 0.01 0.1 1 10

Output Amplitude (VRMS) C004 Output Amplitude (VRMS) C004 1 kHz, 80-kHz measurement bandwidth 90-kHz measurement bandwidth

Figure 17. THD+N Ratio vs Output Amplitude Figure 18. Intermodulation Distortion vs Output Amplitude

Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted) -80 160 No Load PSRR+ 32- Load 140 600- Load -100 120 PSRR- 100

-120 80

60 Crosstalk (dB) -140 40

20 Power Power Supply Rejection Ratio (dB) -160 0 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M

Frequency (Hz) C004 Frequency (Hz) C115

Figure 19. Channel Separation vs Frequency Figure 20. PSRR vs Frequency (Referred to Input) 5 140 4 120 3 2 100 1 80 0 -1 60

-2 40 -3 20 -4 Common-mode Rejection Ratio (dB) Power-Supply Power-Supply Rejection Ratio (µV/V) -5 0 œ75 œ50 œ25 0 25 50 75 100 125 150 1 10 100 1k 10k 100k 1M 10M

Temperature (°C) C001 Frequency (Hz) C004

Figure 21. PSRR vs Temperature Figure 22. CMRR vs Frequency (Referred to Input) 1 90

0.8 V = ±2 V, (Vœ) +1.5 ≤ V ≤ (V+) œ 1 V 80 S CM G = +1 0.6 70 0.4 60 0.2 G = -1 50 0 40 -0.2 VS = ±18 V, (Vœ) +1.5 ≤ VCM ≤ (V+) œ 1V 30 -0.4 Phase Margin (º) 20 -0.6 -0.8 10 Common-Mode Common-Mode Rejection Ratio (µV/V) -1 0 œ75 œ50 œ25 0 25 50 75 100 125 150 0 200 400 600 800 1000

Temperature (°C) C001 Capacitive Load (pF) C308

Figure 23. CMRR vs Temperature Figure 24. Phase Margin vs Capacitive Load

10 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: INA1620 Copyright at Typical www.ti.com T A = 25 © 2018, ° Characteristics 5 V/div 5 V/div 2 mV/div C, V Texas S Figure Figure = ± Instruments Figure 18 V IN IN 27. V 25. V OUT V, IN IN Negative Small-Signal G and 29. = G Time (500 ms/div) ms/div) (500Time Time (200 ns/div) (200 Time Time (2.5Time Incorporated 1, No = R (continued) 10 – L 10 Phase = Overload mV 2 s/div) k Step Ω Reversal (unless V Response OUT Recovery otherwise Product Folder C017 C017 C017 noted) Links: INA1620 Input Bias Current (A) 0.9 1.1 1.2 1.3 1.4 1.5 1 œ

50 5 V/div 2 V/div Figure Figure œ 25 Figure 26. V 28. V SBOS859B OUT IN IN 55 510125 100 75 50 25 0 Large-Signal Submit Positive G 30. G Time (200 ns/div) (200 Time Temperature (ºC) Temperature = Time (2.5Time = 1, I B – Documentation – 10 vs 10 MARCH Overload V Temperature s/div) Step 2018 Response Recovery – REVISED Feedback INA1620 JULY IB+ IB- C017 C017 C304 2018 11 INA1620 SBOS859B –MARCH 2018–REVISED JULY 2018 www.ti.com

Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted) 5 1.5

1.4

4 A)

1.3 3 1.2

2 Input Input Bias Current ( Input Input Offset Current (nA) 1.1

1 1 œ50 œ25 0 25 50 75 100 125 -20 -10 0 10 20

Temperature (ºC) C305 Common-Mode Voltage (V) C001

VS = ±18 V

Figure 31. IOS vs Temperature Figure 32. IB vs Common-Mode Voltage 1.3 5 4.5 4

A) 1.25

3.5 VS = ±18 V 3 VS = ±2 V 1.2 2.5 (mA) Q I 2 1.5 1.15 Input Input Bias Current ( 1 0.5 1.1 0 -1.5 -1 -0.5 0 0.5 1 1.5 œ75 œ50 œ25 0 25 50 75 100 125 150

Common-Mode Voltage (V) C002 Temperature (°C) C001

VS = ±2 V

Figure 33. IB vs Common-Mode Voltage Figure 34. Quiescent Current vs Temperature 3 5

2.5 4 125ºC 85ºC 2

3 1.5 (mA) (mA) Q Q I I 2 -40ºC 25ºC 1

1 0.5

0 0 0 2 4 6 8 10 12 14 16 18 20 0.5 1 1.5 2

Supply Voltage (V) C001 Enable Voltage (V) C002

Figure 35. Quiescent Current vs Supply Voltage Figure 36. Quiescent Current vs Enable Voltage

Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted) 200 18 16 180 14 I , Source 160 SC 12

140 10 (V) (V) O (mA) 120 V 8 SC I 6 100 ISC, Sink 125°C 25°C 4

80 2 85°C œ40°C

60 0 œ75 œ50 œ25 0 25 50 75 100 125 150 0 20 40 60 80 100 120 140 160 180 200 I (mA) Temperature (°C) C001 O C001

Figure 37. Short-Circuit Current vs Temperature Figure 38. Positive Output Voltage vs Output Current 0 100 -2 125°C -4 25°C

-6 85°C

œ40°C )

-8 ( (V) (V) O O 10 O Z

V -10

-12

-14

-16

-18 1 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1k 10k 100k 1M 10M 100M I (mA) O C001 Frequency (Hz) C001

Figure 39. Negative Output Voltage vs Output Current Figure 40. Open-Loop Output Impedance vs Frequency 20 25 18 22.5 16 20 14 17.5 12 15 10 12.5 8 10 Resistors (%) Resistors Resistors (%) Resistors 6 7.5 4 5 2 2.5 0 0 0 925 930 935 940 945 950 955 960 965 970 975 980 985 990 995 0.02 -0.02 1000 1005 1010 1015 1020 1025 D026 0.004 0.008 0.012 0.016 D028 -0.016 -0.012 -0.008 -0.004 Resistance (W) 19635 resistors Resistor Ratio Matching Error (%) 19639 resistor pairs Figure 41. Resistor Absolute Value Histogram Figure 42. Resistor Pair Matching Histogram

Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted) 27.5 25 22.5 20 )

% 17.5 15 12.5 10 Resistor Pairs ( Pairs Resistor 7.5 5 2.5 0 0 -0.1 0.01 0.02 0.03 0.04 0.05 -0.15 -0.14 -0.13 -0.12 -0.11 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 D029 Resistor Ratio Matching Drift (ppm/èC) 64 resistor pairs

Figure 43. Resistor Pair Matching Drift Histogram

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Links: pins node œ single ground pair œ and when preserved

IN- B IN- A allows of INA1620 pin, is is output in to amplifier pairs microcontrollers. gain-stage made not the the pin. well. transitioning greatly deliver

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Feature Description (continued) INA1620 package allowing the resistor pairs to be used in multiple configurations. The nodes in the pair are protected from damage due to electrostatic discharge (ESD) events by diodes tied to the power supplies of the IC. For this reason, voltages beyond the power supplies cannot be applied to the resistors without forward- biasing the ESD protection diodes. The resistor pairs should not be used if there is no power applied to the INA1620. The configuration of the ESD protection diodes is shown in Figure 44.

V+ V+ V+

1 k 1 k RxA RxC

V- V- V- RxB Figure 44. ESD Protection Diodes on Each Resistor Pair

Although the resistor pairs and amplifier core are fabricated on the same silicon substrate, they can be used in separate circuits as long as the previously-mentioned voltage limits are observed. The functional state of the amplifier (enabled or shutdown) does not affect the resistor pair's performance.

7.3.2 Power Dissipation The INA1620 is capable of high output current with power-supply voltages up to ±18 V. Internal power dissipation increases when operating at high supply voltages. The power dissipated in the op amp (POPA) is calculated using Equation 1:

VOUT PVVIVVOPA=-()()++ OUT ì=- OUT OUT ì RL (1) In order to calculate the worst-case power dissipation in the op amp, the ac and dc cases must be considered separately. In the case of constant output current (dc) to a resistive load, the maximum power dissipation in the op amp occurs when the output voltage is half the positive supply voltage. This calculation assumes that the op amp is sourcing current from the positive supply to a grounded load. If the op amp sinks current from a grounded load, modify Equation 2 to include the negative supply voltage instead of the positive. 2 ≈’VV++ PPOPA(MAX _DC)== OPA ∆÷ «◊2 4RL (2) The maximum power dissipation in the op amp for a sinusoidal output current (ac) to a resistive load occurs when the peak output voltage is 2/π times the supply voltage, given symmetrical supply voltages: 2 ≈’2V++ 2∂ V PP==∆÷ OPA(MAX _ AC) OPA p 2 «◊p∂RL (3) The dominant pathway for the INA1620 to dissipate heat is through the package thermal pad and pins to the PCB. Copper leadframe construction used in the INA1620 improves heat dissipation compared to conventional materials. PCB layout greatly affects thermal performance. Connect the INA1620 package thermal pad to a copper pour at the most negative supply potential. This copper pour can be connected to a larger copper plane within the PCB using vias to improve power dissipation. Figure 45 shows an analogous thermal circuit that can be used for approximating the junction temperature of the INA1620. The power dissipated in the INA1620 is represented by current source PD; the ambient temperature is represented by voltage source 25ºC; and the junction-to-board and board-to-ambient thermal resistances are represented by resistors RθJB and RθBA, respectively. The board-to-ambient thermal resistance is unique to every application. The sum of RθJB and RθBA is the junction-to-ambient thermal resistance of the system. The value for junction-to-ambient thermal resistance reported in the Thermal Information table is determined using the JEDEC standard test PCB. The voltages in the analogous thermal circuit at the points TJ and TPCB represent the INA1620 junction and PCB temperatures, respectively.

Feature Description (continued)

,JB

TPCB

,BA PD

25ºC

Figure 45. Approximate Thermal System Model of the INA1620 Soldered to a PCB

7.3.3 Thermal Shutdown If the junction temperature of the INA1620 exceeds 175°C, a thermal shutdown circuit disables the amplifier in order to protect the device from damage. The amplifier is automatically re-enabled after the junction temperature falls below approximately 160°C. If the condition that caused excessive power dissipation has not been removed, the amplifier oscillates between a shutdown and enabled state until the output fault is corrected.

7.3.4 EN Pin The enable pin (EN) of the INA1620 is used to toggle the amplifier enabled and disabled states. The logic levels defining these two states are: VEN ≤ 0.78 V (shutdown mode), and VEN ≥ 0.82 V (enabled). These threshold levels are referenced to the device ground (GND) pin. The EN pin can be driven by a GPIO pin from the system controller, discrete logic gates, or can be connected directly to the V+ supply. Do not leave the EN pin floating because the amplifier is prevented from being enabled. Likewise, do not place GPIO pins used to control the EN pin in a high-impedance state because this placement also prevents the amplifier from being enabled. A small current flows into the enable pin when a voltage is applied. Using the simplified internal schematic shown in Figure 46, use Equation 4 to estimate the enable pin current:

VEN - 0.7 V IEN = 700 k (4) As illustrated in Figure 46, the EN pin is protected by diodes to the amplifier power supplies. Do not connect the EN pin to voltages outside the limits defined in the Specifications section.

To VCC Amplifier

500 k EN

VEE VCC 200 k

GND

VEE Figure 46. EN Pin Simplified Internal Schematic

Feature Description (continued) 7.3.5 GND Pin The inclusion of a ground (GND) pin in the INA1620 architecture allows the internal enable circuitry to be referenced to the system ground, eliminating the need for level shifting circuitry in many applications. The internal amplifier compensation capacitors are also referenced to this pin, greatly increasing the ac PSRR. For highest performance, connect the GND pin to a low-impedance reference point with minimal noise present. As shown in Figure 46, the GND pin is protected by ESD diodes to the amplifier power supplies. Do not connect the GND pin to voltages outside the limits defined in the Specifications section.

7.3.6 Input Protection The amplifier input pins of the INA1620 are protected from excessive differential voltage with back-to-back diodes, as Figure 47 shows. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain or G = +1 circuits, fast-ramping input signals can forward bias these diodes because the output of the amplifier cannot respond quickly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently limited, use an input series resistor (RI) or a feedback resistor (RF) to limit the signal input current. This input series resistor degrades the low-noise performance of the INA1620 and is examined in the Noise Performance section. Figure 47 shows an example configuration when both current-limiting input and feedback resistors are used.

–

Device Output

RI + Input

Figure 47. Pulsed Operation

7.4 Device Functional Modes The INA1620 has two operating modes determined by the voltage between the EN and GND pins: a shutdown mode (VEN ≤ 0.78 V) and an enabled mode (VEN ≥ 0.82 V). The measured datasheet performance parameters specified in the Typical Characteristics and Specifications sections are given with the amplifier in the enabled mode, unless otherwise noted.

7.4.1 Shutdown Mode When the EN pin voltage is below the logic low threshold, the INA1620 enters a shutdown mode with minimal power consumption. In this state the output transistors of the amplifier are not powered on. However, do not consider the amplifier output to be high-impedance. Applying signals to the output of the INA1620 while the device is in the shutdown mode can parasitically power the output stage, causing the INA1620 output to draw current. The INA1620 enable circuitry limits transients at the output when transitioning into or out of shutdown mode. However, small output transients do still accompany this transition, as illustrated in Figure 48 and Figure 49. Note that in both figures the time scale is 1 µs per division, indicating that the output transients are extremely brief in nature, and therefore not likely to be audible in headphone applications.

Device Functional Modes (continued)

Enable (2 V/div) Enable (2 V/div) Voltage Voltage Voltage Voltage

Output (20 mV/div) Output (20 mV/div)

Time (1 s/div) Time (1 s/div)

C001 C002 Figure 48. INA1620 Output Voltage When EN Pin Figure 49. INA1620 Output Voltage When EN Pin Transitions High (32-Ω Load Connected) Transitions Low (32-Ω Load Connected)

7.4.2 Output Transients During Power Up and Power Down To minimize the possibility of output transients that might produce an audible click or pop, ramp the supply voltages for the INA1620 symmetrically to their nominal values. Asymmetrical supply ramping can cause output transients during power up that can be audible in headphone applications. If possible, hold the EN pin low while the power supplies are ramping up or down. If the EN pin is not being independently controlled (for example, by a GPIO pin), use a voltage divider to hold the enable pin voltage below the logic-high threshold until the power supplies reach the specified minimum voltage, as shown in Figure 50.

VCC

22.1 k

To enable pin on IC

10.7 k

Figure 50. Voltage Divider Used to Hold Enable Low at Power-Up or Power-Down

8 Application and Implementation

NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information The low noise and distortion of the INA1620 make the device useful for a variety of applications in professional and consumer audio products. However, these same performance metrics also make the INA1620 useful for industrial, test-and-measurement, and data-acquisition applications. The example shown here is only one possible application where the INA1620 provides exceptional performance.

8.1.1 Noise Performance Figure 51 shows the total circuit noise for varying source impedances with the op amp in a unity-gain configuration (no feedback resistor network, and therefore no additional noise contributions). The INA1620 is shown with total circuit noise calculated. The op amp contributes both a voltage noise component and a current noise component. The voltage noise is commonly modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying component of the input bias current, and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The low voltage and current noise of the INA1620 internal op amps make the device an excellent choice for use in applications where the source impedance is less than 10 kΩ as shown in Figure 51.

1000

Source Resistor Noise Contribution 100

10 Total Noise

1 Voltage Noise Contribution

Current Noise Contribution 0.1 Voltage Voltage Noise Spectral Density (nV/√Hz) 10 100 1k 10k 100k 1M

Source Resistance ( ) C302 Figure 51. Noise Performance of the INA1620 Internal Amplifiers

Application Information (continued) 8.1.2 Resistor Tolerance The INA1620 integrated resistor pairs use an advanced thin film process to create resistor pairs that have excellent matching. Each specific resistor pair is specifically designed for accurate matching between the two resistors. Figure 42 shows the distribution of resistor matching for a typical device population. The equation used to calculate matching between resistors in a pair is shown in Equation 5. RR- Resistor Ratio Matching () %=ìXA XB 100 Average () RXA ,R XB (5) In addition to excellent matching between resistors in each resistor pair, all resistors on a single INA1620 achieve good matching due to inherent process matching across each device. Figure 52 shows a typical distribution of the worst-case matching across all resistors on a single INA1620. The matching was calculated using the highest value resistance on a device matched with the lowest resistance value on the same device.

22 20 18 16

) 14 % 12 10

Devices ( Devices 8 6 4 2 0 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 D032 Resistor Matching, Maximum to Minimum (%) Figure 52. Matching Histogram, Maximum to Minimum

8.1.3 EMI Rejection The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for the following three reasons: • Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the supply or output pins. • The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit approximately matching EMIRR performance. • EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input terminal with no complex interactions from other components or connecting PCB traces. High-frequency signals conducted or radiated to any pin of the operational amplifier result in adverse effects, as the amplifier does not have sufficient loop gain to correct for signals with spectral content outside its bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC offsets, transient voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes from noisy radio signals and digital clocks and interfaces. The EMIRR IN+ of the INA1620 amplifiers is plotted versus frequency as shown in Figure 53. See also EMI Rejection Ratio of Operational Amplifiers, available for download from www.ti.com.

Application Information (continued)

70 65 60 55 50 45 40 35 30 25 EMIRR IN+ (dB) IN+ EMIRR 20 15 10 5 0 100M 1G 10G Frequency (Hz) D033 Figure 53. INA1620 EMIRR IN+

Table 1 lists the EMIRR IN+ values for the INA1620 at particular frequencies commonly encountered in real- world applications. Applications listed in Table 1 may be centered on or operated near the particular frequency shown. This information may be of special interest to designers working with these types of applications, or working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, and medical (ISM) radio band.

Table 1. INA1620 EMIRR IN+ for Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ Global system for mobile communications (GSM) applications, radio communication, navigation, 900 MHz 18 dB GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 33 dB 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and 2.4 GHz 26 dB medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 40 dB 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite 5 GHz 55 dB operation, C-band (4 GHz to 8 GHz)

8.1.4 EMIRR +IN Test Configuration Figure 54 shows the circuit configuration for testing the EMIRR IN+. An RF source connects to the op amp noninverting input pin using a transmission line. The op amp is configured in a unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the op amp input causes a voltage reflection; however, this effect is characterized and accounted for when determining the EMIRR IN+. A multimeter samples and measures the resulting DC offset voltage. The LPF isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.

Ambient temperature: 25˘C

+VS

œ 50 Low-Pass Filter +

RF source -VS DC Bias: 0 V Sample / Modulation: None (CW) Averaging Digital Multimeter Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF supply decoupling

Figure 54. EMIRR +IN Test Configuration

8.2 Typical Application The low distortion and high output-current capabilities of the INA1620 make this device an excellent choice for headphone-amplifier applications in portable or studio applications. These applications typically employ an audio digital-to-analog converter (DAC) and a separate headphone amplifier circuit connected to the DAC output. High- performance audio DACs can have an output signal that is either a varying current or voltage. Voltage output configurations require less external circuitry, and therefore have advantages in cost, power consumption, and solution size. However, these configurations can offer slightly lower performance than current output configurations. Differential outputs are standard on both types of DACs. Differential outputs double the output signal levels that can be delivered on a single, low-voltage supply, and also allow for even-harmonics common to both outputs to be cancelled by external circuitry. A simplified representation of a voltage-output audio DAC is shown in Figure 55. Two ac voltage sources (VAC) deliver the output signal to the complementary outputs through their associated output impedances (ROUT). Both output signals have a dc component as well, represented by dc voltage source VDC. The headphone amplifier circuit connected to the output of an audio DAC must convert the differential output into a single-ended signal and be capable of producing signals of sufficient amplitude at the headphones to achieve reasonable listening levels.

100 pF

ROUT 1 k 1 k

5V VAC œ Headphone Output

+ + VDC VAC -5V

ROUT

1 k 1 k

Audio DAC INA1620

100 pF Figure 55. INA1620 Used as a Headphone Amplifier for a Voltage-Output Audio DAC

8.2.1 Design Requirements • ±5-V power supplies • 150-mW output power (32-Ω load) • < –110-dB THD+N at maximum output (32-Ω load) • < 0.01-dB magnitude deviation (20 Hz to 20 kHz)

8.2.2 Detailed Design Procedure Figure 55 shows a schematic of a headphone amplifier circuit for voltage output DACs. An op amp is configured as a difference amplifier that converts the differential output voltage to single-ended. The gain of the difference amplifier in Figure 55 is determined by the resistor values, and includes the output impedance of the DAC. For R2 = R4 and R1 = R3, the output voltage of the headphone amplifier circuit is shown in Equation 6:

R2 VVOUT= DAC RR1+ OUT (6) The output voltage required for headphones depends on the headphone impedance, as well as the headphone efficiency (η), a measure of the sound pressure level (SPL, measured in dB) for a certain input power level (typically given at 1 mW). The headphone SPL at other power levels is calculated using Equation 7:

Typical Application (continued)

≈’PIN SPL(dB)=h+ 10log∆÷ «◊1 mW where • η = efficiency

• PIN = input power to the headphones (7) Figure 56 shows the input power required to produce certain SPLs for different headphone efficiencies. Typically, over-the-ear style headphones have lower efficiencies than in-ear types with 95 dB/mW being a common value.

150

140

130

120

110

100 90-dB/mW 90 95-dB/mW

Sound Sound Pressure Level (SPL, dB) 100-dB/mW 80 105-dB/mW 70 110-dB/mW 115-dB/mW 60 0.01 0.1 1 10 100 1000 Input Power (mW)

C001 Figure 56. Sound Pressure Level vs Input Power for Headphones of Various Efficiencies

In-ear headphones can have efficiencies of 115 dB/mW or greater, and therefore have much lower power requirements. The output power goal for this design is 150 mW — sufficient power to produce extremely loud sound pressure levels in a wide range of headphones. A 32-Ω headphone impedance is used for this requirement because 32 Ω is a very common value in headphones for portable applications. Equation 8 shows the voltage required for 32-Ω headphones: 2.191 V VO =ì= P R 150 mW ì 32 = RMS (8)

Capacitors C1 and C2 limit the bandwidth of the circuit to prevent the unnecessary amplification of interfering signals. The maximum value of these capacitors is determined by the limitations on frequency response magnitude deviation detailed in the Design Requirements section. C1 and C2 combine with resistors R2 and R4 to form a pole, as shown in Equation 9: 1 f = P p 2 (R2 ,R 4 )(C,C 1 2 ) (9) Calculate the minimum pole frequency allowable to meet the magnitude deviation requirements using Equation 10: f 20 kHz fP í í í 416.6 kHz 22 ≈’11 ≈ ’ ∆÷--11 ∆ ÷ «◊G « 0.999 ◊

where • G represents the gain in decimal for a –0.01-dB deviation at 20 kHz. (10)

Typical Application (continued)

Use Equation 11 to calculate the upper limit for the value of C1 and C2 in order to meet the goal for minimal magnitude deviation at 20 kHz. 11 C,C Ç Ç Ç 382 pF 12 pp 2 (R2 ,R 4 )F P 2 (1 k )(416.6 kHz) (11) For this design, 100-pF capacitors were used because they meet the design requirements for amplitude deviation in the audio bandwidth.

8.2.3 Application Curves Figure 57 shows the maximum output voltage achievable for a 32-Ω load before the onset of clipping (±5-V supplies), indicated by a sharp increase in distortion. As more current is delivered by the output transistors of an amplifier, additional distortion is produced. At low frequencies, this distortion is corrected by the feedback loop of the amplifier. However, as the loop gain of the amplifier begins to decline at high frequencies, the overall distortion begins to climb. The unique output stage design of the INA1620 greatly reduces the additional distortion at high frequency when delivering large currents, as shown in Figure 58. High-ordered harmonics (above the 2nd and 3rd) are also kept to a minimal level at high output powers, as shown in Figure 59.

-60 -80 Left Channel -82 Left Channel Right Channel -84 Right Channel -70 -86 -88 -80 -90 -92 -94 -90 -96 -98 -100 -100 -102 -104 -110 -106

Total Total Harmonic Distortion (dB) + Noise Total Harmonic Distortion (dB) + Noise -108 -120 -110 0.01 0.1 1 55 10 100 1k 10k Output Level (Vrms) Frequency (Hz)

22.4-kHz measurement bandwidth 90-kHz measurement bandwidth, 1-VRMS output

Figure 57. THD+N vs Output Voltage for a 32-Ω Load Figure 58. THD+N vs Frequency for a 32-Ω Load

0 -10 -20 -30 -40 -50 -60 -70 -80 -90

Amplitude (dBV) Amplitude -100 -110 -120 -130 -140 -150 0 5000 10000 15000 20000 Frequency (Hz)

1 kHz, 32-Ω load, 1 VRMS

Figure 59. Output Spectrum

8.3 Other Application Examples

8.3.1 Preamplifier for Professional Microphones Figure 60 shows a preamplifier designed for high performance applications that require low-noise and high common-mode rejection. Both channels of the INA1620 are configured as a two-op amp instrumentation amplifier with a variable gain from 6 to 40 dB. The excellent matching of the integrated 1kΩ resistors allows for high common-mode rejection in the circuit. An OPA197 is configured as a buffered power supply divider to provide a biasing voltage to the circuit, allowing the system to operate properly on a single 9-V battery. The additional components at the INA1620 inputs are for phantom power, EMI, and ESD protection.

9 V 9 V

0.1 F 100 k OPA197

+ VBIAS œ

100 k 1 F 10-k Potentiometer (Logarithmic) 20

VBIAS R2B R3B 48 V Phantom Power R2A 1 k 1 k R2C R3A 1 k 1 k R3C

9 V 9 V 0.1 F

47 k 10 V VCC OUTA IN-B 6.8 k 6.8 k D1 D2 IN-A 47 F œ œ 68 47 F Microphone INA1620 Output Input + + OUTB 68 30 100 IN+A VBIAS 47 k pF 2.2 k GND IN+B 2 100 1 pF 3 22 k 100 2.2 k pF 68 30

Figure 60. Preamplifier for Professional Microphones

9 Power Supply Recommendations The INA1620 operates from ±2-V to ±18-V supplies, while maintaining excellent performance. However, some applications do not require equal positive and negative output voltage swing. With the INA1620, power-supply voltages do not need to be equal. For example, the positive supply could be set to 25 V with the negative supply at –5 V. In all cases, the common-mode voltage must be maintained within the specified range. Key parameters are specified over the temperature range of TA = –40°C to 125°C. Parameters that vary with operating voltage or temperature are shown in the Typical Characteristics section.

10 Layout

10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply applications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry, because noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp specifically. • Connect the device ground pin to a low-impedance, low-noise, system reference point, such as an analog ground. • Place the external components as close to the device as possible. As shown in Figure 61, keep feedback resistors close to the inverting input to minimize parasitic capacitance and the feedback loop area. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).

10.2 Layout Example

IN- Minimize capacitance IN+ at amplifier inputs

Minimize feedback GND 1 k 1 k loop area

1 k EMI Filtering 1 k Place bypass capacitors as close to OUT A VCC OUT

IC as possible + œ

GND EN GND IC ground pin connected to low- NC NC impedance, low-noise system ground + œ VEE OUT OUT B

1 k EMI Filtering 1 k

GND 1 k 1 k

IN+

IN- Copper pour for thermal pad must be connected to negative supply (VEE) Figure 61. Board Layout for a Difference Amplifier Configuration

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 TINA-TI™ (Free Software Download) TINA-TI software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI software is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI software offers extensive post- processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder.

11.1.1.2 TI Precision Designs TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.

11.2 Documentation Support

11.2.1 Related Documentation For related documentation see the following: • Feedback Plots Define Op Amp AC Performance • Circuit Board Layout Techniques, SLOA089 • Headphone Amplifier for Voltage-Output Audio DACs Reference Design • Stabilizing Difference Amplifiers for Headphone Applications • Reducing Distortion from CMOS Analog Switches • EMI Rejection Ratio of Operational Amplifiers • HiFi Audio Circuit Design

11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, find the device product folder on ti.com. In the upper right corner, click on Alert me to receive a weekly digest of any product information that has changed. For change details, see the revision history included in any revised document.

11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.5 Trademarks E2E is a trademark of Texas Instruments. TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. DesignSoft is a trademark of DesignSoft, Inc. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) INA1620RTWR ACTIVE WQFN RTW 24 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 INA1620 & no Sb/Br) INA1620RTWT ACTIVE WQFN RTW 24 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 INA1620 & no Sb/Br)

(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. 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IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non- compliance with the terms and provisions of this Notice.

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