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View of This Work INFORMATION TO USERS The most advanced technology has been used to photo­ graph and reproduce this manuscript from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction. In the unlikely event that the author did not send UMI a complete manuscript and there are missing pages, these will be noted. Also, if unauthorized copyright material had to be removed, a note will indicate the deletion. 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University Microfilms International A Bell & Howell Information Company 300 North Zeeb Road, Ann Arbor, Ml 48106-1346 USA 313/761-4700 800/521-0600 Order Number 8824450 Performance evaluation of RISC-based architectures for image processing Al-Ghitany, Nashat El-Khameesy, Ph.D. The Ohio State University, 1988 Copyright ©1988 by Al-Ghitany, Nashat El-Khameesy. All rights reserved. UMI 300 N. Zeeb Rd. Ann Arbor, MI 48106 PERFORMANCE EVALUATION OF RISC-BASED ARCHITECTURES FOR IMAGE PROCESSING ■ A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of the Ohio^'State University by Nashat El-Khameesy Al-Ghitany, B.S., M.S. ***** The Ohio State University 1988 Dissertation Committee: Approved by: Jogakidal M. Jagadeesh Fiisun Ozgiiner Adviser Department of Electrical P. Sadayappan Engineering Copyright by Nashat El-Khameesy Al-Ghitany 1988 To my beloved wife, son, mother and the memory of my father ACKNOWLEDGEMENTS I would like to express my sincere gratitude to my advisor Professor Jogikal M. Jagadeesh for his guidance, encouragement and patience throughout my re­ search. He has given me unlimited support towards refining my research ideas and developing a broad knowledge in all the related areas to my research. I am grateful for Professor Fusun Ozgiiner for advising me during my course work. Her encouragement and continuous support has helped my progress in the PhD program during the beginning of studies at the Ohio State University. Thanks are also due to her careful review of this work. My sincere appreciation is due to Professor P. Sadayappan for the useful discussions and suggestions on the last chapter of this dissertation. I would like also to thank him for his review of this work. Thanks are due to all the faculty and friends at The Electrical Engineering Department, Ohio State University for their support and the valuable knowledge they passed genrously to me. Special thanks for Phil Cooper, Jake Glower, Tony Tzes and Farshad Khorrami for their sincere assistance and moral support during the preparation of this work. Special thanks are due to my wife Iman and my son Wesam for their moral support and patience for not seeing me as often as they should. Finally my thanks are due to the Egyptian Military for giving me the opportunity to pursue my graduate studies at a great institution. VITA January 16, 1953 ......................................... Born - Mansoura, Egypt 1974 ...............................................................B.S., Electrical Engineering, B.S., Military Science, Military Technical College, Cairo, Egypt 1980 ...............................................................M.S., Computer Engineering, Cairo University, Egypt 1978- 1983 ................................................. Graduate Research and Teaching Asso­ ciate Military Technical College, Cairo, Egypt 1983- 1988 ................................................... Graduate Student, Departement Of Electrical Engineering The Ohio State University, USA PUBLICATIONS “Fault Detection In Digital Computer Circuits,” Master thesis, Cairo Univer­ sity, Cairo, Egypt, 1980. “A RISC-Approach For Image Processing Architectures,” IProceeding of the 13th Northeast Bioengineering Conference, Philadelphia, Pennselvania, March 12- 13, 1987. “ Performance Evaluation Methodology Of Enhanced RISC Architectures For Image Processing,” The European Computer Simulation Multiconference, Nice, France, June 4-7, 1988. “ Performance Simulation Methodology Of Enhanced RISC Architectures For Image Processing,” SCS Summer Computer Simulation Conference, Seatle, Washington, July 16-19, 1988. FIELDS OF STUDY Major Field: Electrical Engineering Studies in Computer Engineering: Professor j. M. Jagadeesh Professor K. Breeding Professor K. W. Olson. Professor F. Ozgiiner Studies in Computer and Information Science: Professor P. Sadayappan, Professor Y. Lee Professor P. Ashok. Studies in Control Engineering: Professor R. Fenton. Professor R. Mayhan. Studies in Biomedical Engineering: Professor H. Weed Professor R. Campbell TABLE OF CONTENTS ACKNOWLEDGEMENTS VITA iv LIST OF FIGURES x LIST OF TABLES xii I. INTRODUCTION 1 1.1 B a c k g ro u n d ............................................................................................... 1 1.2 Organization Of The Dissertation ....................................................... 4 II. IMAGE PROCESSING ARCHITECTURES : REQUIREMENTS AND EXISTING SYSTEMS 7 2.1 In tro d u c tio n ............................................................................................... 7 2.2 General-Image-Processing, GIP :An Overview .................................. 8 2.3 Image-Processing Requirements ........................................................... 9 2.3.1 Image-Processing Levels .......................................................... 12 2.3.2 Matching The Algorithm Requirements onto Architecture 14 2.4 Architectures For Image Processing .................................................... 21 2.4.1 Classification of IP System Architectures ........................ 21 2.4.2 Cellular Array Processors, SIMD Architectures .............. 24 2.4.3 Pipelined Architectures .......................................................... 28 2.4.4 Systolic-Designs .......................................................................... 29 2.4.5 Multiprocessors ........................................................................ 30 2.4.6 Hierarchical Architectures For Image Processing .... 33 2.4.7 Pyramid Architectures ............................................................. 36 III. Reduced Instruction Set Computers (RISC): an Overview 40 3.1 Introduction ............................................................................................... 40 3.2 History of Reduced-Instruction-Set Computers ........................... 41 3.3 RISC COMMON DESIGN CONSTRAINTS.................................. 45 3.4 RISCs versus CISCs: An Ongoing D ebate ..................................... 47 3.4.1 Issues for D e b a te ........................................................................ 47 3.4.2 Hardware Complexity, Time, and Code Compactness . 49 3.4.3 High Level Language Support .......................................... 57 3.4.4 Efficient Pipelining .............................................................. 62 3.4.5 LOAD/STORE Architectures ............................................ 65 3.4.6 RISCs And Current Technology ....................................... 66 IV. The PROBLEM FORMULATION AND PRIMARY INVES­ TIGATIONS 09 4.1 Problem Formulation ............................................................ 70 4.1.1 Motivations Of The Research T opic ..................... 71 4.1.2 Main Addressed Problems .................................... 73 4.1.3 The Main Approach and Research Phases .... 74 4.2 Investigation of Image-Processing O perations ............................... 77 4.2.1 Data-Structure : Type, Size and A ccess ...................... 78 4.2.2 Anatomy of Image Operations ........................................... 80 4.2.3 Basic IP- Transform Operations ....................................... 86 vii 4.3 Distribution of Software Metrics Over Common Image Process­ ing T a s k s ...........................................................................................................88 4.4 Statistical Program Measurements ..................................................... 90 4.4.1 Program Measurements on Microprocessor-Based Systems 93 4.4.2 Measurements On Specialized IP- Architectures .... 96 4.4.3 Common High-Level Non-Primitives ........................ 100 4.4.4 Study Of Some Fortran Control-Procedures ................... 104 4.4.5 Source-Code Profiling Exam ples ................................ 106 4.5 Summary ................................................................................................... 109 V. SIMULATION MODELLING AND METHODOLOGY OF PERFORMANCE EVALUATION 112 5.1 Simulation Methodology
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