2010 International Conference on Field Programmable Logic and Applications An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier Malte Baesler, Sven-Ole Voigt, Thomas Teufel Institute for Reliable Computing Hamburg University of Technology Schwarzenbergstr. 95, D-21073 Hamburg
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[email protected] 0 Abstract—Decimal floating point operations are important for Ax1BCD-4221 P BCD-4221 ABCD-8421 Ax2BCD-4221 1 P BCD-4221 SBCD-8421 applications that cannot tolerate errors from conversions between Ax3BCD-4221 binary and decimal formats, for instance, scientific, commercial, p digits 2p digits Ax4BCD-4221 CPA CSAT ... PPMux p+1 and financial applications. In this paper we present an IEEE MMGen Ax5BCD-4221 P BCD-4221 754-2008 compliant parallel decimal floating-point multiplier de- B' BCD-4221 signed to exploit the features of Virtex-5 FPGAs. It is an extension B'signs Ss_BCD-4221 to a previously published decimal fixed-point multiplier. The 2p BCD-8421 Sw_BCD-4221 decimal floating-point multiplier implements early estimation of B NDCBCD-4221 p digits 2p the shift-left amount and efficient decimal rounding. Additionally, DRec it provides all required rounding modes, exception handling, over- NegDC flow, and gradual underflow. Several pipeline stages can be added Fig. 1. Parallel fixed-point multiplier to increase throughput. Furthermore, different modifications are analyzed including shifting by means of hard-wired multipliers and delayed carry propagation adders. II. DECIMAL FIXED-POINT MULTIPLIER I. INTRODUCTION The Decimal Fixed-Point Multiplier (DFixMul) computes the product A · B of the unsigned decimal multiplicand A Numerical problems are usually formulated in decimal and multiplier B, both with the same precision p.