DOCSLIB.ORG

Chang-Hong Wu Distinguished Engineer, Juniper Networks the INTERNET EXPLOSION

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Chang-Hong Wu Distinguished Engineer, Juniper Networks the INTERNET EXPLOSION ASICS: THE HEART OF MODERN ROUTERS Chang-Hong Wu Distinguished Engineer, Juniper Networks THE INTERNET EXPLOSION # Web Sites 130EB/yr Internet Capacity 162M # Connected Devices 1B Total Digitized Information 420EB # Google Searches/Month 100M 31B/mo 12EB/yr 40M 110EB 4PB/yr 60PB/yr 9.5M 160M 25M 33K 1 1.7M 2.7B/mo 1988 1993 1998 2003 2008 Exponential growth, no matter how you measure it! The clearest indication of value delivered to end-users 2 Copyright © 2010 Juniper Networks, Inc. DRIVING FORCE BEHIND EXPONENTIAL GROWTH C S C S N C S Information N System N Digital Stored Pipelining Microprocessor Multi-core Computing Program Computing Digital Circuit Packet TCP/IP Transmission Switching Switching HPN Networking Flash Digital Core Disk DRAM Storage Memory Storage 3 Copyright © 2010 Juniper Networks, Inc. COMPUTER PERFORMANCE: 1988-2008 228 500,000 X over 20 years 226 224 222 220 218 System CAGR: 1.9x /year 216 214 12 2 Super Computers 210 28 26 Megahertz Megahertz / MFlops 24 Microprocessor CAGR: 1.3x /year 22 20 „88 „89 „90 „91 „92 „93 „94 „95 „96 „97 „98 „99 „00 „01 „02 „03 „04 „05 „06 „07 „08 4 Copyright © 2010 Juniper Networks, Inc. ROUTER PERFORMANCE 1988 – 2008 1000,000 X over 20 years (2x /year) 224 Post-ASIC era: 2.2x /year TX T1600 222 220 T640 M160 218 Pre-ASIC era: 1.6x /year M40 216 214 212 Interface CAGR: 1.7x /year 210 28 26 Megabits per second 24 22 20 „88 „89 „90 „91 „92 „93 „94 „95 „96 „97 „98 „99 „00 „01 „02 „03 „04 „05 „06 „07 „08 5 Copyright © 2010 Juniper Networks, Inc. SILICON THE FOUNDATION OF PERFORMANCE General-Purpose Microprocessor (G) Services Engine (S) Edge Engine Core (E) Fabric Engine Engine (C) (F) 1–10 10–100 100–1000 1000–100,000 100,000–∞ Instructions/packet 6 Copyright © 2010 Juniper Networks, Inc. COMPARISON OF SILICON TECHNOLOGIES Technology Advantages Disadvantages Use Cases Flexibility is General Poor performance, more important Very flexible Purpose CPUs density, and power than performance Field Smaller up-front Lower performance, Volume is low; Programmable development cost; density, and power; Changes are Gate Arrays Field upgrades High per part price expected Can fall short of Off-the-shelf Flexible. Jump performance, Differentiation is straight into Network power, and not important software design Processors functionality targets High High upfront cost; Tailor to your performance; Long development ASICs specification Low production cycle cost 7 Copyright © 2010 Juniper Networks, Inc. SYSTEM ARCHITECTURE Market requirements . Performance, density, feature, cost targets Software/hardware interactions . Functional partitioning Silicon process technology evaluation . Cost/performance tradeoffs Memory choices . Stores configuration, FIB tables, etc. Temporary working buffers Chip partitioning . IO and logic ratio, die size, interface simplicity 8 Copyright © 2010 Juniper Networks, Inc. ASIC PROCESS TECHNOLOGY . Greater density allows more features/functionality for the same price . Moore‟s Law: Transistor density doubles every 18 months – Holding up remarkably well. But how much longer? . While density is increasing, performance is starting to level off . The decrease in operating voltage, hence dynamic power, also slowed . Static power is becoming an issue . NRE costs associated with newer processes increasing dramatically . Architectural innovations are needed to continue to provide value to customers 9 Copyright © 2010 Juniper Networks, Inc. NETWORKING ASICS AND MEMORIES Queues / Packet Buffers Link Memory Input / Input / Output/ Output ASICs Fabric Control Memories (FIB, ACL, configs, etc.) 10 Copyright © 2010 Juniper Networks, Inc. MEMORY TECHNOLOGY CHARACTERISTICS Technology Capacity Frequency Latency Power Cost Embedded L H L M H SRAM Embedded M M L+ L M DRAM Embedded L M L+ H H TCAM External M L M H H SRAM External H M M L H RLDRAM External H+ M H L L- SDRAM External L L H H H TCAM 11 Copyright © 2010 Juniper Networks, Inc. MEMORY CHOICES WITH NETWORKING ASICS Packet buffering • Need high throughput, high density • Long bursts ok • SDRAM or RLDRAM (Reduced Latency DRAM) Queuing/Link memory • Need high throughput, low latency • Shorter bursts • SRAM, RLDRAM, or SDRAM Control memory • Need high throughput, low latency • Even smaller access quantum • SRAM, TCAM, or RLDRAM 12 Copyright © 2010 Juniper Networks, Inc. ARCHITECTURE – CHIP PARTITIONING . Fewer chips does not necessarily mean less overall cost – Chips get very expensive once Chip yield & they cross a certain die size PCB layers $ dominate – Economics of silicon is all about 1 chip fabrication yield Pins, packaging, power, PCB area dominate . Goals 2 chips – Balance size of each chip within packet forwarding engine – Minimize pin-count on each chip – Minimize overall component cost X depends on – Flexibility of support different technology configs with the same chipset Total # of transistors 13 Copyright © 2010 Juniper Networks, Inc. EXAMPLES OF SILICON PROCESS IMPROVEMENT, CHIP PARTITIONING, AND MEMORY USAGE Trio/NISP 65nm 4 Chips 1.2Bn Transistors IP3 I-Chip 180nm (90nm) 90nm 604Gbps IO IP1, 2 10 Chips 1 Chip RLDRAM/ 250nm 446m Trans 160m Transistors DDR3 SDRAM 4 Chips 412Gbps IO 219Gbps IO 18m Trans SRAM/ RLDRAM/ 47Gbps IO SRAM/ RDRAM DDR2 SDRAM SDRAM (RLDRAM) 1998 2002 2006 2009 14 Copyright © 2010 Juniper Networks, Inc. EXAMPLES: BENEFITS OF ASIC EVOLUTIONS M40 M160 T640 T1600 Slot Capacity, 3.0 10 40 100 Gbps System 40Gbps 160Gbps 640Gbps 1600Gbps Capacity Max System 1.5 KW 3.15 KW 4.52 KW 8.35 KW Draw EER 13 25 71 96 (Gbps/KW) FRS 1998 2000 2002 2007 15 Copyright © 2010 Juniper Networks, Inc. MICRO ARCHITECTURE Xchip Take each subsystem, divide into blocks, divide each block into sub- blocks, design down to the basic X_in X_out logic elements Document both functionality and X_in_a X_in_b architecture . Rigorous peer reviews of all documents X_in_b_cntl X_in_b_dp Control logic Datapath 16 Copyright © 2010 Juniper Networks, Inc. REGISTER TRANSFER LEVEL CODING Translate micro architecture for all blocks to “Register Transfer Level” code. always @ (sel or a or b) a begin out if (sel == 1) out = a; b else out = b; sel end OR assign out = sel ? a : b; . A large chip will have hundreds of thousands of lines of RTL code . Must always keep in mind physical placement and timing during the micro architecture phase – You pay now or you pay more later 17 Copyright © 2010 Juniper Networks, Inc. SYNTHESIS & TIMING Synthesis is the exercise of mapping RTL to GATES in the technology of choice INPUT – RTL code – Specification of clocks and cycle-time (frequency) – Input and output constraints for module being synthesized – Wire-load models as basis to model interconnect effects on gates – Recent trends: physical synthesis 18 Copyright © 2010 Juniper Networks, Inc. VERIFICATION Goal: First-time-right silicon . Avoid expensive ASIC respins . Simulations are far easier to debug than real chips Recipe: At least as many verification engineers as design engineers per chip TOOLS Performed at multiple levels Test-bench tool . Block level SystemVerilog . Chip level C/C++, Verilog Coverage tools . Sub-system level Equivalency checkers . System level Simulators Waveform viewers . Software/hardware co-simulation 19 Copyright © 2010 Juniper Networks, Inc. PHYSICAL DESIGN Power and clock planning Perform high-level floor-planning Place I/O, SRAMs, & Register Arrays Random logic placements Perform congestion analysis Wire up all the logic and IOs Run timing with physical placement Many iterations of all of the above 20 Copyright © 2010 Juniper Networks, Inc. PHYSICAL DESIGN EXAMPLE 1) Memory placement 2) Logic placement & clocks 3) M1 routing 4) M2 routing 5) M3 routing 6) M4 routing 7) M5 routing 8) M6 routing 9) M2/M4/M6 routing 10) M1/M3/M5 routing 21 Copyright © 2010 Juniper Networks, Inc. ASIC TAPEOUT Criteria for ASIC Tapeout . All functionality complete . All verification complete . Performance simulations meet goals . Chip is error free from a testability perspective . Chip meets timing under all process, temperature and voltage conditions . Design and verification database is archived 22 Copyright © 2010 Juniper Networks, Inc. MANUFACTURING After the ASIC is taped out . Masks are generated for photolithography . ASICs are then built layer-by-layer on a silicon substrate wafer Once the ASIC wafer is complete . Each die is tested in wafer test . Only good die are laser cut for packaging Once cut die are available . They are put in a package . The packaged devices are then tested again Tested packaged parts are put on system boards . Test with other hardware and software 23 Copyright © 2010 Juniper Networks, Inc. MANUFACTURING – CONTINUED Copper layers 300mm wafer 300mm wafer fab Packaging 24 Copyright © 2010 Juniper Networks, Inc. SUMMARY ASIC technology has transformed the network industry Silicon process technology is evolving at an impressive pace but architectural innovations are required to keep up with the demand for increasing performance at lower power A rigorous architecture, design, and verification process is required to implement complex networking ASICs There are a vast amount of architectural and design tradeoffs to be made so user community should provide feedbacks early and often 25 Copyright © 2010 Juniper Networks, Inc. .
Load more

Recommended publications
  • Modeling System Signal Integrity Uncertainty Considerations
    WHITE PAPER Intel® FPGA Modeling System Signal Integrity Uncertainty Considerations Authors Abstract Ravindra Gali This white paper describes signal integrity (SI) mechanisms that cause system-level High-Speed I/O Applications timing uncertainty and how these mechanisms are modeled in the Intel® Quartus® Engineering, Intel® Corporation Prime software Timing Analyzer to achieve timing closure for external memory interface designs. Zhi Wong By using the Intel Quartus Prime software to achieve timing closure for external High-Speed I/O Applications memory interfaces, a designer does not need to allocate a separate SI timing Engineering, Intel Corporation budget to account for simultaneous switching output (SSO), simultaneous Navid Azizi switching input (SSI), intersymbol interference (ISI), and board-level crosstalk for Software Engineeringr flip-chip device families such as Stratix® IV and Arria® II FPGAs for typical user Intel Corporation implementation of external memory interfaces following good board design practices. John Oh High-Speed I/O Applications Introduction Engineering, Intel Corporation The widening performance gap between FPGAs, microprocessors, and memory Arun VR devices, along with the growth of memory-intensive applications, are driving the Memory I/O Applications Engineering, need for faster memory technologies. This push to higher bandwidths has been Intel Corporation accompanied by an increase in the signal count and the signaling rates of FPGAs and memory devices. In order to attain faster bandwidths, device makers continue to reduce the supply voltage. Initially, industry-standard DIMMs operated at 5 V. However, due to improvements in DRAM storage density, the operating voltage was decreased to 3.3 V (SDR), then to 2.5V (DDR), 1.8 V (DDR2), 1.5 V (DDR3), and 1.35 V (DDR3) to allow the memory to run faster and consume less power.
    [Show full text]
  • Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory Sung I
    Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory Sung I. Hong, Sally A. McKee†, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, Wm. A. Wulf Dept. of Electrical and Computer Engineering †Dept. of Computer Science University of Virginia University of Utah Charlottesville, VA 22903 Salt Lake City, Utah 84112 Abstract current DRAM page forces a new page to be accessed. The Processor speeds are increasing rapidly, and memory speeds are overhead time required to do this makes servicing such a request not keeping up. Streaming computations (such as multi-media or significantly slower than one that hits the current page. The order of scientific applications) are among those whose performance is requests affects the performance of all such components. Access most limited by the memory bottleneck. Rambus hopes to bridge the order also affects bus utilization and how well the available processor/memory performance gap with a recently introduced parallelism can be exploited in memories with multiple banks. DRAM that can deliver up to 1.6Gbytes/sec. We analyze the These three observations — the inefficiency of traditional, performance of these interesting new memory devices on the inner dynamic caching for streaming computations; the high advertised loops of streaming computations, both for traditional memory bandwidth of Direct Rambus DRAMs; and the order-sensitive controllers that treat all DRAM transactions as random cacheline performance of modern DRAMs — motivated our investigation of accesses, and for controllers augmented with streaming hardware. a hardware streaming mechanism that dynamically reorders For our benchmarks, we find that accessing unit-stride streams in memory accesses in a Rambus-based memory system.
    [Show full text]
  • DDR400/333/266, Dual DDR, RDRAM 16 Bit and 32 Bit, SDRAM
    Ace’s Hardware Granite Bay: Memory Technology Shootout Granite Bay: Memory Technology Shootout By Johan De Gelas – December 2002 Dual-Channel DDR SDRAM Arrives for the Pentium 4 DDR400/333/266, Dual DDR, RDRAM 16 bit and 32 bit, SDRAM... almost every memory technology on the market is available for the Pentium 4 platform. One of our previous technical articles discussed the advantages and disadvantages of the different architectures of Rambus and SDRAM based memory technology such as DDR and DDR-II. In this article, we will investigate how the different memory technologies and their supporting chipsets compare on the test bench. The following motherboards were tested: • The ASUS P4T533 features the i850E chipset and 32 bit RDRAM • The ASUS P4T533-C comes with the same chipset but uses two channels of 16 bit RIMMs • The MSI 648 Max comes with SIS 648 chipset which unofficially supports DDR400 • The MSI i845PE comes with Intel's newest i845 chipset, which officially support DDR333 • The Tyan Trinity 7205 and MSI GNB Max feature the Dual DDR266 Granite Bay chipset We are well aware that there have already many tests with Pentium 4 chipsets, Granite Bay included. So why bother to publish another on Ace’s Hardware? The focus of this article is on the memory technology supported by these chipsets. This article will offer you a insight in how the different memory technologies compare in a wide variety of applications. We'll investigate in depth what the advantages and disadvantages are of each memory technology and try to find out what are the reasons behind this.
    [Show full text]
  • Complaint Counsel's Response to Rambus's Supplemental Brief In
    UNITED STATES OF AMERICA BEFORE FEDERAL TRADE COMMISSION COMMISSIONERS: Deborah Platt Majoras, Chairman Thomas B. Leary Pamela Jones Harbour Jon Leibowitz In the Matter of Docket No. 9302 RAMBUS INCORPORATED, PUBLIC a corporation. COMPLAINT COUNSEL’S RESPONSE TO RAMBUS’S SUPPLEMENTAL BRIEF IN SUPPORT OF MOTION TO REOPEN RECORD “[P]roof of price fixing by DRAM manufacturers . is immaterial to the issues in this case, including whether Rambus’ conduct alleged in the Complaint could tend to injure competition.” Judge Timony, Opinion Supporting Order Granting Motion of the United States Department of Justice to Limit Discovery Relating to the Grand Jury at 7 (January 15, 2003). In its Supplemental Brief, Rambus again fails to address the fundamental problem in its motion: the material it seeks to add to the record is irrelevant to this proceeding. Indeed, the information submitted by Rambus in its Supplemental Brief confirms this. The Samsung plea agreement attached to Rambus’s brief states, “The charged violation with respect to RDRAM occurred at times during the period from January 1, 2001 to June 15, 2002.” Samsung Plea Agreement, ¶ 4(d) (October 13, 2005). Thus, according to this description submitted by Rambus, the asserted RDRAM conspiracy did not begin until long after 1 Rambus’s conduct at issue in this case. Indeed, the RDRAM conspiracy apparently did not begin until: • after the industry had implemented use of the JEDEC SDRAM standard; • after JEDEC adopted the DDR SDRAM standard; • after JEDEC had completed substantial work on
    [Show full text]
  • Dynamic Random Access Memory Topics
    Dynamic Random Access Memory Topics Simple DRAM Fast Page Mode (FPM) DRAM Extended Data Out (EDO) DRAM Burst EDO (BEDO) DRAM Synchronous DRAM (SDRAM) Rambus DRAM (RDRAM) Double Data Rate (DDR) SDRAM One capacitor and transistor of power, the discharge y Leaks a smallcapacitor amount slowly Simplicit refresh Requires top sk de in ed Us le ti la o v General DRAM Formats • DRAM is produced as integrated circuits (ICs) bonded and mounted into plastic packages with metal pins for connection to control signals and buses • In early use individual DRAM ICs were usually either installed directly to the motherboard or on ISA expansion cards • later they were assembled into multi-chip plug-in modules (DIMMs, SIMMs, etc.) General DRAM formats • Some Standard Module Type: • DRAM chips (Integrated Circuit or IC) • Dual in-line Package (DIP) • DRAM (memory) modules • Single in-line in Package(SIPP) • Single In-line Memory Module (SIMM) • Dual In-line Memory Module (DIMM) • Rambus In-line Memory Module (RIMM) • Small outline DIMM (SO-DIMM) Dual in-line Package (DIP) • is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins • 14 pins Single in-line in Package (SIPP) • It consisted of a small printed circuit board upon which were mounted a number of memory chips. • It had 30 pins along one edge which mated with matching holes in the motherboard of the computer. Single In-line Memory Module (SIMM) SIMM can be a 30 pin memory module or a 72 pin Dual In-line Memory Module (DIMM) Two types of DIMMs: a 168-pin SDRAM module and a 184-pin DDR SDRAM module.
    [Show full text]
  • Dram Technology
    7 DRAM TECHNOLOGY OVERVIEW DRAM (Dynamic Random Access Memory) is the main memory used for all desktop and larger computers. Each elementary DRAM cell is made up of a single MOS transistor and a storage capacitor (Figure 7-1). Each storage cell contains one bit of information. This charge, however, leaks off the capacitor due to the sub-threshold current of the cell transistor. Therefore, the charge must be refreshed several times each second. Bit Line Word Line Transistor Capacitor Plate Source: ICE, "Memory 1997" 19941 Figure 7-1. DRAM Cell HOW THE DEVICE WORKS The memory cell is written to by placing a “1” or “0” charge into the capacitor cell. This is done during a write cycle by opening the cell transistor (gate to power supply or VCC) and presenting either VCC or 0V (ground) at the capacitor. The word line (gate of the transistor) is then held at ground to isolate the capacitor charge. This capacitor will be accessed for either a new write, a read, or a refresh. Figure 7-2 shows a simplified DRAM diagram. The gates of the memory cells are tied to the rows. The read (or write) of a DRAM is done in two main steps as illustrated in Figure 7-3. The row (X) and column (Y) addresses are presented on the same pads and multiplexed. The first step consists of validating the row addresses and the second step consists of validating the column addresses. INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-1 DRAM Technology Address X Row Decode Pads CAS RAS Y Data Sense Data Amplifier Data Sense Data Amplifier Output Dout Buffer Data Y Decode Sense Data Amplifier Input D in Buffer Data Sense Data Amplifier Source: ICE, "Memory 1997" 22430 Figure 7-2.
    [Show full text]
  • Rambus-FTC Brief Final
    SCHEDULED FOR ORAL ARGUMENT FEBRUARY 14, 2008 Nos. 07-1086, 07-1124 IN THE UNITED STATES COURT OF APPEALS FOR THE DISTRICT OF COLUMBIA CIRCUIT RAMBUS INC., Petitioner, v. FEDERAL TRADE COMMISSION, Respondent. On Petitions for Review of Final Orders of the Federal Trade Commission FINAL BRIEF FOR RESPONDENT FEDERAL TRADE COMMISSION JEFFREY SCHMIDT WILLIAM BLUMENTHAL Director General Counsel KENNETH L. GLAZER JOHN D. GRAUBERT Deputy Director Principal Deputy General Counsel RICHARD B. DAGEN JOHN F. DALY ROBERT P. DAVIS Deputy General Counsel for Litigation SUZANNE T. MICHEL PATRICK J. ROACH WILLIAM E. COHEN Attorneys Deputy General Counsel for Policy Studies Bureau of Competition Federal Trade Commission LESLIE RICE MELMAN IMAD D. ABYAD Attorneys Federal Trade Commission 600 Pennsylvania Ave., N.W. Washington, DC 20580 (202) 326-2478 CERTIFICATE AS TO PARTIES, RULINGS, AND RELATED CASES Pursuant to Circuit Rule 28(a)(1), Respondent Federal Trade Commission certifies that: (A) Parties and Amici All parties, intervenors, and amici appearing before the Commission and in this Court are listed in the Brieffor Petitioner. (B) Rulings Under Review References to the rulings at issue appear in the Brieffor Petitioner. (C) Related Cases The case on review has not been previously before this Court or any other court, and Respondent is not aware ofany related cases in this Court or any other court. -1- TABLE OF CONTENTS PAGE CERTIFICATE AS TO PARTIES, RULINGS, AND RELATED CASES 1 TABLE OF AUTHORITIES v GLOSSARY x ISSUES PRESENTED FOR REVIEW 1 STATUTES AND REGULATIONS 1 STATEMENT OF THE CASE 2 STATEMENT OF FACTS 3 A. The JEDEC Standard-Setting Process 3 B.
    [Show full text]
  • Development of DDR2 SDRAM Module Interface Software Core
    Prajakta Chandilkar. Int. Journal of Engineering Research and Application www.ijera.com ISSN : 2248-9622, Vol. 7, Issue 9, ( Part -2) September 2017, pp.28-32 RESEARCH ARTICLE OPEN ACCESS Development of DDR2 SDRAM Module Interface Software Core Prajakta Chandilkar*, Dr. Uday Wali** *(M.tech Student Electronics and Communication, KLE Dr. M.S. Sheshgiri College of Engineering and Technology, Belagavi, Karnataka, India ,[email protected] **(Professor, Dept. of Electronics and Communication, KLE Dr. M.S .Sheshgiri College of Engineering and Technology, Belagavi, Karnataka, India, [email protected]) ABSTRACT Memory module simulation is critical to testing of embedded systems. Hardware software co-design strategy requires that clock accurate system modules be available in software. DDR2 SDRAM is one of the popular memory modules used in embedded systems. Memory modules have their own built in controllers to interpret and execute commands from the processor. This paper describes an implementation of the finite state machine (FSM) of a DDR2 SDRAM module. The module can be used as a basis for hardware design of memory modules. It can also be used as a part of hardware-software co-design tool for embedded systems using DDR2 memory modules. The technology independent FSM is implemented in Verilog HDL. Keywords Command sets, DDR, DDR2 SDRAM, Hardware-Software co-design, Verilog ----------------------------------------------------------------------------------------------------------------------------- ---------- Date of Submission: 29-08-2017 Date of acceptance: 09-09-2017 ----------------------------------------------------------------------------------------------------------------------------- ---------- modify an existing interface hardware to match any I. INTRODUCTION other member of the DDR family. Developments in VLSI technology are driven by the never ending demand for faster processors. Faster processors need faster memory.
    [Show full text]
  • Rambus, Inc.: Commercializing the Billion Dollar Idea
    Harvard Business School N9-701-056 January 24, 2001 Rambus, Inc.: Commercializing the Billion Dollar Idea In January, 2001, after seven years of development and three years of production, Rambus’s DRAM memory technology, RDRAM, could be found in more than 150 products. Yet Rambus had faced several unexpected obstacles in its attempts to make RDRAM the dominant memory architecture in personal computers, the single largest market for memory. The last six months had witnessed typically ambiguous events. On one hand, Rambus chalked up a significant increase in revenues during 2000, and RDRAM shipments were at an all-time high. On the other hand, DRAM manufacturers – many of them licensees of Rambus technology – continued to pursue alternate approaches to speeding up DRAMs. As Rambus faced another challenging year, industry observers wondered how the firm could achieve its goal of becoming the dominant DRAM architecture in PCs – and whether that was still the appropriate goal. The Semiconductor Industry Semiconductors were first commercialized on a large scale in the 1950s, and by 2000 were credited with much of the productivity growth in Western economies. Scientists at AT&T’s Bell Laboratories developed the first transistor in 1948 to replace vacuum tubes with a more reliable way of regulating electronic currents. Transistors used semiconductor material to amplify an electronic signal. Made of silicon or germanium crystal, and often measuring no larger than a human finger, transistors could control the flow of a very large electric current by means of a very small electric current at another point on their surface, serving as switches.1 Unlike vacuum tubes, transistors were virtually unbreakable.
    [Show full text]
  • 24 What Your DRAM Power Models Are Not Telling
    What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study SAUGATA GHOSE, Carnegie Mellon University ABDULLAH GIRAY YAĞLIKÇI, ETH Zürich & Carnegie Mellon University RAGHAV GUPTA, Carnegie Mellon University DONGHYUK LEE, NVIDIA KAIS KUDROLLI, Carnegie Mellon University WILLIAM X. LIU, Carnegie Mellon University HASAN HASSAN, ETH Zürich KEVIN K. CHANG, Carnegie Mellon University NILADRISH CHATTERJEE, NVIDIA ADITYA AGRAWAL, NVIDIA MIKE O’CONNOR, NVIDIA & The University of Texas at Austin ONUR MUTLU, ETH Zürich & Carnegie Mellon University Main memory (DRAM) consumes as much as half of the total system power in a computer today, due to the increasing demand for memory capacity and bandwidth. There is a growing need to understand and analyze DRAM power consumption, which can be used to research new DRAM architectures and systems that consume less power. A major obstacle against such research is the lack of detailed and accurate information on the power consumption behavior of modern DRAM devices. Researchers have long relied on DRAM power models that are predominantly based off of a set of standardized current measurements provided byDRAM vendors, called IDD values. Unfortunately, we find that state-of-the-art DRAM power models are often highly inaccurate, as these models do not reflect the actual power consumed by real DRAM devices. To build an accurate model and provide insights into DRAM power consumption, we perform the first comprehensive experimental characterization of the power consumed by modern real-world
    [Show full text]
  • Lessons from Rambus – Play by the Rules in Standards Setting
    clarity, a duty of good faith underlies the stan- dard-setting process” and noted that Rambus Lessons from Rambus – Play and other JEDEC members understood that patent applications needed to be disclosed.5 by the Rules in Standards Conversely, the Federal Circuit opined that Rambus had no duty to disclose its intention to amend pending claims to cover the pro- Setting Organizations posed standards under consideration.6 Rambus was a member of the JEDEC sub- goal of such policies is to prevent an SSO BY DEAN DUNLAVEY, PARTNER, AND MICHAEL SCHALLOP, committee addressing standards for dynamic member from concealing its patents or pend- 7 OF COUNSEL, LATHAM & WATKINS LLP random access memory (DRAM) chips from ing patent applications relating to a proposed February 1992 until June 1996. During this standard under consideration, only to assert time period, Rambus had pending patent he recent Federal Trade Commission the patents later – after the standard has been 1 applications with disclosures broad enough to opinion concerning Rambus, Inc. pro- adopted and the market “locked in.” cover technologies for the standards under vides important lessons for companies Manipulation of standards setting activi- T consideration. Using information from the ties may harm competition and chill stan- that participate in standards setting organi- JEDEC meetings, Rambus repeatedly dards setting efforts. In contrast, accurate and zations (SSOs). The FTC found that amended pending patent claims and filed a timely patent disclosures along with ex ante Rambus’ misconduct in concealing its series of divisional applications in order to license disclosure obligations promote pending patent applications from an SSO build a patent portfolio that would cover the informed decision-making by SSO members had harmed competition.
    [Show full text]
  • MINIMIZING MEMORY COST in SET-TOP BOXES Jeff Mitchell Rambus Inc
    MINIMIZING MEMORY COST IN SET-TOP BOXES Jeff Mitchell Rambus Inc. conventional DRAMs. This makes a difficult Abstract choice for the system designer - add more memory and increase cost or accept lower Memory is the largest contributor to performance. the cost of a set top box, typically comprising up to half or more of the component cost. This Recently there have been new paper examines methods of minimizing this developments in the DRAM industry that offer cost using commodity memory parts solutions to the memory size/bandwidth consumed in large volumes by the PC industry dichotomy. Two new types of DRAM and by taking advantage of new developments devices, RambusTM DRAM (RD~) and in high density, high bandwidth DRAMs. Synchronous DRAM (SDRAM) offer improved bandwidth over traditional devices Architectural methods of extracting and yet still maintain an inexpensive DRAM bandwidth from conventional DRAM are cost structure. Both are designed to be used in examined, along with performance personal computer main memory applications, requirements of emerging set-top box the largest user of DRAM memory. Over half architectures. Alternatives are presented for of the world's annual DRAM shipments go meeting product performance goals while into PC's. Interactive set top boxes which use preserving low cost. these new high bandwidth types of memory can meet their performance objectives and take advantage of the PC cost/volume curves. This allows the consumer to have the best of both THE EFFECT OF MEMORY ON SYSTEM worlds - high performance at low cost. PERFORMANCE Digital set top boxes require tremendous amounts of bandwidth in order to MEMORY ALTERNATIVES deliver the interactive experience desired by consumers.
    [Show full text]