MPC8560 PowerQUICC III™ Torridon User’s Guide

MPC8560UG Rev. 0.1 12/2004

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MPC8560UG Rev. 0.1 10/2004

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number Chapter 1 References

1.1 Glossary ...... 1 1.2 References...... 3

Chapter 2 Introduction

2.1 Background...... 1 2.2 Scope...... 1 2.3 System Overview...... 1

Chapter 3 Motherboard

3.1 Motherboard Overview...... 1 3.2 Motherboard Features ...... 2

Chapter 4 Processor

4.1 Overview...... 1 4.2 MPC8560 Processor Configuration ...... 2 4.3 COP Interface ...... 4

Chapter 5 Flash

5.1 Overview...... 1 5.2 Flash...... 1

Chapter 6 DDR

6.1 Overview...... 1 6.1.1 DDR Memory ...... 1 6.1.2 The MPC8560’s DDR Memory Controller ...... 1 6.1.2.1 Available Signals ...... 1 6.2 Design Considerations ...... 2 6.2.1 Signal Termination...... 2 6.2.2 Signal Connections ...... 3 6.2.2.1 Address and Control Signals ...... 3 6.2.2.2 Data...... 3 6.2.2.3 Clock...... 4

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -iii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number 6.2.2.4 Serial Presence Detect ...... 4 6.2.2.5 DDR SDRAM Power ...... 4 6.2.2.6 Voltage Generation ...... 5 6.3 Physical Implementation...... 5 6.3.1 Schematics ...... 7 6.4 Layout ...... 12 6.4.1 Address and Control ...... 12 6.4.2 Data...... 14 6.4.3 Clocks ...... 17 6.4.4 DDR Power...... 19

Chapter 7 RapidIO

7.1 Overview...... 1 7.1.1 RapidIO Interconnect...... 1 7.1.2 The MPC8560’s RapidIO Controller...... 1 7.1.3 Signals Descriptions ...... 1 7.2 Design Considerations ...... 2 7.2.1 Signal Termination...... 2 7.2.2 Signal Connections ...... 3 7.3 Logic Analyser Connection ...... 5 7.4 Physical Connections...... 7 7.5 Layout Considerations ...... 11

Chapter 8 GBit Ethernet

8.1 Overview...... 1 8.2 GBit Ethernet Connection...... 1 8.3 GMII Interface ...... 2 8.4 PHY Device ...... 3 8.5 Magnetics & RJ45 ...... 5 8.6 Layout Considerations ...... 6

Chapter 9 UART

9.1 Overview...... 1

Chapter 10 PCI

10.1 Overview...... 1 10.2 PCI Clocks ...... 2

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 -iv Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number 10.3 Bus Connectivity...... 2 10.4 PCI Configuration...... 2 10.5 Schematics ...... 2

Chapter 11 Peripheral Support

11.1 Overview...... 1 11.2 IDE Interface...... 1 11.2.1 Compact Flash Support...... 4 11.2.1.1 Overview...... 4 11.2.1.2 Implementation on Torridon ...... 4 11.3 USB...... 6 11.4 PS2 ...... 7

Chapter 12 Communications

12.1 Overview...... 1 12.2 Test...... 1 12.3 QUADS Compatible Headers...... 1 12.4 UTOPIA Interface...... 13

Chapter 13 Reset

13.1 Overview...... 1 13.2 Reset Sources...... 1 13.3 Reset Scheme...... 2

Chapter 14 Clocking

14.1 Overview...... 1 14.2 System Clocks...... 1 14.3 RapidIO Clocks...... 4 14.3.1 Overview...... 4 14.3.2 Torridon’s RapidIO Sub-System...... 5 14.3.3 Processor Clocks...... 7 14.3.4 TSI500 Clocks ...... 7 14.3.5 Clock Distribution on Torridon...... 9 14.4 Processor Real Time Clock...... 14 14.5 GBit Ethernet Clocks ...... 16 14.6 Southbridge Real Time Clock...... 16

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -v PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number Chapter 15 Voltage Regulation

15.1 Overview...... 1 15.2 Power Available...... 1 15.3 Power Required...... 2 15.4 Power Distribution...... 2 15.5 Voltage Generation...... 4 15.5.1 CPLD Power...... 4 15.5.2 5V/3.3V Switching ...... 6 15.5.3 MPC8560...... 8 15.5.3.1 MPC8560 Power Requirements ...... 8 15.5.3.2 Core & PLL Voltage ...... 8 15.5.3.3 DDR DRAM I/O Voltage ...... 14 15.5.3.4 I/O Voltage...... 16 15.5.4 DDR SDRAM...... 16 15.5.5 GBit Ethernet ...... 18 15.5.6 TSI500 ...... 21 15.6 Power Sequencing...... 25

Chapter 16 Processor Sockets

16.1 Overview...... 1 16.2 The Need For Sockets...... 1 16.3 Socket Criteria ...... 1 16.4 The Choice of a Socket...... 2 16.5 Socket Mechanics ...... 2 16.6 The Base Package Emulator (BPE) ...... 4 16.7 The Flat Pin Array (FPA)...... 6 16.8 Alternative Parts ...... 8 16.9 Sockets on Torridon ...... 8

Chapter 17 Heat Sinks

17.1 Overview...... 1 17.2 Processor Thermal Characteristics...... 1 17.3 Thermal Management Information...... 2 17.4 Adhesives and Thermal Interface Materials ...... 2 17.5 Heat Sink Selection...... 3 17.6 Fans...... 5 17.7 Heat Sinks On Torridon ...... 6

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 -vi Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number Appendix A Schematics

Appendix B Revision History

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -vii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 -viii Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Tables Table Page Number Title Number 1-1 Glossary of Terms ...... 1 4-1 MPC8560 Configuration...... 3 4-2 COP/JTAG Connector...... 5 6-1 DDR SDRAM Interface Signals ...... 2 6-2 Data Byte Lanes ...... 14 7-1 RapidIO Interface Signals...... 2 7-2 RapidIO Probe - P30 ...... 7 7-3 RapidIO Probe - P31 ...... 8 7-4 RapidIO Probe - P32 ...... 9 7-5 RapidIO Probe - P33 ...... 10 8-1 TSEC GMII Interface Signals...... 2 8-2 PHY Configuration Pins ...... 4 8-3 Setting PHY Configuration Pins ...... 4 8-4 PHY Configuration Pins on Torridon ...... 5 8-5 Ethernet Connections ...... 6 9-1 Specific MPC8560 - UART Signals ...... 1 9-2 RS232 Connector ...... 2 11-1 CompactFlash Interconnect...... 4 12-1 ADS Compatible Expansion Connector - P28 - Row A ...... 5 12-2 ADS Compatible Expansion Connector - P28 - Row B ...... 6 12-3 ADS Compatible Expansion Connector - P28 - Row C ...... 7 12-4 ADS Compatible Expansion Connector - P28 - Row B ...... 8 12-5 ADS Compatible Expansion Connector - P29 - Row A ...... 9 12-6 ADS Compatible Expansion Connector - P29 - Row B ...... 10 12-7 ADS Compatible Expansion Connector - P29 - Row C ...... 11 12-8 ADS Compatible Expansion Connector - P29 - Row D ...... 12 12-9 16 Bit UTOPIA Connector - P7 - Row A ...... 13 12-10 16 Bit UTOPIA Connector - P7 - Row B ...... 14 12-11 16 Bit UTOPIA Connector - P7 - Row C ...... 14 12-12 16 Bit UTOPIA Connector - P7- Row D ...... 15 12-13 16 Bit UTOPIA Connector - P7 - Row E...... 16 12-14 16 Bit UTOPIA Connector - P7 - Row F...... 16 13-1 Reset Signals ...... 3 15-1 Power Supplied from an ATX Power Supply ...... 1 15-2 Power Required...... 2 15-3 MPC8560 Power Requirements...... 8 16-1 Alternative Socket Vendors...... 8 17-1 Package Thermal Characteristics ...... 1

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -ix PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Tables Table Page Number Title Number B-1 Revision History ...... 1

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 -x Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figures Figure Page Number Title Number 2-1 Typical Torridon Platform Configuration ...... 2 3-1 Torridon Motherboard...... 1 3-2 Torridon Block Diagram ...... 3 4-1 MPC8560 POR Configuration ...... 2 4-2 COP/JTAG Connections ...... 6 5-1 Flash ROM...... 2 5-2 Flash ROM Schematics - Local Bus Controller...... 3 5-3 Flash ROM Schematics - Address/Data Demuxing...... 4 5-4 Flash ROM Schematics - Flash...... 5 6-1 DDR Termination...... 3 6-2 DDR SDRAM Voltage Levels ...... 4 6-3 DDR SDRAM Voltage Generation ...... 5 6-4 64 Bit DDR SDRAM ...... 6 6-5 MPC8560 DDR Controller ...... 8 6-6 SODIMM Connection...... 10 6-7 VTT Voltage Generation...... 11 6-8 Address and Control...... 12 6-9 Address and Control Layout ...... 13 6-10 Data ...... 15 6-11 Data Layout...... 16 6-12 DLL Configuration ...... 17 6-13 DDR Clock Signals...... 18 6-14 Clock Layout...... 19 6-15 LP2995 Layout...... 20 6-16 VREF Layout ...... 21 6-17 VTT Island ...... 22 6-18 VTT Voltage Monitoring...... 22 7-1 RapidIO Termination ...... 2 7-2 RapidIO Signal Connections...... 4 7-3 Tektronix TLA700 System...... 5 7-4 P6880 Probes...... 5 7-5 Mother Board Connection...... 6 7-6 Probe Layout ...... 6 7-7 RapidIO Receive Path Layout...... 11 7-8 RapidIO Receive Path Layout (With Logic Probes)...... 12 8-1 GBit Ethernet Connection...... 1 8-2 GMII Interface ...... 3 8-3 RJ45 with Integrated Magnetics ...... 6

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -xi PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figures Figure Page Number Title Number 8-4 MDI Bus Layout ...... 7 9-1 RS232 Interface...... 1 9-2 MPC8560 CPM...... 3 9-3 RS232 Transceiver ...... 4 10-1 Boot Processor’s PCI Bus ...... 1 10-2 MPC8560’s PCI Interface - Schematics...... 3 10-3 PCI Slot - Schematics ...... 5 11-1 Primary IDE Interface - Schematics ...... 2 11-2 Secondary IDE Interface - Schematics ...... 3 11-3 CompactFlash Connection ...... 6 11-4 USB - Schematics ...... 7 11-5 PS2 - Schematics...... 8 12-1 E1/T1 Card...... 2 12-2 QUADS Compatible Headers ...... 3 12-3 Connectivity to the QUADS Headers ...... 4 13-1 Reset Scheme ...... 2 13-2 Resets ...... 6 14-1 System Clocks...... 2 14-2 System Clocks - Schematics ...... 3 14-3 RapidIO Clocking ...... 5 14-4 RapidIO Sub-System...... 6 14-5 RapidIO Clock Options...... 7 14-6 TSI500 RapidIO Clock Options...... 8 14-7 RapidIO Clock Distribution on Torridon ...... 10 14-8 High Speed Clock Generation...... 11 14-9 Slow Speed Clock Generation ...... 13 14-10 Processor Real Time Clocks ...... 14 14-11 Processor Real Time Clocks - Schematics...... 15 14-12 GBit Ethernet Clocks ...... 16 14-13 Real Time Clock Schematics ...... 18 15-1 Power Distribution ...... 3 15-2 CPLD Power - Schematics...... 5 15-3 3.3V/5V Isolator - Schematics ...... 7 15-4 NXI100 Power Module...... 8 15-5 Vdd Power - Schematics ...... 10 15-6 Vdd Power - Feedback- Schematics ...... 11 15-7 PLL Power - Schematics...... 13 15-8 DDR12 Module...... 14 15-9 2.5V Voltage Generation...... 15 15-10 1.25V Signal Generation...... 17

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 -xii Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figures Figure Page Number Title Number 15-11 GBit Ethernet - 2.5V Generation ...... 19 15-12 GBit Ethernet - 1.5V Generation ...... 20 15-13 TSI500 - 2.5V Generation...... 22 15-14 TSI500 - 1.3V Generation...... 23 15-15 TSI500 - 1.2V Generation...... 24 15-16 Power-Up Sequence...... 26 16-1 Socket Mechanics ...... 3 16-2 Processor - Socket Swapping...... 4 16-3 The BPE ...... 5 16-4 The FPA ...... 7 16-5 BPE ...... 8 16-6 PowerQUICCIII in FPA...... 9 16-7 PowerQUICCIII in FPA - Side View ...... 9 16-8 PowerQUICCIII + FPA + BPE ...... 10 16-9 Heat Sink Attached ...... 10 17-1 Heat Sink Attachment ...... 2 17-2 Thermal Performance of Interface Material...... 3 17-3 Aavid Thermalloy 10-THMA-01 Thermal Characteristics ...... 4 17-4 Aavid Thermalloy 10-THMA-01 Dimensions...... 5 17-5 Heat Sink on Torridon...... 6 A-1 Top Level ...... 2 A-2 Boot Processor—Top Level ...... 3 A-3 Boot Processor—Local Bus—Flash ...... 4 A-4 Boot Processor—DDR SDRAM...... 5 A-5 Boot Processor—PCI Interface...... 6 A-6 Boot Processor—RapidIO Interface ...... 7 A-7 Boot Processor—GigaByte Ethernet Interface—Top ...... 8 A-8 Boot Processor—GigaByte Ethernet Interface ...... 9 A-9 Boot Processor—GigaByte Ethernet Interface—PHY1 ...... 10 A-10 Boot Processor—GigaByte Ethernet Interface—PHY2 ...... 11 A-11 Boot Processor—Communications Processor Module...... 12 A-12 Boot Processor—Auxiliary Functions ...... 13 A-13 Boot Processor—Power On Configuration...... 14 A-14 Boot Processor—PCI Expansion ...... 15 A-15 Southbridge—Top Level...... 16 A-16 Southbridge—PCI, PIDE, AC97 ...... 17 A-17 Southbridge—Side, ISA, Peripheral ...... 18 A-18 Southbridge—IO...... 19 A-19 Boot Processor—PCI Slot...... 20 A-20 Boot Processor—Power ...... 21

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -xiii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figures Figure Page Number Title Number A-21 Work Processor 1—Top Level ...... 22 A-22 Work Processor 1—Local Bus ...... 23 A-23 Work Processor 1—DDR SDRAM...... 24 A-24 Work Processor 1—RapidIO Interface ...... 25 A-25 Work Processor 1—PCI Interface...... 26 A-26 Work Processor 1—GigaByte Ethernet Interface—Top ...... 27 A-27 Work Processor 1—GigaByte Ethernet Interface ...... 28 A-28 Work Processor 1—GigaByte Ethernet Interface—PHY ...... 29 A-29 Work Processor 1—Communications Processor Module...... 30 A-30 Work Processor 1—Auxiliary Functions ...... 31 A-31 Work Processor 1—Power On Configuration...... 32 A-32 Work Processor 1—Power ...... 33 A-33 Work Processor 2—Top Level ...... 34 A-34 Work Processor 2—Local Bus ...... 35 A-35 Work Processor 2—DDR SDRAM...... 36 A-36 Work Processor 2—RapidIO Interface ...... 37 A-37 Work Processor 2—PCI Interface...... 38 A-38 Work Processor 2—GigaByte Ethernet Interface—Top ...... 39 A-39 Work Processor 2—GigaByte Ethernet Interface ...... 40 A-40 GigaByte Ethernet Interface—PHY...... 41 A-41 Work Processor 2—Communications Processor Module...... 42 A-42 Work Processor 2—Auxiliary Functions ...... 43 A-43 Work Processor 2—Power On Configuration...... 44 A-44 Work Processor 2—Power ...... 45 A-45 Work Processor 3—Top Level ...... 46 A-46 Work Processor 3—Local Bus ...... 47 A-47 Work Processor 3—DDR SDRAM...... 48 A-48 Work Processor 3—RapidIO Interface ...... 49 A-49 Work Processor 3—PCI Interface...... 50 A-50 Work Processor 3—GigaByte Ethernet Interface—Top ...... 51 A-51 Work Processor 3—GigaByte Ethernet Interface ...... 52 A-52 Work Processor 3—GigaByte Ethernet Interface—PHY ...... 53 A-53 Work Processor 3—Communications Processor Module...... 54 A-54 Work Processor 3—Auxiliary Functions ...... 55 A-55 Work Processor 3—Power On Configuration...... 56 A-56 Work Processor 3—Power ...... 57 A-57 RapidIO Switch—Top Level...... 58 A-58 RapidIO Switch—Ports 0 and 1...... 59 A-59 RapidIO Switch—Ports 2 and 3...... 60 A-60 RapidIO Switch—Misc...... 61

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 -xiv Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figures Figure Page Number Title Number A-61 RapidIO Switch—Power...... 62 A-62 Clocking—Top Level...... 63 A-63 Clocking—Processor ...... 64 A-64 Clocking—RapidIO ...... 65 A-65 Reset Control...... 66 A-66 Power Supply—Top Level...... 67 A-67 Power Supply—Core Voltage ...... 68 A-68 Power Supply—IO Voltages ...... 69 A-69 Power Supply—Supplied Power...... 70 A-70 WP—Debug Ports...... 71

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -xv PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Figures Figure Page Number Title Number

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 -xvi Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 1 References

This section contains references used throughout this design guide.

1.1 Glossary Table 1-1 shows acronyms and terms used throughout this design guide. Table 1-1. Glossary of Terms

Term Description

ATA AT Attachment ATM Asynchronous Transfer Mode Boot Processor MPC8560 Networking and Communications Processor CD Carrier Detect COP Common On-Board Processor CPM Communication Processor Module CTS Clear To Send DDR SDRAM Double Data Rate SDRAM DIMM Dual Inline Memory Module DIP Dual Inline Package

DLL Delay Locked Loop

DMA Direct Memory Access

DSR Data Send Ready

DTR Data Terminal Ready

EEPROM Electrically Erasable Programmable Read Only Memory

FCC Fast Communications Controller FIFO First In First Out FPGA Field Programmable Gate Array GMII GBit Media Independent Interface GPCM General Purpose Chip Select Machine I2C Inter-Integrated Circuit Controller IDE Integrated Device Electronics I/O Input/Output

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 1-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE References

Table 1-1. Glossary of Terms (continued)

Term Description

LP-LVDS Link Protocol - Low Voltage Differential Signalling JTAG Joint Test Access Group MAC Media Access Controller MCC Multi-Channel Communications Controller MII Media Independent Interface PCB Printed Circuit Board PCI Peripheral Component Interconnect PCMCIA Personal Computer Memory Card International Association PLL Phase Locked Loop PHY Physical Interface POR Power on Reset PowerQUICC MPC8xx Networking and Communications Processor PowerQUICCII MPC82xx Networking and Communications Processor PowerQUICCIII MPC85xx Networking and Communications Processor RI Ring Indicator RIO RapidIO ROM Read Only Memory RTS Ready to Send Rxd Received Data SCC Serial Communications Controller SDRAM Synchronous Dynamic Random Access Memory SPD Serial Presence Detect SSTL_2 Stub Series Terminated Logic for 2.5 Volts TDM Time Division Multiplex TSEC Triple Speed Ethernet Controller Txd Transmitted Data USB Universal Serial Bus UTOPIA Universal Test Operational Physical Interface for ATM Work Processor MPC8560 Networking and Communications Processor

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 1-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE References

1.2 References Please refer to the following for more information. 1. MPC8560 Integrated Processor Reference Manual 2. MPC8540 Integrated Processor Reference Manual 3. TSI500 RapidIO Multi-port Switch User Manual 4. M88E1011 Data Sheet 5. Via VT82C686B “Super South” South Bridge Data Sheet 6. Torridon System Specification - Ver 1.3 7. Torridon User Manual - Ver 2.0

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 1-3 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE References

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 1-4 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 2 Introduction

This section provides a brief introduction to the Torridon Platform.

2.1 Background Torridon has been developed as a demonstration vehicle for Motorola’s new generation of integrated communication processors, the PowerQUICCIII in a multi processor RapidIO environment. As well as a demonstration system, it is also a hardware and software reference platform and code development platform.

2.2 Scope This design guide details the key design features of the platform and describes the specific implementation. This document is intended as a guide for hardware designers who are involved in the development of PowerQUICCIII based products. It is not intended as a system specification nor a user manual for Torridon. Both these exist as separate documents.

2.3 System Overview Although Torridon is designed such that it can plug into a larger system (e.g. through connectivity to a backplane), typically the platform will operate as a stand alone system. System configurations can change depending, for example, on the peripherals which are attached. The diagram in Figure 2-1 shows one possible system configuration.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 2-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Introduction

ID E 0 /1 Software

USB

PCI

Torridon Board

GBit RS232 RS232

Figure 2-1. Typical Torridon Platform Configuration

The system consists of various parts • The Torridon motherboard • PCI expansion cards (e.g. graphics, additional peripherals) • USB Peripherals (e.g. keyboard, mouse) • Non-volatile storage (e.g. hard disk drive, Compact Flash) • Communications (e.g. Gbit Ethernet, RS232) • Linux Software Operating System • Software Development Environment

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 2-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 3 Motherboard

This section provides a brief introduction to the Torridon Motherboard.

3.1 Motherboard Overview Figure 3-1below shows a picture of the Torridon Motherboard.

Figure 3-1. Torridon Motherboard

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 3-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Motherboard

The board supports four MPC8560 processors. The main processor, which is responsible for booting the others and controlling the main peripherals, is referred to as the Boot Processor. The other three processors are referred to as Work Processor 1, 2 and 3. The Boot Processor is responsible for peripheral support (e.g. USB, PS2 keyboard/mouse, hard disk, audio) via a “Southbridge chip”. It also provides support for a 64 bit PCI plug in card. It utilizes DDR memory as its local storage. Off board communications are made via a UART connection and a dual GBit ethernet connection. In addition to the boot processor, there are the three additional PowerQUICCIII processors, Work Processor 1, 2 and 3. Each one of these processors support their own local DDR memory, UART and GBit Ethernet connections. All of the processors communicate with each other via parallel RapidIO. A Tundra TSI500 RapidIO switch provides the switch fabric. The board is powered from a 12V/5V/3.3V supply. All the other required voltages being generated on-board.

3.2 Motherboard Features The motherboard consists of various subsystems • Processor - The board has four MPC8560 processors. • Flash - The main processor boots from its own local Flash ROM. • DDR - Each processor has its own local bank of DDR memory. • RapidIO - The processors communicate with each over RapidIO. This communication is via a RapidIO switch. • GBit Ethernet - Each processor provides an interface to GBit Ethernet. • UART - Each processor provides connectively to a UART port. • PCI Expansion - Provided by a 64 bit PCI slot. • Peripheral Support - Provided by a South Bridge Chip. • Communications - Additional communications are handled via a “QUICC Application Development System” (QUADS) Compatible Header and a UTOPIA connection to the backplane • Reset - The system reset is handled by an on-board CPLD. • System Clocking - All the required clock signals are generated locally on board. • Voltage Regulation - All the required voltage levels are generated locally on board.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 3-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Motherboard Features

Figure 3-2 below shows a block diagram of the system.

RJ45 PHY GBit1 Voltage Reset RJ45 PHY GBit2 Regulation Gbit Ethernet RJ45 PHY GBit3 J5 Power RJ45 PHY GBit4 RJ45 PHY GBit5 Clock Generation QUADS D-Type PHY UART1 Compatible RJ11 PHY UART2 UART DDR Header RJ11 PHY UART3 RJ11 PHY UART4 Flash + Latch 64 Bit PCI UART1 GBit1

USB MPC8560 Boot Processor South GBit5 IDE Bridge J3 16 Bit UTOPIA RIO Access IDE

Work Processor 3 GBit2 TSI500 UART2 MPC8560 RapidIO MPC8560 UART4 Switch GBit4 Work Processor 1 QUADS Compatible DDR Work Processor 2 DDR Header

MPC8560 DDR UART3 GBit3

Figure 3-2. Torridon Block Diagram

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MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 3-4 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 4 Processor

This section describes the processor sub-section on the Torridon Motherboard.

4.1 Overview The processors on Torridon are all MPC8560s. The MPC8560 PowerQUICCIII is the next generation PowerQUICCII integrated communications processor. The MPC8560 provides integration of processing power for networking and communications peripherals resulting in higher device performance. The MPC8560 has four main system blocks. The first block is a high-performance embedded e500 core processor with 256 kbyte of level-2 cache, implementing the enhanced Book E instruction set architecture. The second block is the communications processor module (CPM). The CPM of the MPC8560 supports three high-performance fast communications channels (FCCs) for 155Mbps ATM and Fast Ethernet, and up to 256 full-duplex, time-division-multiplexed (TDM) channels using two multi-channel controllers (MCCs). Other communications (for example UART) are supported by the serial communication controllers (SCCs). The third block is a bus controller which provides a DDR SDRAM memory controller, a local bus controller, I2C interconnect as well as an interrupt controller. The fourth block provides additional interfaces for system integration. These include two integrated 10/100/1000 Triple Speed Ethernet controllers (TSECs), a 64-bit PCI/PCI-X controller and a RapidIO interconnect. This high level of integration simplifies board design and offers significant bandwidth and performance for high-end control-plane and data-plane applications. Each MPC8560 provides the following main functionality on board: • A DDR memory controller • A Flash ROM memory controller (On the Boot Processor only) • An RS232 interface • Two GBit Ethernet interfaces (Only one is supported on each of the Work Processors) • A PCI interface (provides a connection to the Southbridge) (On the Boot Processor only) • A RapidIO interface

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4.2 MPC8560 Processor Configuration Unlike the PowerQUICCII family which uses a hard reset configuration word for initial configuration of the processor, the MPC8560 uses dedicated input pins. These pins are sampled during the assertion of reset and are used to configure variables such as the internal clock frequency, boot ROM location and so on. These pins are sampled during the assertion of reset. This reset signal is generated locally on-board from the reset circuitry. The configuration signals are passed through a ‘244 buffer with its output enable signal controlled by the reset. This is shown in Figure 4-1 below.

+3.3V

‘244 Buffer MPC85x0

Configuration Pins

+3.3V

0V

Reset* 0V OE

Figure 4-1. MPC8560 POR Configuration

Note: For the sake of clarity, only six configuration signals are shown in the diagram above. Some of the signals are changeable via a set of DIP switches, whereas others are hard wired on the board. Some of these signals have an internal pull-up which selects a default state.

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Table 4-1 below summarizes these configuration pins and their specific usage on Torridon. Table 4-1. MPC8560 Configuration

Chip Torridon Functional Pin Usage Torridon Setup Description Controlled By Note Default Setting

LA[28:31] Internal PLL Ratio None 1010 Internal clock set to 10:1 Ratio DIP Switches 1 LALE, LGPL2 e500 Core PLL Ratio None 01 e500 core set to 5:2 Ratio DIP Switches 2 TSEC1_TxD[6:4] Boot ROM Location 111 111 Processor boots from 32bit ROM DIP Switches 3 LWE[2:3] Host/Agent Config. 11 11 Processor acts as a host DIP Switches 4 processor LA[27] CPU Boot Hold off 1 1 Processor is released from reset DIP Switches 5 without waiting for external configuration

LGPL3,LGPL5 Boot Sequence Config. 11 11 Boot sequencer is disabled Default — Assumed EC_MDC Adjust TSEC Width 1 1 TSEC Port Width set to GMII Default — Assumed

TSEC1_TxD[7] Configure TSEC 1 I/F 1 0 TSEC1 set to GMII mode DIP Switches — TSEC2_TxD[7] Configure TSEC 2 I/F 1 0 TSEC2 set to GMII mode DIP Switches 6 LGPL0, LPGL1 RapidIO Clock Source 11 01 The source of the RapidIO DIP Switches — Transmit Clock is the RapidIO Receive Clock TSEC2_TxD[4:2] RapidIO Device ID None 001 Select RapidIO Device ID DIP Switches 7 PCI_REQ64 PCI Width (32 or 64) 1 1 PCI Bus set to 32 Bit Default 8 Assumed

PCI_GNT[1] PCI I/O Impedance 1 0 PCI I/O Impedance set to 25 DIP Switches 8 ohms PCI_GNT[2] PCI Arbiter Enable 1 1 Internal PCI Arbitrator is Enabled Default 8 Assumed PCI_GNT[3] PCI Debug Enable 1 1 PCI Debug is Disabled Default 8 Assumed

PCI_GNT[4] PCI/PCI-X Bus 1 1 PCI Mode is Selected Default 8 Configuration Assumed MSRCID[0] Memory Debug Enable 1 1 Debug Data is driven on MSrcID DIP Switches — and MDVAL Pins MSRCID[1] DDR Debug Enable 1 1 Debug Data is not Driven on Default — ECC Assumed

LWE[0:1] PCI O/P Hold Config 11 11 Adjust Hold Times for PCI DIP Switches 8 Drivers TSEC2_TxD[6:5] Local Bus Hold Config 11 11 Adjust Hold Times for Local Bus DIP Switches 9 Drivers

1 Based on a 33.3MHz input clock, the platform clock will run at 333MHz.

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2 Based on a 33.3MHz input clock, the core clock will run at 833Mhz 3 For the Work Processors, this is set to 011 meaning the boot ROM location is RapidIO 4 For the Work Processors, this is set to 01 meaning the processor is configured as a RapidIO agent 5 For the Work Processors, this is set to 0 meaning the processor is prevented from booting until released by the Boot Processor 6 Not used on the Work Processors; they only use TSEC1 7 The RapidIO device IDs are as follows Boot Processor ID = 1 Work Processor 1 ID = 2 Work Processor 2 ID = 3 Work Processor 3 ID = 4 8 Not used on the Work Processors; they do not use PCI. 9 Not used on Work Processors 2 & 3; they do not use their local bus

4.3 COP Interface The COP - Common On-Chip Processor, is part of the MPC8560’s JTAG machine, implemented as a set of additional instructions and logic within the JTAG permissions. This port may be connected to a dedicated debug station for extensive system debug. There are several third party debug solutions on the market. These debug-stations may be connected to the host computer via either Ethernet, Parallel-Port, RS232 or any other media. To support debug station connection to the COP/JTAG port of each processor, five 16 pin headers are provided on Torridon, carrying the COP/JTAG signals as well as additional signals aiding in system debug.

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The pinout for each of the COP/JTAG connectors is shown in Table 4-2 below. Table 4-2. COP/JTAG Connector

Pin# Signal Description

1 TDO Transmit Data Output. The MPC8560’s JTAG serial data output pin. 2 NC Not Connected 3 TDI Transmit Data Input. The MPC8560’s JTAG serial data input pin. 4 TRST* Test port Reset. Used to resets the JTAG logic on the MPC8560. 5 +3.3V +3.3 Volt Power. 6 +3.3V +3.3 Volt Power 7 TCLK Test port Clock. This clock shifts in / out data to / from the MPC8560’s JTAG logic. 8 CHK_STP_IN* Check Stop In.This pin is pulled up to 3.3V via a 10K resistor. 9 TMS Test Mode Select. This signal changes the state of the JTAG machines. 10 NC Not Connected 11 SRESET* Soft Reset. The MPC8560’s Soft Reset Signal. 12 NC Not Connected 13 HRESET* Hard Reset. The MPC8560’s Hard Reset Signal. 14 NC Not Connected 15 CHK_STP_OUT* Check Stop Out.This pin is pulled up to 3.3V via a 10K resistor. 16 GND Digital Ground

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The diagram in Figure 4-2 shows the COP/JTAG connections.

From Target SRESET Board Sources SRESET (if any) HRESET HRESET

HRESET 10 kΩ 13 OVDD SRESET 11 OVDD 10 kΩ OVDD 10 kΩ

OVDD 10 kΩ TRST TRST 1 KEY 4 No pin GND Ω 3 4 VDD_SENSE 2 k 6 OVDD 10 kΩ 5 6 1 5 OVDD 7 8 CHKSTP_OUT 15 CHKSTP_OUT 9 10 10 kΩ OVDD 11 12 Key 10 kΩ 142 OVDD KEY 13 No pin CHKSTP_IN 8 CHKSTP_IN 15 16 TMS 9 TMS TDO COP Connector 1 TDO Physical Pin Out TDI COP Header COP 3 TDI TCK 7 TCK 22

10 NC

12 NC 16

Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the part. Ω Connect pin 5 of the COP header to OVDD with a 10 K pull-up resistor. 2. Key location; Pins 2 and 14 are not physically present on the COP header Figure 4-2. COP/JTAG Connections

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This section describes the flash sub-section on the Torridon Motherboard.

5.1 Overview Although Torridon supports four processors, only one of these, the boot processor, uses local Flash ROM directly as its boot device. The other processors, the work processors, boot over RapidIO. Hence, Torridon only requires one bank of Flash memory. The MPC8560 boots from a Flash ROM which is accessed using the MPC8560’s General Purpose Chip Select Machine (GPCM). The address and data on the local bus of the MPC8560 is multiplexed. An external demultiplexor, controlled by the local buses address latch enable (LALE) signal is used to separate the address and data bus.

5.2 Flash The Flash is arranged as 32 bit wide Flash ROM and is physically implemented in two AMD 29LV641D Flash devices providing a total of 16Mbytes of Flash. This Flash is soldered directly onto the Torridon motherboard.

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The diagram in Figure 5-1 shows the Flash ROM on the Boot processor.

AM 29LV641D

LOE* OE*

LCS0* B uffer CE*

LW E0*, LWE2* LW E0* WE*

RESET* RESET*

LAD[0:15] D[15:0]

LAD[0:31] LA[8:26] LALE Demux A[21:3] BLA[27:29] A[2:0]

AM 29LV641D

OE*

CE* LW E2* WE*

RESET*

D[15:0]

LA[8:26] A[21:3]

A[2:0]

Figure 5-1. Flash ROM

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The schematics for the Flash interface are shown in Figure 5-2, Figure 5-3, and Figure 5-4.

Figure 5-2. Flash ROM Schematics - Local Bus Controller

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Figure 5-3. Flash ROM Schematics - Address/Data Demuxing

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Figure 5-4. Flash ROM Schematics - Flash

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The following should be noted about the circuitry. • Although the local bus’s DLL is connected (LSYNC_IN, LSYNC_OUT), no synchronous devices are connected to the local bus. • The external Transfer Acknowledge (/LGTA) signal is pulled up to ensure the cycle is not terminated by a false transfer acknowledge cycle. • The ‘74ALVCH32973 devices provide both buffering and de multiplexing. • As the ‘74ALVCH32973 is 16 bits wide, two devices are required to de-multiplex the 32 bit bus. • Some of the control signals (e.g. LWE_N0, LGPL2 etc.) are used elsewhere in the design. These are buffered to provide additional drive to cope with the additional loading. • As the processor is big endian, the least significant bit on the address and data bus is bit 31. • The flash devices are arranged as 32 bit wide devices, hence the two least significant address bits are don’t cares. • The burst address pins (BLA(27:29]) allow burst accesses to be supported. • Note the write enable signals are different for each Flash device.

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This section describes the DDR sub-section on the Torridon Motherboard.

6.1 Overview

6.1.1 DDR Memory DDR (Double Data Rate) memory is the next generation SDRAM. Like SDRAM, DDR is synchronous with the system clock however, DDR reads data on both the rising and falling edges of the clock signal. SDRAM only carries information on the rising edge of a signal. This enables the DDR module to transfer data twice as fast as traditional SDRAM. For example, using a clock rate of 133MHz on a SDRAM would yield a data rate of 133MHz. The same clock rate on DDR memory would transfer data at 266MHz.

6.1.2 The MPC8560’s DDR Memory Controller The MPC8560 has an integrated memory controller which supports JEDEC standard DDR Type 1 SDRAMs. The DDR memory controller is intended for use with x8 or x16 DDR SDRAMs. In addition, the memory controller will either be connected to all unbuffered DIMMs or all registered DIMMs. The memory controller does not support a mix of unbuffered and registered DIMMs in the same system. The memory controller includes these distinctive features: • Support for DDR Type 1 SDRAM • 64/72-bit DRAM data bus • Programmable settings for meeting all DRAM timing parameters • Many different DRAM configurations supported • Support for up to four banks, each bank independently addressable • Support for 64 Mbit to 1 Gbit devices with x8/x16 data ports

6.1.2.1 Available Signals The DDR SDRAM memory is controlled directly by the processor’s memory controller. The memory controller provides all the signals necessary for this control. The signals used by DDR can be split into three different groups.

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Table 6-1 details the signals provided by the MPC8560’s memory controller. Table 6-1. DDR SDRAM Interface Signals

I/O Signal Signal Description (w.r.t. Group Name Processor)

Address BA[0:1] Bank Address Bus Output & Control A[0:14] Address Bus Output RAS* Row Address Strobe Output CAS* Column Address Strobe Output WE* Write Enable Output CS[0:3]* Chip Selects Output Data DQ[0:63] Data Bus Input/Output DQS[0:8] Data Strobes Input/Output DM[0:8] Data Masks Outputs ECC[0:7] Error Correction Codes Input/Output Clock CLK[0:5] Clocks Output CLK[0:5]* Complement Clocks Output CKE[0:1] Clock Enable Output MSYNC_IN Delay Locked Loop Synchronization In Input MSYNC_OUT Delay Locked Loop Synchronization Out Output

6.2 Design Considerations The following section details design considerations.

6.2.1 Signal Termination The DDR SDRAM memory controller uses Stub Series Terminated Logic for 2.5 Volts, SSTL_2. To guard against unwanted signal reflections on the signal paths, these lines must be impedance matched. Typically this is achieved by the use of a series termination and a pull up resistor, connected to the termination voltage, VTT. The VTT voltage is implemented on the PCB as a split plane on the top layer. This is referred to as the “VTT Island”.

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The diagram in Figure 6-1 shows a single ended termination scheme.

MPC8560

Driver VTT V DDQ DDR

RT Receiver RS

VREF VOUT VIN

VSS

Figure 6-1. DDR Termination

Where RS = Series Resistance, RT = Termination Resistance.

On Torridon; RT = 27 Ohms, RS = 22Ohms.

6.2.2 Signal Connections

6.2.2.1 Address and Control Signals As well as fifteen address bits, A[0:14], the MPC8560’s memory controller provides two bank address bits, BA[0:1]. This allows a maximum address range of 1GBit. Four chip selects (CS[0:3]) provide connection to four separate physical banks. (As opposed to the Bank Address pins which select logical banks). As with “normal” SDRAM, the row and column addresses are latched using a Row Address Strobe (RAS*) and a Column Address Strobe (CAS*) respectively. A Write Enable signal (WE*) indicates a write cycle is in progress.

6.2.2.2 Data The data signal group is made up of four different types of signals; data bits, mask bits, strobe bits and parity bits. The data bus is 64 bits wide. Each byte of data has its own mask bit (used to mask specific data byte lanes during a write cycle) and its own strobe bit (used to latch the data). As well as this, the entire data bus is protected by parity. As with the data bits, the parity bits have their own dedicated mask and strobe bits.

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6.2.2.3 Clock The MPC8560’s memory controller provides 6 clock / complement clock pairs. The number of clock pairs actually used will depend on the physical implementation. For example, a single 64 bit DDR DIMM would require 3 clock pairs.

6.2.2.4 Serial Presence Detect Most DDR SDRAM DIMMs support Serial Presence Detect (SPD). The DDR SDRAM configuration is contained in a non-volatile ROM on the DDR SDRAM DIMM. This ROM is accessed by the processor’s I2C bus. Using the interface, the processor may interrogate the memory to check for its presence, size, speed etc. Note: The I2C signals are open drain and require pull ups.

6.2.2.5 DDR SDRAM Power The diagram in Figure 6-2 shows the voltage levels associated with the DDR SDRAM interface.

VTT

RT

VDD DDR SDRAM

VREF

Figure 6-2. DDR SDRAM Voltage Levels

The SSTL_2 interface uses a reference voltage and differential input to determine the logic levels.

VREF = VDD / 2

VTT = VREF

Where: VDD is the supply voltage

VREF is the reference voltage

VTT is the termination voltage Therefore,

VDD = 2.5 Volts

VTT = VREF = VDD / 2 = 1.25 Volts.

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6.2.2.6 Voltage Generation The required termination voltage for each DDR SDRAM DIMM is generated locally. i.e. each DDR DIMM will have its own dedicated power supply.

The reference voltage, VREF, and the termination voltage, VTT, are generated from the input voltage, VDD, using a National Semiconductor LP2995 voltage regulator. The diagram in Figure 6-3 shows the generation of these voltage levels.

VDD = 2.5V VTT = 1.25V

LP2995 VREF = 1.25V

Figure 6-3. DDR SDRAM Voltage Generation

6.3 Physical Implementation The diagram in Figure 6-4 shows the connection between the MPC8560 and the DDR SDRAM. On Torridon, the DDR is physically implemented as a SODIMM (Small Outline DRAM In Line Memory Module) however the connections shown will be very similar for a full sized DIMM or if using discrete devices.

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SO DIM M Socket MPC8560

64 D Q [0:63] D [0:63] Rs R T 8 EC C [0:7] CB[0:7] Rs R T 9 D M [0:8] D Q M [0:8] Rs R T 9 DQS[0:8] DQS[0:8] Rs R T A [0:12] 13 A [0:12] Rs R T A [13:14]

2 B A [0:1] Rs BA[0:1] R V

T TT

1 Island WE* *W E Rs R T

RAS* 1 *RAS Rs R T CAS* 1 *CAS Rs R T C S [0:1]* 2 *S0[0:1] Rs R T C S [2:3]*

C K E[0:1] 2 Rs C K E[0:1] R T 6 C LK [0:2]/*C LK [0:2] Rs C K [0:2]/ C LK [3:5]/*C LK [3:5] 3.3V *C K [0:2] Rp Rp MSYNC_OUT Rs MSYNC_IN 2 SDA/SCL SDA/SCL

V DD = 2.5V V DD V DD

V REF = 1.25V V REF

LP2995 V TT = 1.25V R T = 22R R S = 27R R p = 4K 7 Figure 6-4. 64 Bit DDR SDRAM

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The diagram in Figure 6-4 above shows the connection between the MPC8560 and the SODIMM on Torridon. Each processor can support an SODIMM up to 1Gbit. Thirteen address signals, A[0:12], and the two bank address signals, BA[0:1], are used to support this address range. The other two address signals, A[13:14], are not used and are left unconnected. Each processor support one SODIMM. As each SODIMM may have up to two banks, two chip selects, CS[0:1], are used. The other two chip selects, CS[2:3], which would be used if another DIMM were present on the design, are left unconnected. Again, due to the fact that only one SODIMM is used, only three of the clock pairs are required. Although not part of the DDR controller, the I2C interface is shown which supports the serial presence detect mechanism.

6.3.1 Schematics The schematics in Figure 6-5 show the MPC8560 - DDR SODIMM connection on Torridon.

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Figure 6-5. MPC8560 DDR Controller

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The schematics in Figure 6-5 above show the breakout from the MPC8560’s DDR controller The following points should be noted. • Torridon supports four MPC8560 processors, each with its own dedicated DDR memory. To differentiate the signals, the net names are preceded with a number: 0, 1, 2 or 3. • The undulating line connecting MSYNC_OUT and MSYNC_IN indicates that this signal length must be of a certain length. The length of this signal will be determined during the layout process. • Specific net names are given to the nets between the processor and the series resistor and the nets between the series resistor and the SODIMM. These specific net names are used when matching signal lengths during the layout. • The use of discrete resistors, as opposed to resistor networks, makes the layout easier with respect to matching signal lengths. Using resistor networks would force several signals to converge to a single package. This makes line length matching more difficult as it limits flexibility. The schematics in Figure 6-6 below show the connection to the SODIMM. The following points should be noted. • In this case, resistor networks can be used as opposed to individual ones. The constraints on these signals (i.e. the distance to the VTT island) are not as stringent as on the previous signal, hence more variations on signal lengths can be tolerated. • As a rule of thumb, two decoupling capacitors should be used for each resistor network. • In addition, two bulk capacitors (10uF) are also used.

• A voltage tap is taken from the mid point of the VTT rail. This monitors the actual voltage on this rail. This data is fed back to the voltage generator.

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Figure 6-6. SODIMM Connection

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The schematic in Figure 6-7 below shows the VTT voltage generation.

Figure 6-7. VTT Voltage Generation

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6.4 Layout The following section details layout considerations.

6.4.1 Address and Control The diagram in Figure 6-8 below shows the usage of the address and control signals on Torridon.

DDR MPC8560 SDRAM

A[0:12] Rs MA[0:12] A[13:14]

BA[0:1] Rs MBA[0:1]

RAS* Rs MRAS*

CAS* Rs MCAS*

WE* Rs MWE*

CS[0:1]* Rs MCS[0:1]* CS[2:3]*

CKE[0:1] Rs MCKE[0:1]

Figure 6-8. Address and Control

The length of each signal is the length of the etch from the processor to the series resistor plus the length of the etch between the series resistor and the DDR SODIMM. For example, the total length of the row address strobe is [RAS*] + [MRAS*]. To ensure correct operation, all the signals should be equal in length to each other to within 50mils. The diagram in Figure 6-9 shows the layout of the address and control group.

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6.4.2 Data The data group is made up of nine data lanes. Each data lane contains the byte of data, the strobe signal and the mask signal. The data signal group should be considered as nine separate byte lanes as detailed below in Table 6-2. Although during normal operation, the designation of these signal groups is all but transparent to the user, the grouping of these signal lanes is important during the layout of the data signal group. Table 6-2. Data Byte Lanes

Byte Lane Signal Name

0 DQ[0:7], DQS[0],DM[0] 1 DQ[8:15], DQS[1],DM[1] 2 DQ[16:23], DQS[2],DM[2] 3 DQ[24:31], DQS[3],DM[3] 3 DQ[32:39], DQS[4],DM[4] 3 DQ[40:47], DQS[5],DM[5] 6 DQ[48:55], DQS[6],DM[6] 7 DQ[56:63], DQS[7],DM[7] 8 ECC[0:7], DQS[8],DM[8]

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The diagram below in Figure 6-10 shows the data lanes.

DDR MPC8560 SDRAM

D[ 0: 7] , DQS0, DQM0 Rs MDQ[0:7], MDQS0, MDQM0

D[ 8: 15] , DQS1, DQM1 Rs MDQ[8:15], MDQS1, MDQM1

D[ 16: 23] , DQS2, DQM2 Rs MDQ[16:23], MDQS2, MDQM2

D[ 24: 31] , DQS3, DQM3 Rs MDQ[24:31], MDQS3, MDQM3

D[ 32: 39] , DQS4, DQM4 Rs MDQ[32:39], MDQS4, MDQM4

D[ 40: 47] , DQS5, DQM5 Rs MDQ[40:47], MDQS5, MDQM5

D[ 48: 55] , DQS6, DQM6 Rs MDQ[48:55], MDQS6, MDQM6

D[ 56: 63] , DQS7, DQM7 Rs MDQ[56:63], MDQS7, MDQM7

ECC[0:7], DQS8, DQM8 Rs MECC[ 0: 7] , MDQS8, MDQM8

Figure 6-10. Data

The following rules should be applied when laying out the data signals. • Route each data byte lane on a single layer. • Each data byte lane consists of 10 signals. • Each signal has two sections - between the processor and the series resistor and between the series resistor and the DIMM. • The 9 data byte lanes are as follows: (xDQ + xMDQ)[7:0], (xDM+xMDM)[0], (xDQS+xMDQS)[0] (xDQ + xMDQ)[15:8], (xDM+xMDM)[1], (xDQS+xMDQS)[1] (xDQ + xMDQ)[23:16], (xDM+xMDM)[2], (xDQS+xMDQS)[2] (xDQ + xMDQ)[31:24], (xDM+xMDM)[3], (xDQS+xMDQS)[3] (xDQ + xMDQ)[39:32], (xDM+xMDM)[4], (xDQS+xMDQS)[4] (xDQ + xMDQ)[47:40], (xDM+xMDM)[5], (xDQS+xMDQS)[5] (xDQ + xMDQ)[55:48], (xDM+xMDM)[6], (xDQS+xMDQS)[6] (xDQ + xMDQ)[63:56], (xDM+xMDM)[7], (xDQS+xMDQS)[7] (xECC + xMECC[7:0], (xDM+xMDM)[8], (xDQS+xMDQS)[8] Note: x = 0, 1, 2 or 3 • All signals on a single byte lane should be equal +/- 25mils • All byte lanes should be equal +/- 250mils

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The diagram in Figure 6-11 below shows the layout of one of the data lanes.

DQ[28] DQ[26] DQ[25] DQ[24] DQ[27] PowerQUICCIII DM3

DQ[29]

DQS3

DQ[30]

DQ[31]

Vias to Series Resistors

Figure 6-11. Data Layout

The diagram above shows the routing of the signals from the PowerQUICCIII to the series resistors, Rs.

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6.4.3 Clocks The processor’s on chip DLLs (Delay Locked Loop) uses a PCB trace to measure how much delay is needed, so that the timing can be optimised. PCB traces allow extremely precise and predictable delays. The diagram in Figure 6-12 below shows this.

CLK3/CLK3* MPC8560 Rs Not Used CLK4/CLK4* Rs CLK5/CLK5* Rs CKE0/CKE1 Rs MCKE0/MCKE1 DDR SDRAM CLK0/CLK0* MCLK0/MCLK0* Internal DLL Rs DLL Clock CLK1/CLK1* Rs MCLK1/MCLK1* DLL CLK2/CLK2* Rs MCLK2/MCLK2* DLL MSYNC_OUT Rs MSYNC_IN

Figure 6-12. DLL Configuration

The DLL loop should exactly match the signal length of the clock path. i.e. [MSYNC_OUT] + [MSYNC_IN] = [CLK0] + [MCLK0] [MSYNC_OUT] + [MSYNC_IN] = [CLK0*] + [MCLK0*] Where: CLK0 / CLK0* is the differential pair. [x] denotes the length of signal x. Rs is the series resistor. Note: The same is true for any other clock pairs.

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Torridon uses one SODIMM per processor to implement its DDR. This required 3 pairs of clock signals. The diagram in Figure 6-13 below shows the signals used in the clocking scheme.

DDR MPC8560 SDRAM CKE0 Rs MCKE0

CKE1 Rs MCKE1

CK0Rs MCK0

CK_N0Rs MCK_N0

CK1Rs MCK1

CK_N1Rs MCK_N1

CK2Rs MCK2

CK_N2Rs MCK_N2

MSYNC_OUT Rs MSYNC_IN

Figure 6-13. DDR Clock Signals

The following rules should be applied when laying out the clock signals. • Clock traces should be as short as possible • All the DDR clocks should be on the same PCB layer • The clocks must be treated as differential pairs. • Each clock signal must equal its differential partner +/- 10 mils. • They must be tightly coupled and remain (as far as possible) the same distance apart. • The clock pairs should not cross. If need be, the clock pairs can be swapped. i.e. clock pair 0 from the MPC8560 may be connected to clock pair 1 on the SODIMM. This is because all the clock pairs from the processor have identical timing. • The clock pairs should all be equal +/- 25mils. • The length of the clock should be equal to the length of the longest address signal. • [MSYNC_IN] + [MSYNC_OUT] = longest clock signal +/- 10mils.

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The diagram in Figure 6-14 below shows the clock routing between the processor and an SODIMM.

MSYNC_OUT MSYNC_IN

RS

Clock Pairs Figure 6-14. Clock Layout

6.4.4 DDR Power The following points should be noted about the LP2995. • AVIN and PVIN should be tied together for optimal performance. A local bypass capacitor should be placed as close as possible to the PVIN pin. • GND should be connected to a ground plane with multiple vias for improved thermal performance. • VSENCE, (used by the voltage regulator to monitor the voltage produced), should be connected to the VTT termination bus at the point where regulation is required. For mother-board applications an ideal location would be at the centre of the termination bus.

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• VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the memory controller. This provides the most accurate point for creating the reference voltage.

•VREF should be bypassed with a 0.01 uF or 0.1uF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the pin.

LP2995

By-Pass Capacitor

Figure 6-15. LP2995 Layout

The following points should be noted about the VREF voltage reference plane. • Use 30 mils trace between de coupling cap and destination • Maintain a 25 mils clearance from other nets. • Isolate VREF and/or shield with Ground. • Decouple using distributed 0.01uf and 0.1uf capacitors by the regulator, controller, and SODIMM slot. • Place one 0.01uf and 0.1uf near pin one of the SODIMM.

• Place one 0.1uf near the source of VREF, one near the VREF pin on the controller and two between the controller and the SODIMM.

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LP2995

30 mil Trace

De-Coupling Capacitor

Figure 6-16. VREF Layout

The following points should be noted about the VTT voltage reference plane. • Place the VTT island on the component side signals layer at the end of the bus behind the DIMM slot. • Use a wide-island trace for current capacity

• Place VTT generator as close to termination resistors as possible to minimize impedance (inductance).

• Place one or two 0.1uf de coupling capacitor by each termination RPACK on the VTT island to minimize the noise on VTT. Other bulk (10-22uf) de coupling is also recommended to be placed on the VTT island.

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The diagram in Figure 6-17 below shows an example of DDR layout.

VTT Island

Figure 6-17. VTT Island

To ensure the voltage on the Vtt island remains constant, it is monitored by the voltage regulator. The feedback from the island should be provided by tapping off the voltage at the mid point of the island. This is shown in Figure 6-18 below.

LP2995 VTT tapped from mid point of VTT island

Figure 6-18. VTT Voltage Monitoring

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This section describes the RapidIO sub-section on the Torridon Motherboard.

7.1 Overview

7.1.1 RapidIO Interconnect RapidIO is a point to point, packet switched interconnect. Developed as an open standard, the RapidIO architecture addresses the needs of present and future systems. RapidIO is focused as a processor, memory, and memory mapped I/O interface optimised for use inside a chassis.

7.1.2 The MPC8560’s RapidIO Controller The MPC8560 provides an integrated 8 bit parallel RapidIO interface which is based on the Rev 1.1 RapidIO Interconnect Specification. The port physically connects to other RapidIO devices via an 8/16 LP-LVDS (Link Protocol - Low Voltage Differential Signalling) physical layer. The physical layer of the RapidIO unit can operate at up to 500 MHz. As the interface is defined as a source synchronous, double data rate, LVDS signaling interconnect, the theoretical unidirectional peak bandwidth is 1 Gbyte/s for an 8-bit port.

7.1.3 Signals Descriptions RapidIO uses two distinct, uni-directional data paths; one for transmit and one for receive. Each data path is made up of the following components. • Data Signals - The actual data being transmitted • Clock - Used to clock the data • Frame - Indicates the start of a frame As RapidIO uses an LVDS interface, each signal is made up of two individual parts - the signal plus its differential compliment. Table 7-1 details the signals used for each point to point connection.

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Table 7-1. RapidIO Interface Signals

I/O Signal Data Path Description (w.r.t. Name Processor)

Receive RD[7:0]/RD[7:0]* 8 Bit Wide Data Input RCLK/RCLK* Clock Input RFRAME/RFRAME* Frame Input Transmit TD[7:0]/TD[7:0]* 8 Bit Wide Data Output TCLK/TCLK* Clock Output TFRAME/TFRAME* Frame Output

7.2 Design Considerations The following sections detail design considerations for RapidIO.

7.2.1 Signal Termination Due to the high speed of LVDS, impedance matching is very important. Any discontinuities in the trace will cause reflections which can degrade the signal quality. The LVDS outputs need a termination resistor to close the loop. Without termination resistors, the interface will not work. The value of the termination resistor, (RT), should match the differential impedance of the transmission line to reduce the reflections. Typically this will range from 90 ohms to 100 ohms. See Figure 7-1

Driver Receiver

Signal

RT Signal*

Figure 7-1. RapidIO Termination

As far as all Torridon is concerned, all of the RapidIO connections are between the MPC8560 processors and the Tundra TSI500 switch. Both the processors and the switch have the termination built in.

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7.2.2 Signal Connections The connection between each processor and the switch is very straight forward. It is simply a point to point connection. No additional components are required. The diagram in Figure 7-2 shows the connections of the RapidIO buses on Torridon.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 7-3 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE RapidIO

MPC8560

R eceive Transmit TCLK/TCLK* T D [7:0]/T D [7:0]* TFRAME/TFRAME* RD[7:0]/RD[7:0]* RCLK/RCLK* RFRAME/RFRAME*

MPC8560 T D [7:0]/T D [7:0]* Transm it Receive RD[7:0]/RD[7:0]* M PC8560 Transmit TFRAME/TFRAME* RFRAME/RFRAME* Receive Receive Transmit TCLK/TCLK* RCLK/RCLK* TSI500 RD[7:0]/RD[7:0]* T D [7:0]/T D [7:0]* RFRAME/RFRAME* Transmit TFRAME/TFRAME* Receive Receive Transmit RCLK/RCLK* TCLK/TCLK* Receive Transmit R D [7:0]/R D [7:0]* RCLK/RCLK* RFRAME/RFRAME* TCLK/TCLK* T D [7:0]/T D [7:0]* TFRAME/TFRAME*

Transmit Receive

MPC8560

Figure 7-2. RapidIO Signal Connections

Note: The receive port on the processor connects to the transmit port of the switch and vice-versa. Torridon uses a 4 port, parallel RapidIO switch from Tundra Semiconductor, the TSI500.

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7.3 Logic Analyser Connection To aid in the debug of RapidIO driver code and to allow the bus to be monitored, logic analyser connectors have been added to one of the RapidIO buses. Due to space constraints, it was only possible to add these connections onto one of the RapidIO buses, the one between the Boot Processor and the switch. Torridon has been designed to support the Tektronix analyser. The TLA700 logic analyser with the TMS805 RapidIO Support Package directly supports RapidIO. See Figure 7-3.

Figure 7-3. Tektronix TLA700 System

The logic analyser connects to the motherboard using compression fit probes, the P6880. The P6880 is a 34-channel high-density compression probe with differential clock and differential data. This probe utilises a connector less probe attach mechanism for quick and reliable connection to the motherboard. See Figure 7-4.

Figure 7-4. P6880 Probes

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The probes connect to the motherboard using compression fittings as shown in Figure 7-5.

Figure 7-5. Mother Board Connection

Each probe connects to a series of pads on the motherboard. As well as the 27 pads, the probe requires two holes. These holes are used to attach a back plate which ensures sufficient pressure can be applied to make a solid electrical connection. The diagram in Figure 7-6 shows the layout required for each probe.

Figure 7-6. Probe Layout

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7.4 Physical Connections Four probes are required to allow access to bus, two for receive and two for transmit. On Torridon, these four probes are labelled as P30, P31, P32 & P33. Table 7-2, Table 7-3, Table 7-4, and Table 7-5 below detail the connections to these four probes. Table 7-2. RapidIO Probe - P30

Pin# Signal Description

A1 RIO0_TXD0 RapidIO Transmit Data[0] A2 GND 0 Volts A3 RIO0_TXD0* RapidIO Transmit Data[0]* A4 RIO0_TXD2 RapidIO Transmit Data[2] A5 GND 0 Volts A6 RIO0_TXD2* RapidIO Transmit Data[2]* A7 RIO0_TXD4 RapidIO Transmit Data[4] A8 GND 0 Volts A9 RIO0_TXD4* RapidIO Transmit Data[4]* A10 RIO0_TXD6 RapidIO Transmit Data[6] A11 GND 0 Volts A12 RIO0_TXD6* RapidIO Transmit Data[6]* A13 RIO0_TFRAME RapidIO Transmit Frame A14 GND 0 Volts A15 RIO0_TFRAME* RapidIO Transmit Frame* B1 RIO0_TXD1 RapidIO Transmit Data[1] B2 GND 0 Volts B3 RIO0_TXD1* RapidIO Transmit Data[1]* B4 RIO0_TXD3 RapidIO Transmit Data[3] B5 GND 0 Volts B6 RIO0_TXD3* RapidIO Transmit Data[3]* B7 RIO0_TXD5 RapidIO Transmit Data[5] B8 GND 0 Volts B9 RIO0_TXD5* RapidIO Transmit Data[5]* B10 RIO0_TXD7 RapidIO Transmit Data[7] B11 GND 0 Volts B12 RIO0_TXD7* RapidIO Transmit Data[7]*

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Table 7-3. RapidIO Probe - P31

Pin# Signal Description

A1 NC Not Connected A2 GND 0 Volts A3 NC Not Connected A4 NC Not Connected A5 GND 0 Volts A6 NC Not Connected A7 NC Not Connected A8 GND 0 Volts A9 NC Not Connected A10 NC Not Connected A11 GND 0 Volts A12 NC Not Connected A13 RIO0_TCLK RapidIO Transmit Clock A14 GND 0 Volts A15 RIO0_TCLK* RapidIO Transmit Clock* B1 NC Not Connected B2 GND 0 Volts B3 NC Not Connected B4 NC Not Connected B5 GND 0 Volts B6 NC Not Connected B7 NC Not Connected B8 GND 0 Volts B9 NC Not Connected B10 NC Not Connected B11 GND 0 Volts B12 NC Not Connected

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Table 7-4. RapidIO Probe - P32

Pin# Signal Description

A1 RIO0_RXD0 RapidIO Receive Data[0] A2 GND 0 Volts A3 RIO0_RXD0* RapidIO Receive Data[0]* A4 RIO0_RXD2 RapidIO Receive Data[2] A5 GND 0 Volts A6 RIO0_RXD2* RapidIO Receive Data[2]* A7 RIO0_RXD4 RapidIO Receive Data[4] A8 GND 0 Volts A9 RIO0_RXD4* RapidIO Receive Data[4]* A10 RIO0_RXD6 RapidIO Receive Data[6] A11 GND 0 Volts A12 RIO0_RXD6* RapidIO Receive Data[6]* A13 RIO0_RFRAME RapidIO Receive Frame A14 GND 0 Volts A15 RIO0_RFRAME* RapidIO Receive Frame* B1 RIO0_RXD1 RapidIO Receive Data[1] B2 GND 0 Volts B3 RIO0_RXD1* RapidIO Receive Data[1]* B4 RIO0_RXD3 RapidIO Receive Data[3] B5 GND 0 Volts B6 RIO0_RXD3* RapidIO Receive Data[3]* B7 RIO0_RXD5 RapidIO Receive Data[5] B8 GND 0 Volts B9 RIO0_RXD5* RapidIO Receive Data[5]* B10 RIO0_RXD7 RapidIO Receive Data[7] B11 GND 0 Volts B12 RIO0_RXD7* RapidIO Receive Data[7]*

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Table 7-5. RapidIO Probe - P33

Pin# Signal Description

A1 NC Not Connected A2 GND 0 Volts A3 NC Not Connected A4 NC Not Connected A5 GND 0 Volts A6 NC Not Connected A7 NC Not Connected A8 GND 0 Volts A9 NC Not Connected A10 NC Not Connected A11 GND 0 Volts A12 NC Not Connected A13 RIO0_RCLK RapidIO Receive Clock A14 GND 0 Volts A15 RIO0_RCLK* RapidIO Receive Clock* B1 NC Not Connected B2 GND 0 Volts B3 NC Not Connected B4 NC Not Connected B5 GND 0 Volts B6 NC Not Connected B7 NC Not Connected B8 GND 0 Volts B9 NC Not Connected B10 NC Not Connected B11 GND 0 Volts B12 NC Not Connected

Note: There are four distinct RapidIO busses on Torridon. Each bus is labelled RIOx_yyy where x is the bus number (0, 1, 2, or 3) and yyy is the signal name. (e.g. RCLK, TFRAME etc.) RIO0 is the bus between the Boot Processor and the switch; RIO1 is the bus between Work Processor 1and the switch etc.

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7.5 Layout Considerations RapidIO uses differential signalling. This means that each individual signal is actually two separate wires. Care must be taken when routing these signals. • The signals should be tightly coupled together. • Each signal should be equal to its complimentary signal to within a tolerance of +/- 10mils (0.02mm) • Within a particular receive or transmit path, all signals should be equal to within a tolerance of +/- 50mils (0.1mm) • The number of vias on any differential pair must be less than or equal to 4 • The transmit signal path should routed on a separate layer to the receive signal path • RapidIO signals should be routed on a different plane than single ended signals • Each of the four RapidIO busses on Torridon (RIO0_yyy, RIO1_yyy, RIO2_yyy and RIO3_yyy) are totally independent. There is no requirement to match signals between busses • Within each RapidIO bus, the transmit and receive paths can be treated as independent. There is no requirement to match signals between receive and transmit paths • The length of the bus should not exceed 3 inches. The board shots in Figure 7-7 show some examples of RapidIO routing on Torridon.

Differential Pairs

PowerQUICCIII TSI500 Figure 7-7. RapidIO Receive Path Layout

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The diagram above shows a receive path between one of the MPC8560’s and the TSI500 switch. Note that each signal pair has been tightly coupled and effectively routed as a single signal. Also note that the shortest signal has been lengthened to match the longest signal length. The board shot above shows layer 8 of the PCB. The transmit path for this connection is routed separately on layer 11. The diagram in Figure 7-8 shows the routing between the Boot Processor and the switch. This path incorporates the probes for the logic analyser.

TSI500

Differential Pairs

Logic Analyser Probe Connections

PowerQUICCIII Figure 7-8. RapidIO Receive Path Layout (With Logic Probes)

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 7-12 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 8 GBit Ethernet

This section describes the GBit Ethernet sub-section on the Torridon Motherboard.

8.1 Overview Torridon provides five GBit Ethernet ports. The Boot Processor provides two of these ports, the other three are provided by each of the Work Processors. Connection to the outside world is made via IEEE 802.3 compliant twisted pair (T.P.) ports (10/100/1000-BaseT). Each port is controlled by the MPC8560’s triple speed Ethernet controller (TSEC). The TSEC incorporates a MAC that supports 10, 100,and 1000 Mbps Ethernet/802.3 networks. The TSEC includes address/data filtering, data insertion and extraction, 2-kbyte FIFOs, and DMA functions.The TSEC network interface supports multiple options. One is the Media Independent Interface (MII) option which uses 18 I/O pins and supports both data and a management interface to the PHY. The MII supports both 10 and 100 Mbps. The GBit Media Independent Interface (GMII) option is a super-set of the MII signals and supports data rates up to 1000Mbps.

8.2 GBit Ethernet Connection The diagram in Figure 8-1 shows the basic parts to allow the MPC8560 to interface to the outside world via GBit Ethernet.

MPC8560

PHY MagneticsRJ45

GMII TSEC

Figure 8-1. GBit Ethernet Connection

The MPC8560’s Triple Speed Ethernet Controller (TSEC) connects to the Ethernet physical device (PHY) via a GBit Media Independent Interface (GMII). Electrical isolation is provided between the PHY and the external connector, (RJ45), via a magnetic circuit. Each of these blocks will be discussed in more detail below.

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8.3 GMII Interface As 1000Mbps data rates are supported on Torridon, the GMII interface is used to interface the processor’s TSEC to its respective PHY device. Table 8-1 and Figure 8-2 detail the signals used in the GMII interface. Table 8-1. TSEC GMII Interface Signals

I/O Signal Description (w.r.t. Processor)

COL Collision Input CRS Carrier Sense Input GTX_CLK GBit Transmit Clock Output GTX_CLK125 GBit Transmit 125MHz Source Input

MDC Management Data Clock Output MDIO Management Data Input/Output Input/Output RX_CLK Receive Clock Input RX_DV Receive Data Valid Input RXD[7:0] Receive Data Input RX_ER Receive Error Input TX_CLK Transmit Clock Input TXD[7:0] Transmit Data Output TX_EN Transmit Enable Output TX_ER Transmit Error Output

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Gigabyte Transmit Clock (GTX_CLK)

Gigabyte Clock (GTX_CLK125) Transmit Error (TX_ER) Transmit Data (TXD[7:0])

Transmit Enable (TX_EN) RJ45 with Built in Transmit Clock (TX_CLK) Magnetics Collision Detect (COL) MPC8560 Receive Error (RX_ER) 88E1011 Receive Data (RXD[7:0]) Receive Clock (RX_CLK) Status Receive Data Valid (RX_DV]) LEDS Carrier Sense (CRS)

Management Data Clock (MDC) Management Data I/O (MDIO) Configuration Reset PHY (Gx_RESET_N) Pins Interrupt PHY (Gx_INT_N)

Figure 8-2. GMII Interface

8.4 PHY Device The Marvell 88E1011 device provides the physical interface for the Ethernet connection on Torridon. The 88E1011 connects to the TSEC via the GBit Media Independent Interface, GMII, which is used for both the device’s control and data path. The PHY may be reset independently by a general purpose pin on the MPC8560. It may also be reset by setting the most significant bit in the 88E1011’s control register via the MII management interface. Each PHY has the ability to interrupt the MPC8560 by the assertion of its respective interrupt (*INT) pin. The polarity of this interrupt is programmable. The initial power on status of the PHY is determined by seven configuration pins, CONFIG[6:0]. These pins determine various initial setting such as the PHY address, connection speed etc. Table 8-2 details the possible settings.

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Table 8-2. PHY Configuration Pins

Pin Bit[2] Bit[1] Bit[0]

Config0 PHYADR[2] PHYADR[1] PHYADR[0] Config1 ENA_PAUSE PHYADR[4] PHYADR[3] Config2 ANEG[3] ANEG[2] ANEG[1] Config3 ANEG[0] ENA_XC DIS_125 Config4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_MODE[0] Config5 DIS_FC DIS_SLEEP HWCFG_MODE[3] Config6 SEL_BDT INT_POL 75/50 Ohm

Note: Refer to the 88E1011 Data Sheet for full details of the settings available Each configuration pin defines three configuration bits. The three bit value is determined by tying the configuration pin to one of the other pins on the device. Table 8-3 details the pins used to set the values of the configuration pins. Table 8-3. Setting PHY Configuration Pins

Pin Bit[2:0]

VDD0 111 LED_LINK10 110 LED_LINK100 101 LED_LINK1000 100 LED_DUPLEX 011 LED_RX 010 LED_TX 001 VSS 000

For example to set Config0 to 101, it must be connected to the LED_LINK100 pin.

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Each one of the configuration pins must be tied to the appropriate pin. On Torridon each one of the PHY are configured as shown in Table 8-4. Table 8-4. PHY Configuration Pins on Torridon

Pin Connected to Bit[2:0]

Config0 VSS 000 Config1 VSS 000 Config2 LED_LINK10 110 Config3 VSS 000 Config4 VDD0 111 Config5 VDD0 111 Config6 VSS 000

This sets the PHYs up in the following initial state. • PHY address set to 0 1 • MAC Pause is not implemented • Auto negotiate - advertise all capabilities, force master operation • Disable MDI crossover • Enable generation of the 125MHz clock • Configure device to run in GMII to copper mode • Disable energy detect • Disable fibre/copper selection • Select the MDC/MDIO interface • Select the interrupt to be active high • Select 50 ohm termination to fibre. (Note: This is irrelevant as there is no support for fibre on Torridon) 1 Note: The second PHY on the Boot Processor is set to address 1 by connecting Config0 pin to LED_TX instead of VSS. All the other PHYs have an address of 0.

8.5 Magnetics & RJ45 The PHY device provides an eight pin media dependent interface (MDI[3:0]+/-). This interface is made up of four differential pairs of signals which, via the magnetics, provide the connection to the RJ45 connector.

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On Torridon, the magnetics and the RJ45 connector are integrated on a single device. As well as simplifying the design, this is a more space efficient solution. The device also includes two built in LEDs. See Figure 8-3 and Table 8-5.

Figure 8-3. RJ45 with Integrated Magnetics

Table 8-5. Ethernet Connections

Pin# Signal Description

1 Tx+ Transmit Data +ve 2 Tx- Transmit Data -ve 3 Rx+ Receive Data +ve 4 GND 0 Volts 5 GND 0 Volts 6 Rx- Receive Data -ve 7 GND 0 Volts 8 GND 0 Volts

8.6 Layout Considerations As far as layout was concerned, the routing of the signals on the GMII bus (between the MPC8560 and the PHY), was not overly critical. Due to the fact that the PHY is situated close to the processor and the interface is digital, apart for following sound layout guidelines, no additional constraints were imposed on this interface. However, the MDI bus between the PHY and the magnetics was more critical due to the relatively long signal lengths involved. The following constraints were imposed on the layout of the MDI bus. • Each pair (e.g. Tx+ and TX-) should be routed so they are tightly coupled in the same layer and the separation between the two traces of the pair should remain constant over the entire length • The signals in a pair should be equal in length to within a tolerance of +/- 10 mils (0.02mm)

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• The signals across the bus should be equal in length to within a tolerance of +/- 50 mils (0.1mm) • The number of vias on any signal should be less than or equal to 4. See Figure 8-4 below.

Signal pairs tightly coupled

4 Pairs of Differential Signals

Signals lengthened To match length

Figure 8-4. MDI Bus Layout

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MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 8-8 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 9 UART

This section describes the UART sub-section on the Torridon Motherboard.

9.1 Overview Each of the processors support a single RS232 port. The MPC8560’s SCC1 controller with a MAX3229 level translator, implements the standard RS232 serial I/O protocol. A DB9 connector is attached to the front of the board provides access to the boot processor’s serial port. The serial ports for the three work processors are accessible on three separate headers. See Figure 9-1. Note the additional SCC control signals, Request to Send (RTS), Carrier Detect (CD) and Clear to Send (CTS) are not connected hence hardware flow control is not supported on this interface.

MPC8560 Transmit Data (TXD)

1 D-Connector C Receive Data (RXD)

C MAX3229 S

Figure 9-1. RS232 Interface

Table 9-1 shows the port usage on the MPC8560 for the serial ports. Table 9-1. Specific MPC8560 - UART Signals

I/O MPC8560 Signal Description (w.r.t. Pin Processor)

SCC1_RXD PD[31] RS232 Receive Data Input SCC1_TXD PD[30] RS232 Transmit Data Output

Note: These signals are pin compatible with the MPC8540’s DUART controller. This means that the MPC8560 may be replaced with an MPC8540 and the RS232 interface will still function.

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Connection to the debug port is made via a standard 9 pin d-type connector. The pin out is shown in Table 9-2. Table 9-2. RS232 Connector

Pin# Signal Connection

1 CD Not connected 2 RXD To SCC1 TXD 3 TXD To SCC1 RXD 4 DTR Not connected 5 GND 0 Volts 6 DSR Not connected 7 RTS Not connected 8 CTS Not connected 9 RI Not connected

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 9-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Overview

The schematics are shown in Figure 9-2 and Figure 9-3.

Figure 9-2. MPC8560 CPM

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Figure 9-3. RS232 Transceiver

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The following should be noted about the schematics: • Only the DEBUG_RXD and DEBUG_TXD signals from the CPM are used to drive the RS232 interface. The other signals shown in the schematics are to control/monitor other devices on Torridon. • The small package size of the MAX3229 helps limit board space

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MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 9-6 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 10 PCI

This section describes the PCI sub-section on the Torridon Motherboard.

10.1 Overview Although Torridon supports four processors, only one of the PCI busses available is utilised. The boot processor provides a single 64 bit PCI slot. The PCI busses on the three Work Processors are not used, these busses are simply left as no connects on the motherboard. As well as providing a 64 bit PCI slot, the Boot Processor also provides an interface to the Via Southbridge chip. This interface is further discussed in Chapter 11, “Peripheral Support”. The diagram in Figure 10-1 details the connection to the Boot Processor’s PCI bus.

MPC8560

64 Bit PCI Bus PCI REQ1* GNT1*

Bus Slot PCI Ctrl.

32 Bit PCI Bus REQ0* GNT0* Via South Bridge South Via

Figure 10-1. Boot Processor’s PCI Bus

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The PCI connection to the PCI slot and the Via chip are very similar with a few notable differences. • Each “peripheral” uses a separate request/grant pair. The Via chip uses REQ0#/GNT0#, the PCI slot uses REQ1#/GNT1# • The Via chip only uses 32 bits of the 64 bit bus.

10.2 PCI Clocks In terms of clocks, the PCI bus sees three separate devices. • The MPC8560 • The PCI slot • The Via chip All three devices are driven from a single 33MHz clock oscillator. The oscillator is passed through a fan out buffer to provide sufficient drive capability. Refer to Section 14.2, “System Clocks” for details.

10.3 Bus Connectivity For the majority of the PCI signals, a straight point to point connection is made between the Boot processor, the interface connector and the Via chip.

10.4 PCI Configuration The PCI interface on the Torridon board can be configured via switch settings. These switches are used to configure the following. • The impedance of the interface • Switch between 32 and 64 bit mode • Enable/disable the internal arbitration unit • Enable/disable the PCI debug feature Refer to Section 4.2, “MPC8560 Processor Configuration” for details.

10.5 Schematics The diagrams in Figure 10-2 and Figure 10-3 show the schematics pertaining to the PCI bus.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 10-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics

Figure 10-2. MPC8560’s PCI Interface - Schematics

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The following should be noted about the circuitry. • To guard against spurious requests/acknowledges, pull-ups are added to the request/acknowledge lines • Pull-ups are added to the unused request inputs. • As the processor is the host, which initiates the PCI transactions, the IDSEL pin is pulled low. This will guard against it replying to one of its own bus transactions.

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Figure 10-3. PCI Slot - Schematics

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The following should be noted about the circuitry. • Control signals are pulled up • As the PCI bus on the MPC8560 is 3.3V only, the I/O voltage is set to 3.3V • As the PCI bus is limited to 33MHz (This is the maximum speed of the Via chip), the M66EN signal, which advertises bus speed capability, is tied to 33MHz. • The IDSEL pin, which sets the address range for this PCI slot, is tied to address pin 19. (This must be a unique address space on the bus)

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 10-6 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 11 Peripheral Support

This section describes the Peripheral sub-section on the Torridon Motherboard.

11.1 Overview The “Super South” South Bridge (VT82C686) from Via Technologies provides additional IO on Torridon; namely IDE, USB and PS2 interfaces. The South Bridge is connected directly to the PCI bus on the boot processor. Please refer to Chapter 10, “PCI” for details of the interface.

11.2 IDE Interface Two IDE interfaces, the Primary and the Secondary, are provided on Torridon. These are available at two separate 40 pin connectors, P23 and P24. The IDE interfaces are driven directly from the Via Southbridge device. The schematics are shown in Figure 11-1 and Figure 11-2. The following should be noted about the schematics • Series resistors are used to smooth out over/under shoots • A 2 pin header (HD23) allows a front panel LED to be added which will indicate when the IDE interface is active. • An inverter is added on the reset drive signal (RSTDRV) to switch the polarity. (The RSTDRV signal from the Via is active high, the IDE interface expects and active low signal)

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Figure 11-1. Primary IDE Interface - Schematics

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Figure 11-2. Secondary IDE Interface - Schematics

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11.2.1 Compact Flash Support

11.2.1.1 Overview A CompactFlash card is essentially a small form factor card version of PCMCIA PC Card ATA (AT Attachment) specification and includes a True IDE (Integrated Drive Electronics) mode which is compatible with the ATA/ATAPI-4 specification. As such, there are 3 distinct interface modes that a CompactFlash card can use: • PC Card Memory Mode (uses WE#, OE# to access memory locations) • PC Card I/O Mode (uses IOWR#, IORD# to access I/O locations) • True IDE Mode (uses IOWR#, IORD# to access I/O locations)

11.2.1.2 Implementation on Torridon The CompactFlash card is essentially a solid state ATA disk drive. On Torridon, the CompactFlash is configured in True IDE mode. True IDE mode is selected by the OE* signal (also known as the ATA_SEL* pin) which is grounded during the assertion of reset. Note: In True IDE mode, removal and hot insertion (i.e. insertion and removal of the card while the system is powered on) is not supported. CompactFlash on Torridon is supported via a 3rd party adapter board which connects into one of the IDE headers on the board. These boards provide a standard IDE interface. See Table 11-1and Figure 11-3below. Table 11-1. CompactFlash Interconnect

Signal Pin# Description

A[2:0] 18,19,20 Address Pins. Used to select one of eight registers in the task file. A[10:3] 8,10,11,12, Address Pins. Not Used; connected to ground. 14,15,16,17 D[15:0] 31,30,29,28, Data Pins. 0 is LSB, 15 is MSB. 27,49,48,47, In True IDE mode, all task file operations are in byte mode on the low order bus and 6,5,4,3,2,23, all the data transfers use the 16 bit bus. 22,21 CS_N[1:0 32,7 Chip Selects. Used to select either the task file registers or Alternate Status Register ] and Device Control Register. ATA_SEL 9 Enables True IDE Mode. Tied to ground. * IORD* 34 IO Read Strobe. Indicates when the CompactFlash Card should drive its data on the bus.

IOWD* 35 IO Write Strobe. Indicates valid data is on the bus.

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Table 11-1. CompactFlash Interconnect (continued)

Signal Pin# Description

CSEL* 39 Used to configure the CompactFlash card as a master or a slave. Tied to ground to configure card as a master. RESET* 41 Reset the Compact Flash. INTRQ 37 Interrupt request to controller. IORDY* 42 IO Ready. PDIAG* 46 Passed Diagnostic. Not connected. (No slave device connected) DASP* 45 Drive Active/Slave Present. Led indicates activity CD[2:1]* 25,26 Card Detect. Not connected. (Hot Insertion not supported) IOIS16* 24 16 Bit Access. Not connected. (16 bit transfer assumed) VS[2:1]* 40,33 Voltage Sense. Not Connected. INPACK* 43 Input Acknowledge. Not used in True IDE mode; connected to +3.3V REG 44 Register Select. Not used in True IDE mode; connected to +3.3V WE* 36 Write Enable. Not used in True IDE mode; connected to +3.3V VCC 13,38 +3.3Volts GND 1,50 0 Volts.

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3 rd Party CompactFlash IDE Adapter VIA ‘686 Connector Card

A[2:0] A[2:0] D[15:0] D[15:0] CS1_N/CS3_N CS[1:0] IO R D _N IO RD _N IO W D _N IO W D _N RSTDRV_N RESET_N IR Q 15 IN TR Q IORDY IORDY* DRQ +3.3V DASP* DACK

PDIAG* CD[2:1] IO IS16* VS[2:1] +3.3V VCC IN PAC K * REG WE* A[10:3] CSEL* ATA_SEL* GND

0V Figure 11-3. CompactFlash Connection

11.3 USB The Via chip provides two USB interfaces. A 10 pin header, HD27, allows connectivity to a standard USB connector. The schematics are shown in Figure 11-4. The following should be noted • The USB interface is clocked from a separate 48MHz clock source • Fuses (F1, F2) protect against incorrect connectivity. In the event of a USB cable being connected incorrectly, theses fuses will protect the power supply on the board. Incorrect connectivity may lead to the fuse being blown. In this event, the fuse would need to be replaced.

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Figure 11-4. USB - Schematics

11.4 PS2 The ability to use a PS2 keyboard and mouse is also provided by the Via chip. A stacked 6 pin DIN, P35, provides the interface. The schematics are shown in Figure 11-5.

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Figure 11-5. PS2 - Schematics

The following should be noted. • A fuse (F3) protects the 5 Volt supply • Pull-ups are added to all the data/clock signals.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 11-8 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 12 Communications

This section describes the Communications sub-section on the Torridon Motherboard.

12.1 Overview

12.2 Test In addition to the five GBit Ethernet ports, Torridon provides connectivity to the outside world via 1. Two 128 pin connectors. These “QUADS” compatible connectors are pin compatible with the family of ADS boards from Motorola. 2. A UTOPIA Interface

12.3 QUADS Compatible Headers The QUADS compatible connectors are implemented using two 128 pin headers. These provide connection to the processor’s CPM and host bus. On Torridon, these connectors are controlled by Work Processor 1. These would allow the connection of an add on card which would typically provide additional PHYs. For example, the TCOM card shown in Figure 12-1 provides the PHYS necessary to connect to an E1/T1 interface.

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Figure 12-1. E1/T1 Card

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As shown in Figure 12-2, two headers are provided for connectivity. As shown in Figure 12-3, one of these provides access to the CPM; the other to a de-multiplexed version of the host bus. Header Header QUADS QUADS QUADS Compatible Compatible Power UTOPIA Bit 16 J5 J3 Voltage Regulation MPC8560 DDR UART2 Flash + Latch GBit2 Work Processor 1 DDR Reset Clock Generation RIO Access DDR GBit5 GBit1 UART1 Switch TSI500 RapidIO RapidIO MPC8560 MPC8560 Work Processor 2 Processor Work GBit1 GBit2 GBit3 GBit4 UART1 UART2 UART3 UART4 GBit5 UART3 GBit3 Boot Processor Boot DDR PHY PHY PHY PHY PHY PHY PHY PHY PHY South Bridge MPC8560

64 Bit PCI UART4 GBit4 Work Processor 3

USB IDE IDE RJ45 RJ45 RJ45 RJ45 RJ45 RJ11 RJ11 RJ11 D-Type UART Gbit Ethernet Gbit Figure 12-2. QUADS Compatible Headers

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MPC8560

LAD[0:31] LA[16:26] Local Buffer LALE LD[0:15] Bus & LBCTL Latch Control Ctrl.

PA[31:0] PB[31:4] CPM PC[31:0] PD[31:4]

Figure 12-3. Connectivity to the QUADS Headers

The following tables (Table 12-1, Table 12-2, Table 12-3, Table 12-4, Table 12-5, Table 12-6, Table 12-7, and Table 12-8) detail the pinout required to allow QUADS compatible expansion cards to be used.

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Table 12-1. ADS Compatible Expansion Connector - P28 - Row A

CONNECTO SIGNAL DESCRIPTION R PIN#

A1 LA16 Local Address Bus [16] A2 LA17 Local Address Bus [17] A3 LA18 Local Address Bus [18] A4 LA19 Local Address Bus [19] A5 LA20 Local Address Bus [20] A6 LA21 Local Address Bus [12] A7 LA22 Local Address Bus [22] A8 LA23 Local Address Bus [23] A9 LA24 Local Address Bus [24] A10 LA25 Local Address Bus [25] A11 LA26 Local Address Bus [26] A12 BLA27 Burst Local Address Bus [27] A13 BLA28 Burst Local Address Bus [28] A14 BLA29 Burst Local Address Bus [29] A15 BLA30 Burst Local Address Bus [30] A16 BLA31 Burst Local Address Bus [31] A17 +12V + 12 Volts A18 +12V + 12 Volts A19 NC Not Connected A20 +3.3V + 3.3 Volts A21 +3.3V + 3.3 Volts A22 +3.3V + 3.3 Volts A23 +3.3V + 3.3 Volts A24 +3.3V + 3.3 Volts A25 NC Not Connected A26 +5V + 5 Volts A27 +5V + 5 Volts A28 +5V + 5 Volts A29 +5V + 5 Volts A30 +5V + 5 Volts A31 +5V + 5 Volts A32 +5V + 5 Volts

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Table 12-2. ADS Compatible Expansion Connector - P28 - Row B

CONNECTO SIGNAL DESCRIPTION R PIN#

B1 0V 0 Volts B2 0V 0 Volts B3 0V 0 Volts B4 NC Not Connected B5 NC Not Connected B6 NC Not Connected B7 NC Not Connected B8 NC Not Connected B9 NC Not Connected B10 NC Not Connected B11 NC Not Connected B12 NC Not Connected B13 NC Not Connected B14 NC Not Connected B15 NC Not Connected B16 0V 0 Volts B17 0V 0 Volts B18 NC Not Connected B19 NC Not Connected B20 NC Not Connected B21 +3.3V + 3.3 Volts B22 +3.3V + 3.3 Volts B23 +3.3V + 3.3 Volts B24 +3.3V + 3.3 Volts B25 NC Not Connected B26 +5V + 5 Volts B27 +5V + 5 Volts B28 +5V + 5 Volts B29 +5V + 5 Volts B30 +5V + 5 Volts B31 +5V + 5 Volts B32 +5V + 5 Volts

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Table 12-3. ADS Compatible Expansion Connector - P28 - Row C

CONNECTOR SIGNAL DESCRIPTION PIN# C1 0V 0 Volts C2 BCLK2 Buffered Clock 2 C3 0V 0 Volts C4 BLCS_N6 Buffered Local Chip Select 6 C5 BLCS_N7 Buffered Local Chip Select 7 C6 0V 0 Volts C7 NC Not Connected C8 NC Not Connected C9 NC Not Connected C10 HRESET Hard Reset C11 IRQ6* Interrupt 6 C12 IRQ7* INterrupt 7 C13 0V 0 Volts C14 LD0 Local Data Bus [0] C15 LD1 Local Data Bus [1] C16 LD2 Local Data Bus [2] C17 LD3 Local Data Bus [3] C18 LD4 Local Data Bus [4] C19 LD5 Local Data Bus [5] C20 LD6 Local Data Bus [6] C21 LD7 Local Data Bus [7] C22 LD8 Local Data Bus [8] C23 LD9 Local Data Bus [9] C24 LD10 Local Data Bus [10] C25 LD11 Local Data Bus [11] C26 LD12 Local Data Bus [12] C27 LD13 Local Data Bus [13] C28 LD14 Local Data Bus [14] C29 LD15 Local Data Bus [15] C30 NC Not Connected C31 NC Not Connected C32 NC Not Connected

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Table 12-4. ADS Compatible Expansion Connector - P28 - Row B

CONNECTO SIGNAL DESCRIPTION R PIN#

D1 0V 0 Volts D2 0V 0 Volts D3 0V 0 Volts D4 BLWE_N0 Buffered Local Write Enable 0 D5 BLWE_N0 Buffered Local Write Enable 0 D6 0V 0 Volts D7 BLGPL0 Buffered Local General Purpose Line 0 D8 BLGPL1 Buffered Local General Purpose Line 1 D9 BLGPL2 Buffered Local General Purpose Line 2 D10 BLGPL3 Buffered Local General Purpose Line 3 D11 BLGPL4 Buffered Local General Purpose Line 4 D12 BLGPL5 Buffered Local General Purpose Line 5 D13 0V 0 Volts D14 BALE Buffered Address Latch Enable D15 BLBCTL Buffered Local Bus Control D16 0V 0 Volts D17 0V 0 Volts D18 0V 0 Volts D19 0V 0 Volts D20 0V 0 Volts D21 0V 0 Volts D22 0V 0 Volts D23 0V 0 Volts D24 0V 0 Volts D25 0V 0 Volts D26 0V 0 Volts D27 0V 0 Volts D28 0V 0 Volts D29 0V 0 Volts D30 0V 0 Volts D31 0V 0 Volts D32 0V 0 Volts

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Table 12-5. ADS Compatible Expansion Connector - P29 - Row A

CONNECTO SIGNAL DESCRIPTION R PIN#

A1 PD[31] Port D [31] A2 PD[30] Port D [30] A3 PD[29] Port D [29] A4 PD[28] Port D [28] A5 PD[27] Port D [27] A6 PD[26] Port D [26] A7 PD[25] Port D [25] A8 PD[24] Port D [24] A9 PD[23] Port D [23] A10 PD[22] Port D [22] A11 PD[21] Port D [21] A12 PD[20] Port D [20] A13 PD[19] Port D [19] A14 PD[18] Port D [18] A15 PD[17] Port D [17] A16 PD[16] Port D [16] A17 PD[15] Port D [15] A18 PD[14] Port D [14] A19 PD[13] Port D [13] A20 PD[12] Port D [12] A21 PD[11] Port D [11] A22 PD[10] Port D [10] A23 PD[9] Port D [9] A24 PD[8] Port D [8] A25 PD[7] Port D [7] A26 PD[6] Port D [6] A27 PD[5] Port D [5] A28 PD[4] Port D [4] A29 +5V + 5 Volts A30 +5V + 5 Volts A31 +5V + 5 Volts A32 +5V + 5 Volts

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Table 12-6. ADS Compatible Expansion Connector - P29 - Row B

CONNECTO SIGNAL DESCRIPTION R PIN#

B1 PA[31] Port A [31] B2 PA[30] Port A [30] B3 PA[29] Port A [29] B4 PA[28] Port A [28] B5 PA[27] Port A [27] B6 PA[26] Port A [26] B7 PA[25] Port A [25] B8 PA[24] Port A [24] B9 PA[23] Port A [23] B10 PA[22] Port A [22] B11 PA[21] Port A [21] B12 PA[20] Port A [20] B13 PA[19] Port A [19] B14 PA[18] Port A [18] B15 PA[17] Port A [17] B16 PA[16] Port A [16] B17 PA[15] Port A [15] B18 PA[14] Port A [14] B19 PA[13] Port A [13] B20 PA[12] Port A [12] B21 PA[11] Port A [11] B22 PA[10] Port A [10] B23 PA[9] Port A [9] B24 PA[8] Port A [8] B25 PA[7] Port A [7] B26 PA[6] Port A [6] B27 PA[5] Port A [5] B28 PA[4] Port A [4] B29 PA[3] Port A [3] B30 PA[2] Port A [2] B31 PA[1] Port A [1] B32 PA[0] Port A [0]

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Table 12-7. ADS Compatible Expansion Connector - P29 - Row C

CONNECTO SIGNAL DESCRIPTION R PIN#

C1 PB[31] Port B [31] C2 PB[30] Port B [30] C3 PB[29] Port B [29] C4 PB[28] Port B [28] C5 PB[27] Port B [27] C6 PB[26] Port B [26] C7 PB[25] Port B [25] C8 PB[24] Port B [24] C9 PB[23] Port B [23] C10 PB[22] Port B [22] C11 PB[21] Port B [21] C12 PB[20] Port B [20] C13 PB[19] Port B [19] C14 PB[18] Port B [18] C15 PB[17] Port B [17] C16 PB[16] Port B [16] C17 PB[15] Port B [15] C18 PB[14] Port B [14] C19 PB[13] Port B [13] C20 PB[12] Port B [12] C21 PB[11] Port B [11] C22 PB[10] Port B [10] C23 PB[9] Port B [9] C24 PB[8] Port B [8] C25 PB[7] Port B [7] C26 PB[6] Port B [6] C27 PB[5] Port B [5] C28 PB[4] Port B [4] C29 NC Not Connected C30 0V 0 Volts C31 0V 0 Volts C32 0V 0 Volts

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Table 12-8. ADS Compatible Expansion Connector - P29 - Row D

CONNECTO SIGNAL DESCRIPTION R PIN#

D1 PC[31] Port C [31] D2 PC[30] Port C [30] D3 PC[29] Port C [29] D4 PC[28] Port C [28] D5 PC[27] Port C [27] D6 PC[26] Port C [26] D7 PC[25] Port C [25] D8 PC[24] Port C [24] D9 PC[23] Port C [23] D10 PC[22] Port C [22] D11 PC[21] Port C [21] D12 PC[20] Port C [20] D13 PC[19] Port C [19] D14 PC[18] Port C [18] D15 PC[17] Port C [17] D16 PC[16] Port C [16] D17 PC[15] Port C [15] D18 PC[14] Port C [14] D19 PC[13] Port C [13] D20 PC[12] Port C [12] D21 PC[11] Port C [11] D22 PC[10] Port C [10] D23 PC[9] Port C [9] D24 PC[8] Port C [8] D25 PC[7] Port C [7] D26 PC[6] Port C [6] D27 PC[5] Port C [5] D28 PC[4] Port C [4] D29 PC[3] Port C [3] D30 PC[2] Port C [2] D31 PC[1] Port C [1] D32 PC[0] Port C [0]

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12.4 UTOPIA Interface Some of the CPM pins from Work Processor 1are pinned out to a 105 pin connector to provide access to a 16 bit UTOPIA interface. This header is compatible with the Compact PCI specification. This interface is purely digital, Torridon does not support any UTOPIA PHYs. The pinout of this connector is shown in the following tables (Table 12-9, Table 12-10, Table 12-11, Table 12-12, Table 12-13, and Table 12-14. Table 12-9. 16 Bit UTOPIA Connector - P7 - Row A

CONNECTO SIGNAL DESCRIPTION R PIN#

A1 +3.3V + 3.3 Volts A2 0V 0 Volts A3 0V 0 Volts A4 TXADD4 Transmit Address [4] A5 TXADD2 Transmit Address [2] A6 TXADD0 Transmit Address [0] A7 TXCLAV Transmit Cell Available A8 TXSOC Transmit Start of Cell A9 TXADD14 Transmit Address [14] A10 TXADD12 Transmit Address [12] A11 TXADD10 Transmit Address [10] A12 TXADD8 Transmit Address [8] A13 0V 0 Volts A14 TXADD6 Transmit Address [6] A15 TXADD4 Transmit Address [4] A16 TXADD2 Transmit Address [2] A17 TXADD0 Transmit Address [0] A18 0V 0 Volts A19 +3.3V + 3.3 Volts

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Table 12-10. 16 Bit UTOPIA Connector - P7 - Row B

CONNECTOR PIN# SIGNAL DESCRIPTION

B1 0V 0 Volts B2 +3.3V + 3.3 Volts B3 0V 0 Volts B4 TXADD3 Transmit Address [3] B5 TXADD1 Transmit Address [1] B6 TXPRTY Transmit Data Parity B7 TXENB Transmit Enable B8 TXD15 Transmit Data [15] B9 TXD13 Transmit Data [13] B10 TXD11 Transmit Data [11] B11 TXD9 Transmit Data [9] B12 TCLK Transmit Clock B13 TXD7 Transmit Data [7] B14 TXD5 Transmit Data [5] B15 TXD3 Transmit Data [3] B16 TXD1 Transmit Data [1] B17 0V 0 Volts B18 +3.3V + 3.3 Volts B19 0V 0 Volts

Table 12-11. 16 Bit UTOPIA Connector - P7 - Row C

CONNECTOR PIN# SIGNAL DESCRIPTION

C1 0V 0 Volts C2 0V 0 Volts C3 0V 0 Volts C4 0V 0 Volts C5 0V 0 Volts C6 0V 0 Volts C7 0V 0 Volts C8 0V 0 Volts C9 0V 0 Volts C10 0V 0 Volts

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Table 12-11. 16 Bit UTOPIA Connector - P7 - Row C (continued)

CONNECTOR PIN# SIGNAL DESCRIPTION

C11 0V 0 Volts C12 0V 0 Volts C13 0V 0 Volts C14 0V 0 Volts C15 0V 0 Volts C16 0V 0 Volts C17 0V 0 Volts C18 0V 0 Volts C19 0V 0 Volts

Table 12-12. 16 Bit UTOPIA Connector - P7- Row D

CONNECTOR PIN# SIGNAL DESCRIPTION

D1 0V 0 Volts D2 +3.3V + 3.3 Volts D3 0V 0 Volts D4 RXADD3 Receive Address [3] D5 RXADD1 Receive Address [1] D6 RXPRTY Receive Data Parity D7 RXENB Receive Enable D8 RXD15 Receive Data [15] D9 RXD13 Receive Data [13] D10 RXD11 Receive Data [11] D11 RXD9 Receive Data [9] D12 RCLK Receive Clock D13 RXD7 Receive Data [7] D14 RXD5 Receive Data [5] D15 RXD3 Receive Data [3] D16 RXD1 Receive Data [1] D17 0V 0 Volts D18 +3.3V + 3.3 Volts D19 0V 0 Volts

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Table 12-13. 16 Bit UTOPIA Connector - P7 - Row E

CONNECTOR PIN# SIGNAL DESCRIPTION

E1 +3.3V + 3.3 Volts E2 0V 0 Volts E3 0V 0 Volts E4 RXADD4 Receive Address [4] E5 RXADD2 Receive Address [2] E6 RXADD0 Receive Address [0] E7 RXCLAV Receive Cell Available E8 RXSOC Receive Start of Cell E9 RXADD14 Receive Address [14] E10 RXADD12 Receive Address [12] E11 RXADD10 Receive Address [10] E12 RXADD8 Receive Address [8] E13 0V 0 Volts E14 RXADD6 Receive Address [6] E15 RXADD4 Receive Address [4] E16 RXADD2 Receive Address [2] E17 RXADD0 Receive Address [0] E18 0V 0 Volts E19 +3.3V + 3.3 Volts

Table 12-14. 16 Bit UTOPIA Connector - P7 - Row F

CONNECTOR PIN# SIGNAL DESCRIPTION

F1 0V 0 Volts F2 0V 0 Volts F3 0V 0 Volts F4 0V 0 Volts F5 0V 0 Volts F6 0V 0 Volts F7 0V 0 Volts F8 0V 0 Volts F9 0V 0 Volts F10 0V 0 Volts

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 12-16 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 13 Reset

This section describes the reset sub-section on the Torridon Motherboard.

13.1 Overview All the reset signals on the motherboard are handled by a CPLD. The CPLD monitors the various reset sources and asserts the required outputs.

13.2 Reset Sources There are four main sources of reset on the motherboard. • Power On - After initial power on, the CPLD ensures all peripherals are brought out of reset in a controlled sequence • Push Button - A board reset can be issued at any time by pressing the reset switch. • COP Reset - A debugger, connected to the COP interface of any of the four processors, may cause a reset. • Boot Processor - The boot processor is capable of resetting the other processors on the board

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 13-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Reset

13.3 Reset Scheme The diagram in Figure 13-1 shows the reset scheme utilised on Torridon. A CPLD responsible for controlling the resets on the board. PCI Slot QUADS Via TSI500 Monitor Voltage

Conn. WP3 COP WP2 COP WP1 COP BP COP WP3_COP_TRST_N WP3_COP_SRESET_N WP3_COP_HRESET_N WP2_COP_TRST_N WP2_COP_SRESET_N WP2_COP_HRESET_N WP1_COP_TRST_N WP1_COP_SRESET_N WP1_COP_HRESET_N BP_COP_TRST_N BP_COP_SRESET_N BP_COP_HRESET_N Push to Make Reset toPush Make PORST ADS_HRESET_N PCI_RST_N VIA_RESET_N VIA_RST_REQ_N TSI500_HW_RST_N FPGA WP3_G1_RESET_N WP2_G1_RESET_N WP1_G1_RESET_N BP_G2_RESET_N BP_G1_RESET_N BP_TRST_N BP_SRESET_N BP_HRESET_N WP3_HRESET_REQ_N WP2_RST_CONF_N WP2_HRESET_REQ_N WP2_TRST_N WP2_SRESET_N WP2_HRESET_N WP1_RST_CONF_N WP1_HRESET_REQ_N WP1_TRST_N WP1_SRESET_N WP1_HRESET_N BP_RST_CONF_N BP_HRESET_REQ_N WP3_TRST_N WP3_SRESET_N WP3_HRESET_N WP3_RST_CONF_N PHYs WP1 WP3 WP2 Latch Latch Latch Latch Gbit BP WP3_RESET_N WP2_RESET_N WP1_RESET_N

Figure 13-1. Reset Scheme

Table 13-1 details the reset signals used on Torridon.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 13-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Reset Scheme

Table 13-1. Reset Signals

I/O Signal Description Asserted When? (w.r.t. CPLD)

PORST Power on Reset On system power up Input Push to Make Reset Push to Make Reset By user depressing switch Input BP_COP_HRESET_N Boot Processor COP Hard Reset By COP tools Input/Output By processor following a system reset BP_COP_SRESET_N Boot Processor COP Soft Reset By COP tools Input/Output By processor following a system reset BP_COP_TRST_N Boot Processor COP Test Reset By COP tools Input BP_HRESET_N Boot Processor Hard Reset By CPLD following system reset, COP Output hard reset or Boot Processor hard reset request

BP_SRESET_N Boot Processor Soft Reset By CPLD following system reset, COP soft Output reset BP_TRST_N Boot Processor Test Reset By CPLD following COP test reset Output BP_HRESET_REQ_N Boot Processor Hard Reset Request By Boot Processor Input BP_RST_CONF_N Boot Processor Reset Configuration On power up or any hard reset. Used to Output latch configuration pins

WP1_COP_HRESET_N Work Processor 1 COP Hard Reset By COP tools Input/Output By processor following a system reset WP1_COP_SRESET_N Work Processor 1 COP Soft Reset By COP tools Input/Output By processor following a system reset WP1_COP_TRST_N Work Processor 1 COP Test Reset By COP tools Input WP1_HRESET_N Work Processor 1 Hard Reset By CPLD following system reset, COP Output hard reset or Work Processor 1 hard reset request

WP1_SRESET_N Work Processor 1 Soft Reset By CPLD following system reset, COP soft Output reset WP1_TRST_N Work Processor 1 Test Reset By CPLD following COP test reset Output WP1_HRESET_REQ_N Work Processor 1 Hard Reset Request By Work Processor 1 Input WP1_RST_CONF_N Work Processor 1 Reset Configuration On power up or any hard reset. Used to Output latch configuration pins

WP2_COP_HRESET_N Work Processor 2 COP Hard Reset By COP tools Input/Output By processor following a system reset WP2_COP_SRESET_N Work Processor 2 COP Soft Reset By COP tools Input/Output By processor following a system reset WP2_COP_TRST_N Work Processor 2 COP Test Reset By COP tools Input WP2_HRESET_N Work Processor 2 Hard Reset By CPLD following system reset, COP Output hard reset or Work Processor 2 hard reset request

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Table 13-1. Reset Signals (continued)

I/O Signal Description Asserted When? (w.r.t. CPLD)

WP2_SRESET_N Work Processor 2 Soft Reset By CPLD following system reset, COP soft Output reset

WP2_TRST_N Work Processor 2 Test Reset By CPLD following COP test reset Output WP2_HRESET_REQ_N Work Processor 2 Hard Reset Request By Work Processor 2 Input WP2_RST_CONF_N Work Processor 2 Reset Configuration On power up or any hard reset. Used to Output latch configuration pins WP3_COP_HRESET_N Work Processor 3 COP Hard Reset By COP tools Input/Output By processor following a system reset WP3_COP_SRESET_N Work Processor 3 COP Soft Reset By COP tools Input/Output By processor following a system reset WP3_COP_TRST_N Work Processor 3 COP Test Reset By COP tools Input WP3_HRESET_N Work Processor 3 Hard Reset By CPLD following system reset, COP Output hard reset or Work Processor 3 hard reset request WP3_SRESET_N Work Processor 3 Soft Reset By CPLD following system reset, COP soft Output reset

WP3_TRST_N Work Processor 3 Test Reset By CPLD following COP test reset Output WP3_HRESET_REQ_N Work Processor 3 Hard Reset Request By Work Processor 3 Input WP3_RST_CONF_N Work Processor 3 Reset Configuration On power up or any hard reset. Used to Output latch configuration pins BP_G1_RESET_N Boot Processor’s TSEC PHY1 Reset On power up or any hard reset. Used to Output reset PHY BP_G2_RESET_N Boot Processor’s TSEC PHY2 Reset On power up or any hard reset. Used to Output reset PHY

WP1_G1_RESET_N Work Processor 1’s TSEC PHY1 Reset On power up or any hard reset. Used to Output reset PHY WP2_G1_RESET_N Work Processor 2’s TSEC PHY1 Reset On power up or any hard reset. Used to Output reset PHY WP3_G1_RESET_N Work Processor 3’s TSEC PHY1 Reset On power up or any hard reset. Used to Output reset PHY

TSI500_HW_RST_N TSI500 RapidIO Switch Reset On power on or Boot Processor reset Output VIA_RESET_N Via Southbridge Reset On power on or Boot Processor reset Output VIA_RESET_REQ_N Via Southbridge Reset Request Via requires a reset. (Software controlled) Input PCI_RST_N PCI Bus Reset On power on or Boot Processor reset Output ADS_HRESET_N Reset for QUADS Compatible On power on or Boot Processor reset Output Connections

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 13-4 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Reset Scheme

The following diagram in Figure 13-2 shows how the resets are handled. The majority of the reset signals are simply ANDed together. As they are all active low, this effectively act as an active low ORing function. A delay is added to some of the signals (e.g. the reset of the PHYS) to ensure they power up in a specific order. A delay is also added to the signals used to latch in the configuration pins. (e.g. BP_RST_CONF_N, WP1_RST_CONF_N etc.). The timing of this signal is critical. Refer to the MPC8560 User Manual for mode details. Please note: This diagram illustrates the functionally of the CPLD, not the actual implementation.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 13-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Reset

FPG A BP_COP_TRST_N BP_TRST_N W P1_C O P_TR ST_N W P1_TR ST _N W P2_C O P_TR ST_N W P2_TR ST _N W P3_C O P_TR ST_N W P3_TR ST _N

BP_COP_HRESET_N BP_HRESET_REQ_N BP_HRESET_N

B P_R ST_C O N F_N ˜ B P_G 1_R ESET_N B P_G 2_R ESET_N V IA_RESET_N PCI_RST_N ADS_HRESET_N TSI500_H W _R ST_N BP_COP_SRESET_N BP_SRESET_N

WP1_COP_HRESET_N

W P1_H R ESE T_R E Q _N W P1_HRESET_N WP1_RESET_N W P1_R ST_C O N F_N W P1_G 1_R ESET_N W P1_CO P_SRESET_N ˜ W P1_SRESET_N

W P2_CO P_HRESET_N W P2_HRESET_REQ _N W P2_HRESET_N WP2_RESET_N

W P2_R ST_C O N F_N W P2_G 1_R ESET_N W P2_CO P_SRESET_N ˜ W P2_SRESET_N

W P3_CO P_HRESET_N W P3_HRESET_REQ _N W P3_HRESET_N WP3_RESET_N W P3_R ST_C O N F_N W P3_G 1_R ESET_N W P3_CO P_SRESET_N ˜ W P3_SRESET_N PO RST

Figure 13-2. Resets

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 13-6 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Reset Scheme

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 13-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Reset

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 13-8 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 14 Clocking

This section describes the Clocking sub-section on the Torridon Motherboard.

14.1 Overview All of the clocks used on the Torridon system are generated locally, it does not rely on any external stimulus. There are four distinct clocking environments on the board • System Clocks • RapidIO Clocks • Processor Real Time Clock • GBit Ethernet PHY Clocks • Southbridge Real Time Clock

14.2 System Clocks The system clock is provided by a 33.33MHz crystal oscillator. This clock is distributed, via a zero delay buffer, to produce the required system clocks. (i.e. processor, PCI, Southbridge and logic analyser.)

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 14-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Clocking

The diagram in Figure 14-1 shows the clocking mechanism.

MPC8560 Boot Processor

MPC8560 Work Processor 1

MPC8560 Work Processor 2 MPC9448 33.33MHz Clock Oscillator Buffer MPC8560 Work Processor 3

VIA ‘686 Southbridge

PCI 64 Bit PCI Slot

Logic Analyser Mictor Connector

Figure 14-1. System Clocks

The diagram in Figure 14-2 shows the schematics for the system clock circuitry.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE System Clocks

Figure 14-2. System Clocks - Schematics

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The following should be noted about the circuitry. • The oscillator is socketed to allow different frequencies to be used (if required) • Series resistors (27 ohm) are inserted on all the clock lines to avoid any over/under shoot • The CLK_SEL input on the MPC9448 fan out buffer is pulled high to select the TTL clock input. (as opposed to the differential input) • Adequate de coupling is added to the 3.3V power rail

14.3 RapidIO Clocks

14.3.1 Overview The RapidIO interface has independent receive and transmit clocks. These are referred to as inbound and outbound clocks. A RapidIO endpoint receives the inbound clock as a LVDS pair from an adjacent RapidIO device through the RapidIO interface, then generates an internal clock using its own clock synchronizer. The outbound (transmit) clock is generated from an internal PLL clock generator which provides the transmit clock by multiplexing the input clock (LVTTL).

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-4 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE RapidIO Clocks

The diagram in Figure 14-3 shows the RapidIO clocking scheme.

RapidIO Device A RapidIO Device B

Clock Transmit Clock –Device A Clock Source PLL Synchroniser

Receive Clock –Device B Internal Logic Internal Logic Receive Clock –Device A

Clock Transmit Clock –Device B Clock PLL Synchroniser Source

Figure 14-3. RapidIO Clocking

A RapidIO system can be designed to operate either asynchronously or synchronously to each RapidIO device. For asynchronous operation, each RapidIO device has its own separate outbound clock input. For synchronous operation, each RapidIO device shares a common clock source.

14.3.2 Torridon’s RapidIO Sub-System As shown in Figure 14-4, Torridon’s RapidIO sub-system consists of four PowerQUICCIIIs connected to a four port RapidIO switch. All the connections to the respective ports are identical apart from the connection between the boot processor and Port 0 of the TSI500. Although this particular link also incorporates the connections to allow the bus to be probed by a logic analyser, this does not influence the clocking scheme.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 14-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Clocking

Work Key: Processor Tektronix Test Probe

Work RapidIO Work Processor Switch Processor

Boot Processor

Figure 14-4. RapidIO Sub-System

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-6 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE RapidIO Clocks

14.3.3 Processor Clocks The processor can generate the source of its RapidIO transmit clock from one of three separate sources. These sources are • The RapidIO receive Clock • The internal CCB clock • The RapidIO_TX_CLK+/RapidIO_TX_CLK- inputs The diagram in Figure 14-5 shows the different clock options available. On Torridon, these options can be chosen using DIP switches, which set the appropriate configuration pins (LGPL0, LGPL1) on the PowerQUICCIII.

RIO_RX_CLK+

RIO_RX_CLK-

RIO_TX_CLK+ CCB RIO_TX_CLK-

RIO_TX_CLK+ Clock Source RIO_TX_CLK-

Configuration Pins Figure 14-5. RapidIO Clock Options

14.3.4 TSI500 Clocks The TSI500 switch may be clocked from one of two sources. • A “slow speed” TTL clock • A high speed differential clock

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 14-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Clocking

As with the processor, the selection of the clock source is made via configurations pins as shown in Figure 14-6.

P0_CLK_SEL[1:0]

P0_TX_CLK+ P0_TX_CLK-

P1_CLK_SEL[1:0]

P1_TX_CLK+ P1_TX_CLK-

P2_CLK_SEL[1:0]

P2_TX_CLK+ P2_TX_CLK-

P3_CLK_SEL[1:0]

LS0_CLK 1GHz P3_TX_CLK+ 100M Hz 500M Hz P3_TX_CLK-

HSPLL

HSPLL_RANGE_SEL[1:0] /5 HSPLL_BYPASS_CLK

LS1_CLK

CORE_CLK_SEL[1:0] REG_CLK

Figure 14-6. TSI500 RapidIO Clock Options

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-8 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE RapidIO Clocks

The selection of clock is made on a per port basis; each port being individually configurable. The “slow” speed clock is provided by two separate clock signals, LS0_CLK and LS1_CLK. Although these are running at the same frequency, they must be provided to the TSI500 out of sync. This is achieved by a “RoboClock” device which skews the two clocks by a fixed amount, again, selectable on Torridon via jumpers/switches. The high speed clock pair is generated from the same circuitry as the processors RapidIO_TX_CLK+/RapidIO_TX_CLK- clocks.

14.3.5 Clock Distribution on Torridon The RapidIO sub-system in Torridon can operate either synchronously or asynchronously. For synchronous operation, each RapidIO device shares a common clock source. The clock source is generated by a 16MHz oscillator. This clock source is fed into a clock synthesizer (ICS8442) where the frequency is multiplied by a PLL. The multiplication factor is set via switches. This multiplied clock frequency is distributed around the board via a clock buffer (ICS8516). Asynchronous operation is very similar. The four processors operate from a common clock as described above but the switch operates from a separate source.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 14-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Clocking

The diagram in Figure 14-7 shows the RapidIO clock distribution around Torridon.

Work Processor

2TX_CLK_IN+ TX _CLK_IN+ 2TX _CLK _IN- TX _C LK _IN-

3TX_CLK_IN+ TX _CLK_IN+ 3TX_CLK_IN- TX _C LK _IN- 500_TX _C LK _IN+ Work TX _CLK_IN+ 500_TX _C LK _IN- Processor TX _C LK _IN- R apidIO Work S w itch P rocessor

1TX _CLK _IN+ TX _C LK _IN+ LS0_CLK “RoboClock” 1TX _C LK _IN- TX_CLK_IN- LS1_CLK

25 M H z 0TX_CLK_IN+ TX _CLK_IN+ 0TX _CLK _IN- TX _C LK _IN-

B oot Processor

500_TX _CLK _IN+

500_TX _C LK _IN- 0TX_CLK_IN+

0TX_CLK_IN- 25 M H z M u ltip lie r Fan O ut 1TX_CLK_IN+ Buffer 1TX_CLK_IN- 2TX_CLK_IN+ 2TX_CLK_IN-

3TX_CLK_IN+ 3TX_CLK_IN-

Figure 14-7. RapidIO Clock Distribution on Torridon

The schematics in Figure 14-8 show how this is implemented.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-10 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE RapidIO Clocks

Figure 14-8. High Speed Clock Generation

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The following should be noted about the circuitry. • The base clock frequency is provided by a 25MHz crystal • Switches select the multiplication factor • A separate push to make switch allows the frequency multiplication to be changed on the fly without the need to power cycle the system • Multiple, exact copies of the clock pairs are generated via a fan out buffer • In line resistors reduce any over/under shoot on the clock lines. • Adequate de coupling is required

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-12 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE RapidIO Clocks

Figure 14-9. Slow Speed Clock Generation

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The following should be noted about the circuitry. • The configurations pins which adjust the frequency multiplication and skew are set via jumpers (not shown for simplicity) • In line resistors reduce any over/under shoot on the clock lines. • Adequate de coupling is required

14.4 Processor Real Time Clock As well as the main clock, each processor uses a separate real time clock input. This clock has to be separate from the system clock and must be driven independently of the system clock. On Torridon, a 16MHz crystal produces this clock input. As shown in Figure 14-10, a fan out buffer is used to distribute this clock signal so it may be driven to all four processors.

MPC8560 Boot Processor

MPC8560 Work Processor 1 16MHz MPC905 Crystal Clock Buffer MPC8560 Work Processor 2

MPC8560 Work Processor 3

Figure 14-10. Processor Real Time Clocks

The diagram in Figure 14-11 shows the schematics for the real time clock circuitry

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-14 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Processor Real Time Clock

Figure 14-11. Processor Real Time Clocks - Schematics

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The following should be noted about the circuitry. • The capacitors (C413, C416) have been chosen to match the characteristics of the crystal • Series resistors (27 ohm) are inserted on all the clock lines to avoid any over shoot • As only four clock signals are required, a smaller part (MPC905) fan out buffer is used • Adequate de coupling is required to the 3.3V power rail

14.5 GBit Ethernet Clocks The MPC8560’s Triple Speed Ethernet Controller (TSEC) requires an external clock to provide the stimulus for its transmit operation. A 125MHz clock input is require to operate the TSEC block. As shown in Figure 14-12, both of the TSEC blocks in an MPC8560 operate from the same clock input so only a single input is required. On Torridon, Marvel 88E1011 devices provide the on-board GBit PHYs. The Marvel device provides the 125MHz clock to the MPC8560 from a 25MHz clock input.

MPC8560

88E1011

TSEC1 125MHz x5 25MHz

88E1011

125MHz TSEC2 x5 25MHz

Figure 14-12. GBit Ethernet Clocks

Note: Although both PHYs produce a 125MHz clock, only one is required to drive both PHYs. The other is a no connect on the board.

14.6 Southbridge Real Time Clock The Via Southbridge chip provides a real time clock. This clock is required by some operating systems, e.g. Linux, to monitor the absolute time. This is used for various operations such as time stamping files, monitoring file backups etc.

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On Torridon, this clock is provided by a dedicated 32kHz crystal. To enable the real time clock to operate when the main power supply is not present, a battery may be fitted to the system. A “standard” 3.3 V battery (similar to those used in personal computers) may be plugged into a 4 pin header. (HD33 in the schematics below). A 3 pin jumper, JP19, is used to select the source of power. When the battery is fitted, a jumper between pin 2 and 3 on JP19 will select the battery as the power source for the real time clock. To operate the real time clock in the event of the battery not being present, a jumper should be placed across pins 1 and 2 on JP19. This will route the boards main 3.3V power supply to the real time clock. Although this will allow the real time clock to function, it will only run when the main power is applied to the system. Hence, if this mode of operation is used, the real time clock will not correctly indicate the actual time.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 14-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Clocking

Figure 14-13. Real Time Clock Schematics

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 14-18 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 15 Voltage Regulation

This section describes the Voltage Regulation sub-section on the Torridon Motherboard.

15.1 Overview The Torridon system requires a number of different voltages to power the various components on board. In fact, the board uses seventeen different power supplies. The majority of these voltages are generated on board.

15.2 Power Available The board receives its power from one of two sources. • The backplane • An ATX power supply. The backplane will be provided by the end customer, so the supplied current will be variable depending on the specific implementation. Table 15-1 shows the current supplied from an ATX power supply. Table 15-1. Power Supplied from an ATX Power Supply

Voltage Current (Volts) (Amps)

+3.3 V 28 A +5 V 30 A +12 V 15 A +5VSB 2 A -12 V 0.8 A - 5 V 0.3 A

NB: Numbers given for a 300W, ATX 12V supply.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 15-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Voltage Regulation

15.3 Power Required Table 15-2 shows the main components on the board and their respective power requirements. Table 15-2. Power Required

I/O Core Total no. On Power per Device Device Voltage Voltage POwer Board (Watts) (Volts) (Volts) (Watts)

MPC8560 4 3.3 V 1.2 V 8 W 32 W RapidIO Switch 1 3.3 V 3.3 V 1.5 W 1.5 W DDR SDRAM 4 2.5 V 2.5 V 2.5 W 10 W Clock Buffer 1 3.3 V 3.3 V 2.6 W 2.6 W GBit PHY 5 3.3 V 3.3 V 1.2 W 6 W Total 52.1 W

15.4 Power Distribution Torridon requires four voltages to operate correctly. These are as follows • +12V •+5V • +3.3V •+5VSB All the other voltages are generated from these stimulus. The diagram in Figure 15-1 shows the power distribution around the board.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 15-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Power Distribution

+5V +5V +5V From Backplane / ATX Power Supply +12V +5V BP/ATX +3.3V BP/ATX +5VSB 5V to 5V to 5V to 1.2V 2.5V 1.3V 5V to 3.3V +3.3VCPLD VREF (1.2V @ 2A) (2.5V @ 2A) VddIO Vdd (1.3V @ 2A) Isolator Isolator CPLD 3.3V +5V +3.3V VREF VddIO Vdd TSI500 +12V +12V 12V to 12V to 2.5V 1.2V +5V +5V +3.3V 5V to 5V to 2.5V 1.5V Conversion Filter Filter Filter 2.5V to 1.25V OVdd (3.3V @ (3.3V 10A) OVdd AVdd3 (1.05 – 1.825V @ 0.4A) 1.825V@ AVdd3 (1.05 – 0.4A) 1.825V@ AVdd2 (1.05 – 0.4A) 1.825V@ AVdd1 (1.05 – Logic Other Vdd (1.05 – 1.825V @ 40A) @ 1.825V Vdd (1.05 – GVdd (2.5V @ (2.5V 12A) GVdd @ (2.5V 8A) GVdd Sense Vss Vdd Sense rf(1.25V @ 0.5A) Vref Vd (2.5V @ 1A) AVddl (3.3V @ 3A) Vddo Vtt (1.25V @ (1.25V 6A) Vtt DVddl (1.5V @ (1.5V 1A) DVddl Vtt Sense DDR DIMM Ethernet PHY t Sense Vtt Vref GVdd GVdd Vdd AVdd3 AVdd2 AVdd1 MPC8560 OVdd DVddl AVddl Vddo s Sense Vss Vdd Sense Vtt Terminati Islands o

Figure 15-1. Power Distribution

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The board must be supplied by four separate power supplies; +3.3V, +5V, +12V and +5VSB. All the other voltages are produced on board. The +5VSB is used to power the CPLD which is responsible for system reset and power up sequencing. Two separate isolators are used to turn the 5V and 3.3V onto the board. These switches allow the voltages to be turned on in a specific sequence. The sequence is detailed in Section 15.6, “Power Sequencing”.

15.5 Voltage Generation The diagram in Figure 15-1 above shows the power distribution around the system. The areas to be discussed are • CPLD Power • 5V/3.3V Switching • MPC8560 • DDR SDRAM • GBit Ethernet • TSI500 RapidIO Switch Each of these will be discussed in detail.

15.5.1 CPLD Power The CPLD is responsible for controlling the resets and sequencing the power supply. This means that the CPLD must be powered on first. The 3.3V power supply for the CPLD is generated from the 5V Stand By (+5VSB). This voltage is present even before the ATX power supply is turned on with its “Power ON” signal. The CPLD is responsible for turning on the ATX power supply so it can not be powered from the “normal” 5V or 3.3V supply as they will not be present initially. The 3.3V power is generated from the +5VSB using a MAXIM MAX1831 voltage regulator. See Figure 15-2.

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Figure 15-2. CPLD Power - Schematics

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The following should be noted about the schematics in Figure 15-2 above: • The stand by voltage (+5VSB) provides the input power • Connecting the FBSEL pin directly to the REF pins sets the voltage to 3.3V. No resistor divider network is required.

15.5.2 5V/3.3V Switching The 5V and 3.3V power supplies, which come directly from the ATX (or the backplane), are turned on via FETs. This allows the various voltages on the board to be turned on in a specific sequence. See Figure 15-3.

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Figure 15-3. 3.3V/5V Isolator - Schematics

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The following should be noted about the schematics in Figure 15-3 above: The sense resistors are not used. (This simplifies layout)

15.5.3 MPC8560

15.5.3.1 MPC8560 Power Requirements Table 15-3 details the power requirements for one of the processors. Table 15-3. MPC8560 Power Requirements

Est. Max. Characteristic Power Source Voltage Current Current

Core Supply Voltage VDD 0.8V - 1.5V 10A 20A

PLL Supply Voltage AVDD[1:3] 0.8V - 1.5V 0.1A 0.1A

DDR DRAM I/O Voltage GVDD 2.5V XA 2A

Three-speed Ethernet I/O, LVDD 3.3V xA 1A MII Management Voltage

PCI/PCI-X, local bus, OVDD 3.3V XA 1.5V RapidIO, 10/100 Ethernet, DUART, system control and power management, I2C, and JTAG I/O voltage

15.5.3.2 Core & PLL Voltage The MPC8560’s core and PLL circuitry requires a voltage of between 0.8 and 1.5V at a maximum current of 20.1A. Hence for the four processors, a maximum current of 80.4A should be available. This power supply is generated from the 12V power rail using a POL (Point of Load) power module from Artesyn, the NXI100, shown in Figure 15-4.

Figure 15-4. NXI100 Power Module

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The NXI100 is a point of load DC/DC convertor capable of delivering up to 81A. The module complies to the VRM9.0 specification. The output voltage from the NXI100 is set using five configuration pins, VID0–VID4. The NXI100 uses an internal 5-bit DAC as a feedback-resistor voltage divider. The output voltage can be digitally set in 25mV increments from 1.1V to 1.85V using the VID0–VID4 inputs. The schematics in Figure 15-5 and Figure 15-6 show how the NXI100 module is used on Torridon.

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Figure 15-5. Vdd Power - Schematics

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Figure 15-6. Vdd Power - Feedback- Schematics

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The following should be noted about the schematics in Figure 15-5 and Figure 15-6 above. • The VID settings are configured using DIP switches. This allows the voltages to be easily changed. For example, to allow for a subsequent, low power version of the processor • Low ESR (Equivalent Series Resistance) capacitors are used to de couple the output (Vdd) voltage • The NXI100 uses a feedback network to monitor the voltage at point of load and, if necessary, adjust to allow for any voltage drop. (For example, if the point of load was physically a long distance away). Zero ohm resistors are used to allow the point of testing to be changed.

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As well as the core voltage, the NXI100 also provides the voltage for the processors PLL circuitry. The Vdd power is fed through an RC network to provide the PLL voltage. See Figure 15-7.

Figure 15-7. PLL Power - Schematics

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15.5.3.3 DDR DRAM I/O Voltage The MPC8560’s DDR DRAM I/O circuitry requires a voltage of 2.5V at a maximum current of 2A. This power supply is generated from the 12V power rail using an Artesyn module, DDR12, shown in Figure 15-8.

Figure 15-8. DDR12 Module

The DDR12 is also a point of load DC/DC convertor capable of producing 2.5V at 25A and 1.25V at 8A.

Note: Although the module is capable of generating the Vdd voltage (2.5 V) and the Vtt voltage (1.25V); on Torridon the DDR12 module is only used to supply the Vdd voltage (2.5V). The termination voltage (VTT) is generated locally for each individual VTT island. This method simplified the board layout.

Unlike the NXI100 module which used voltage ID pins (VIDs) to specify the output voltage, the DDR12 uses a simple resistor divider network to set the required output voltage. This voltage can be adjusted from 2.25V to 2.75V by changing a resistor value from open circuit to 41.7 ohms. The schematics in Figure 15-9 show how the 2.5V is generated on Torridon.

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Figure 15-9. 2.5V Voltage Generation

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The following should be noted about the schematics in Figure 15-9 above: • The output voltage is set to 2.5V using R1376. • Low ESR (Equivalent Series Resistance) capacitors are used to de couple the output (Vdd) voltage • Power On/Power Good signals are available for control/monitoring by the power on state machine.

15.5.3.4 I/O Voltage The MPC8560’s I/O circuitry requires a voltage of 3.3V at a maximum current of 2.5A. This power supply is taken directly from the 3.3V power rail provided.

15.5.4 DDR SDRAM As well as 2.5V, the DDR SDRAM requires a termination voltage of 1.25V. Although it is possible to produce this voltage rail from the DDR12 module, the 1.25V required for each DIMM is generated locally. This method simplifies signal routing and layout.

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A National Semiconductor LP2995 device is used to generate a 1.25V signal from the 2.5 V signal. The schematics are shown in Figure 15-10.

Figure 15-10. 1.25V Signal Generation

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The following should be noted about the schematics in Figure 15-10 above: • To distinguish the four separate 1.25V islands on Torridon, they are labeled VTT0, VTT1, VTT2 and VTT3. • A sense signal, VTTx_Sense, is a tap taken from the midpoint of the VTT island. This tracks the voltage and adjusts, if required.

15.5.5 GBit Ethernet In addition to a 3.3V supply, (which is taken from the 3.3V ATX power rail/backplane), the Ethernet PHYS also require 2.5V and 1.5V. Both of these voltage are generated using two separate MAXIM ‘1831 devices. The schematics are shown in Figure 15-11 and Figure 15-12.

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Figure 15-11. GBit Ethernet - 2.5V Generation

The following should be noted about the schematics in Figure 15-11 above: The output voltage is fixed at 2.5V by tying the FBSEL pin to VCC (+5V)

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Figure 15-12. GBit Ethernet - 1.5V Generation

The following should be noted about the schematics in Figure 15-12 above: The output voltage is fixed at 1.5V by leaving the FBSEL pin unconnected.

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15.5.6 TSI500 In addition to a 3.3V supply, (which is taken from the 3.3V ATX power rail), the TSI500 also requires 2.5V, 1.3V and 1.2V. These voltages are generated using three separate MAXIM ‘1831 devices. The schematics are shown in Figure 15-13, Figure 15-14, and Figure 15-15.

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Figure 15-13. TSI500 - 2.5V Generation

The following should be noted about the schematics in Figure 15-13 above: The output voltage is fixed at 2.5V by tying the FBSEL pin to VCC (+5V)

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Figure 15-14. TSI500 - 1.3V Generation

The following should be noted about the schematics in Figure 15-14 above: • The output voltage is fixed at 1.3V using a resistor divider network. (R1372 & R285) • FBSEL is tied to ground

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Figure 15-15. TSI500 - 1.2V Generation

The following should be noted about the schematics in Figure 15-15 above: • The output voltage is fixed at 1.2V using a resistor divider network. (R682 & R683) • FBSEL is tied to ground

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15.6 Power Sequencing To ensure correct operation, it is imperative that the board is powered up in a controlled manner. This is achieved by the use of a simple state machine implemented in a CPLD. A CPLD (EMP3128) is responsible for the power up sequence of the board. The diagram in Figure 15-16 shows the sequence of events.

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From ATX / Backplane +5VSB Power on Power +5VSB +3.3V +5V 1 1 PWR_OK PS_ON 5 5 5 4 Reset 5V_Power_Good 6 +5V 5V_Power_On Reset 8 7 2 Control Power PLD On On +5V Core_Power_Good Core_Power_On IO_LV_Power_On 3.3V_Power_On DDR_Power_On 3.3V_Power_Good +3.3V DDR_Power_Good +5V 3 9 10 0V 14 16 11 11 12 15 15 12 (MAX1831s) (MAX1831s) 12V to 1.2V to 12V 12V to 2.5V to 12V /1.5V/1.2V 5V to 2.5V (NXI100) (DDR12) Regulator Regulator Regulator +3.3V +2.5V 13 +1.2V_tsi500 +2.5V_tsi500 +1.5V_GEther +2.5V_GEther Vdd 2.5V to 1.25V to 2.5V (LP2995) (LP2995) Regulator Vtt VRef +1.25V

Figure 15-16. Power-Up Sequence

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The power up sequence for Torridon is as follows: 1. The ATX/Backplane Power Supply supplies +5VSB (+5V Stand By) immediately after power is applied. PS_Ready LED lights 2. This voltage (+5VSB) is used by a DS1818 voltage monitor chip to generate a system power on reset signal, (PORST), to the CPLD only. At this point, the sequence stops, awaiting intervention from the user. 3. Operator pushes the on/off switch to turn the system on. 4. A Power Supply On (PS_ON) signal is sent back to the power supply. 5. The power supply generates all the required voltages (i.e. 3.3V, 5V and 12V) 6. The power supply sends a Power OK (PWR_OK) signal to Torridon to indicate that the power is on. 7. Torridon turns on the 5V power rail via the 5V_Power_On Signal. 8. A voltage monitoring device (MAX5918) checks the 5V rail and sends a 5V_Power_Good signal to the power on state machine 9. Torridon turns on the core power rail via the Core_Power_On Signal 10. A voltage monitor (NXI100) checks the Vdd rail and sends a Core_Power_Good signal to the power on state machine 11. Torridon turns on the +2.5V power rail (for DDR) via the DDR_Power_On Signal 12. A voltage monitor (DDR12) checks the +2.5V rail and sends a DDR_Power_Good signal to the power on state machine 13. The +2.5V power rail is regulated via four National Semiconductor ('2995) devices (one per processor) to generate the other required voltages for DDR (+1.25V, VRef, Vtt) 14. Torridon turns on the 3.3V power rail via the 3.3V_Power_On Signal 15. A voltage monitoring device (MAX5918) checks the 3.3V rail and sends a 3.3V_Power_Good signal to the power on state machine 16. Torridon turns on the lower voltages to the peripherals (2.5V, 1.5V, 1.2V) via the IO_LV_Power_On Signal

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MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 15-28 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Chapter 16 Processor Sockets

This section describes the processor socket used on the Torridon Motherboard.

16.1 Overview During the development of the Torridon system, the PowerQUICCIII silicon was very new and fresh out of fabrication. In such an situation, it was deemed necessary to be able to easily change the processors on the motherboard. This prompted the decision to use sockets for the processors.

16.2 The Need For Sockets Typically during the initial release of new silicon, different behaviors can been seen over the range of parts available. These differences in behavior can be due to numerous reasons such as differences in process, test screening or device errata. Whatever the reason, it is advantageous to be able to easily replace processors on the motherboard. Typically, processors would be removed simply by de soldering. However, as well as being time consuming, this adds undue stress to the board as it is baked to remove moisture and then locally heated to attach the new processor. As well as allowing for faulty processors to be replaced, a socket also allows for new revisions of the processor to be tested.

16.3 Socket Criteria Numerous solutions exist in the market place for processor sockets. When choosing a socket, the following criteria were considered. • Cost: With each motherboard requiring up to 4 sockets, cost was particularly sensitive. • Size: Both in terms of height and width. An excessively tall socket could potentially foul on an adjacent board when Torridon is plugged into a rack environment. A wide socket would use up valuable real estate limiting the number of components that could be placed on the board. • Board Attachment: Some sockets require special modifications to the board. For example additional fixing holes may be required. The addition of fixing holes will adversely impact the available board space for other components both on top and bottom of the board. Some sockets may require a “rear bracket” for board attachment and rigidity. This has the potential problem of fouling on adjacent boards in a rack environment or against the metal box in a chassis environment.

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• Socket Foot Print: Ideally, the same foot print should be used for both the socket and the processor. Typically sockets are only used in the first few boards. Once the silicon is deemed stable, the sockets are no longer necessary and the processors can be mounted directly on the motherboard. This means that during assembly, either a socket or a processor may be populated. Alternatively, a board may be fitted with a socket during initial debug. This socket may then be removed, and potentially re-used, and a processor fitted in its place. Some sockets use a different foot print than the processor itself. Using such a socket will obviously not allow processors and sockets to be swapped in/out of boards. Using such a socket will dictate that two versions of the mother board be manufactured, a version to take sockets and a version to take processors. • Heat Sink Attachment: Depending on the environment (e.g. ambient temperature, air flow etc.), it may be necessary to add a heat sink to the processor. Ideally the heat sink used with the socket should also be usable on the “bare processor”. This means only one type of heat sink is required. Again, this allows flexibility where, at the assembly stage, a board may be populated with or without sockets.

16.4 The Choice of a Socket Based on the criteria detailed above, a socket solution from Emulation Technology was chosen. The socket had the following advantages. • Low Cost (Approximately $300 each) • Reliability: This socket technology has been used by many customers in numerous systems operating in various environments. • Foot Print: The socket uses the same foot print as the silicon. This would allow a socketed and a non-socketed processor to be used on the same motherboard. • Size: The socket is only 2mm wider and 2mm deeper than the processor itself. • Height: The socket only adds 3mm to the overall height of the processor. • Board Attachment: No board changes (e.g. fitting holes) are required to accommodate the socket • Heat Sink: The socket does not impair the top or sides of the processor meaning the same heat sink may be used on a socketed and non-socketed processor.

16.5 Socket Mechanics The socket solution is made up of two component parts. 1. The BPE (Base Package Emulator) is soldered to the motherboard. The BPE provides a 783 female connector into which a male socket can be inserted.

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2. The processor itself is soldered onto an FPA (Flat Pin Array).The FPA provides the processor with pins which mate with the BPE. Effectively the FPA turns the processor from a BGA (Ball Grid Array) package to a PGA (Pin Grid Array) package The diagram in Figure 16-1 shows how the component parts fit together.

PowerQUICCIII Soldered

FPA-783-3BG028-NS

“Push to fit” BPE-0783-3BG028-BL

Soldered

Torridon Motherboard 783 Pads Figure 16-1. Socket Mechanics

The foot print of the BPE is identical to that of the PowerQUICCIII processor. This allows the BPE and the processor to be easily interchanged.

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The diagram in Figure 16-2 illustrates how the processor and the socket may be inter-changed.

PowerQUICCIII Soldered

FPA-783-3BG028-NS

“Push to fit” BPE-0783-3BG028-BL PowerQUICCIII

Soldered

Torridon Motherboard 783 Pads Figure 16-2. Processor - Socket Swapping

16.6 The Base Package Emulator (BPE) The Base Package Emulator (BPE) is soldered directly onto the motherboard. 783 spheres present on the bottom of the BPE are used to attach it to the motherboard. The socket provides 783 female sockets on top. They accept the pins on the bottom of the FPA (Flat Pin Array) adapter. See Figure 16-3.

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Figure 16-3. The BPE

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16.7 The Flat Pin Array (FPA) The Flat Pin Array (FPA) adapter allows the processor to mate with the BPE. 783 pads are present on top of the FPA. The PowerQUICCIII is soldered directly on to these pads. The bottom of the adapter provides pins which fit directly into the BPE. See Figure 16-4.

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Figure 16-4. The FPA

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16.8 Alternative Parts Although Torridon used the parts from Emulation Technology, similar socket are available from other companies. Table 16-1 provides alternative sockets that may be used. Table 16-1. Alternative Socket Vendors

Component Part Vendor Part Number

BPE Emulation BPE-0783-3BG028-BL Technology BPE Advanced FHA783-715G Interconnect FPA Emulation FPA-783-3BG028-NS Technology FPA Advanced FHS783-715-GG Interconnect

16.9 Sockets on Torridon The following pictures show the sockets on the Torridon motherboard: Table 16-5, Table 16-6, Table 16-7, Table 16-8, and Table 16-9.

Figure 16-5. BPE

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Figure 16-6. PowerQUICCIII in FPA

Figure 16-7. PowerQUICCIII in FPA - Side View

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Figure 16-8. PowerQUICCIII + FPA + BPE

Figure 16-9. Heat Sink Attached

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This section describes the Heat Sinks used on the Torridon Motherboard.

17.1 Overview The processors on Torridon are each fitted with a heat sink. The choice of size and type of heat sink is dependant on the environment in which the board is situated. Factors such as processor speed, ambient temperature and air flow all dictate the specific characteristics of the heat sink used.

17.2 Processor Thermal Characteristics Table 17-1 details the package thermal characteristics for the MPC8560 processor. Table 17-1. Package Thermal Characteristics

Characteristic Symbol Value Unit Notes

θ 1,2 Junction-to-ambient resistance (Natural convection on 1S board) JA 30 °C/W θ 1,3 Junction-to-ambient resistance (Natural convection on 2S2P board) JMA 19 °C/W θ 1,3 Junction-to-ambient resistance (Forced airflow (200 ft/min) on 1S board) JMA 24 °C/W θ 1,3 Junction-to-ambient resistance (Forced airflow (200 ft/min) on 2S2P JMA 16 °C/W board) θ 4 Die junction-to-board thermal resistance JB 10 °C/W θ 5 Junction-to-case thermal resistance JC 0.3 °C/W 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface without thermal grease.

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17.3 Thermal Management Information Proper thermal control design is primarily dependent upon the system-level design i.e. the heat sink, airflow and thermal interface material. The recommended attachment method to the heat sink is illustrated in Figure 17-1. The heat sink should be attached to the printed circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force.

FC-PBGA Package Heat Sink

Heat Sink Clip

Adhesive or Thermal Interface Material

Lid Die

Printed-Circuit Board

Figure 17-1. Heat Sink Attachment

17.4 Adhesives and Thermal Interface Materials A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, the diagram in Figure 17-2 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint.

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Heat sinks are attached to the package by means of a spring clip to holes in the PCB. Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure.

Silicone Sheet (0.006 inch) 2 Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease

1.5 /W) 2

1

0.5 Specific Thermal (KinSpecific Resistance

0 0 1020304050607080 Contact Pressure (psi)

Figure 17-2. Thermal Performance of Interface Material

17.5 Heat Sink Selection The choice of the heat sink is dependant on a number of factors such as the space available, the air flow across the heat sink and the availability of a fan. This will be ultimately be determined by the mechanical constraints of a system. For preliminary heat sink sizing, the die junction temperature can be expressed as θ θ θ Tj = Ti + Tr + ( jc + int + sa) x Pd

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Where:

Tj is the die-junction temperature Ti is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet θ jc is the junction-to-case thermal resistance θ int is the adhesive or interface material thermal resistance θ sa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device

During operation the die-junction temperatures (Tj) should be maintained within the specified range of 0 - 105°C. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of some thermal interface material θ θ ( int) may be about 1°C/W. Assuming a Ti of 30°C, a Tr of 5°C, a FC-PBGA package jc = 0.3, and a power consumption (Pd) of 7.0 W, the following expression for Tj is obtained: θ Die-junction temperature: Tj = 30°C + 5°C + (0.3°C/W + 1.0°C/W + sa) * 7.0 W θ The heat sink-to-ambient thermal resistance ( sa) versus airflow velocity for a Aavid Thermalloy heat sink 10-THMA-01 is shown in the diagram in Figure 17-3.

Figure 17-3. Aavid Thermalloy 10-THMA-01 Thermal Characteristics

Assuming an air velocity of 1m/s.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 17-4 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Fans

1m/s is equal to 200 LFM. (Linear Feet per minute) θ From the graph above, this will equate to an effective sa of about 4°C/W, thus

Tj = 30°C + 5°C + (0.3°C/W +1.0°C/W + 4°C/W) x 7.0 W, resulting in a die-junction temperature of approximately 72.1°C which is well within the maximum operating temperature of the component. The diagram in Figure 17-4 shows the physical dimensions of the Aavid Thermalloy 10-THMA-01.

Figure 17-4. Aavid Thermalloy 10-THMA-01 Dimensions

17.6 Fans To aid in thermal dissipation, each heat sink is fitted with a fan. Running off a 12V supply, the 25mm x 25mm x 10mm fan is capable of providing an air flow of 1m/s.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor 17-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Heat Sinks

17.7 Heat Sinks On Torridon The photo in Figure 17-5 shows a heat sink on Torridon fitted with a fan.

Figure 17-5. Heat Sink on Torridon

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 17-6 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Appendix A Schematics

The schematics for Torridon are shown on the following pages.

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics A B C D SENSE_VSS SENSE_VDD DDR_Power_On 3.3V_Power_On IO_LV_Power_On 5V_Power_On Core_Power_On +3.3V_BP +5V_BP PWR_OK PS_ON WP3_RXD WP3_TXD WP2_RXD WP2_TXD WP1_RXD WP1_TXD VIA_RESET_REQ_N VIA_RESET_N VIA_ON VIA_CLK LA_CLK PCI_CLK WP3_RE WP2_RE WP1_RE BP_RST_CONF_N PCI_RST_N SYS_RESET_N BP_HRESET_REQ_N BP_COP_T BP_T BP_COP_SRESET_N BP_COP_HRESET_N BP_HRESET_N BP_SRESET_N PCI_INTA_N BP_RTC_CLK RIO0_TXCLK_IN_N RIO0_TXCL SHUTDOWN SYSTEM_RESET_N +1.5V +2.5V +3.3V Vdd +2.5V +3.3V +5V +12V -12V VIA_INT BP_SYS_CLK CGND DGND ID[3:0] BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RST_N GEther GEther SET_N SET_N SET_N RST_N K_IN Power Supply Page 68 5 5 SENSE_VSS SENSE_VDD DDR_Power_On 3.3V_Power_On IO_LV_Power_On 5V_Power_On Core_Power_On PWR_OK PS_ON +3.3V_BP +5V_BP WP - Debug Ports WP Page 72 WP3_RXD WP3_TXD WP2_RXD WP2_TXD WP1_RXD WP1_TXD Boot Processor Page 4 VIA_RESET_REQ_N VIA_RESET_N VIA_ON VIA_CLK VIA_INT LA_CLK PCI_CLK WP3_RESET_N WP2_RESET_N WP1_RESET_N BP_RST_CONF_N PCI_RST_N SYS_RESET_N BP_HRESET_REQ_N BP_COP_TRST_N BP_TRST_N BP_COP_SRESET_N BP_COP_HRESET_N BP_HRESET_N BP_SRESET_N PCI_INTA_N BP_RTC_CLK BP_SYS_CLK RIO0_TXCLK_IN_N RIO0_TXCLK_IN SHUTDOWN SYSTEM_RESET_N CGND DGND +1.5VGEther +2.5VGEther +3.3V Vdd +2.5V +3.3V +5V +12V -12V ID[3:0] BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N Core_Power_Good DDR_Power_Good 3.3V_Power_Good 5V_Power_Good +1.5VGEther +2.5VGEther tsi500_VDD +1.2Vtsi500 +2.5Vtsi500 +5VSB_BP +5VSB CGND DGND +2.5V +3.3V +12V -12V +5V Vdd DGND +3.3V 3.3V_Power_Good 5V_Power_Good DDR_Po Core_Power_Good +3.3V DGND +1.5VGE +2.5VGE wer_Good BP_G2_RESET_N BP_G1_RESET_N RIO0_RFRAME_N RIO0_TFRAME_N tsi500_VDD +1.2Vtsi500 +2.5Vtsi500 RIO0_RD_N[0:7] RIO0_TD_N[0:7] TSI500_INT1_N TSI500_INT0_N RIO0_RFRAME RIO0_TFRAME RIO0_RCLK_N RIO0_TCLK_N RIO0_RD[0:7] RIO0_TD[0:7] SENSE_VDD -12V Vdd +2.5V +3.3V +5V +12V +5VSB +5VSB_BP CGND DGND SENSE_VSS RIO0_RCLK RIO0_TCLK ther ther DLALE USR4 LALE FLA8 LA8 SENSE_VSS SENSE_VDD BP_G2_ BP_G1_ WP1_RST_CONF_N WP1_HRESET_REQ_N WP1_COP_TRST_N WP1_T WP1_COP_SR WP1_COP_HRESET_N WP1_HRESET_N WP1_SRE WP1_RTC_CLK RIO1_TXCLK_ RIO1_TXCL WP1_G1_RESET_N WP1_RXD WP1_TXD +1.5 +2.5 Vdd +2.5V +3.3V WP1_SYS_CLK DGND TSI5 TSI5 TSI500_ TSI5 TSI500_HW TSI500_ TSI500_ TSI500_ RIO0_RFRAME_N RIO0_RFRAME RIO0_RCLK_N RIO0_RCLK RIO0_TFRAME_N RIO0_TFRAME RIO0_TCLK DLALE LALE FLA8 LA8 RIO0_TCLK_N RIO0_R RIO0_R RIO0_TD_N[0:7] RIO0_TD[0:7] VGEther VGEther WP3_RST_CONF_N WP3_HRESET_REQ_N WP3_COP_TRST_N WP3_T WP3_COP_SR WP3_COP_HRESET_N WP3_HRESET_N WP3_SRE WP3_RTC_CLK RIO3_TXCLK_ RIO3_TXCL WP3_RXD WP3_TXD +1.5VGEther +2.5VGEther Vdd +2.5V +3.3V +12V WP3_SYS_CLK USR4 CGND DGND RESET_N RESET_N 00_LS1_CLK 00_LS0_CLK 00_TXCLK_IN RST_N 4 4 SET_N TXCLK_IN_N SW_RST_N INT1_N INT0_N D_N[0:7] D[0:7] K_IN RST_N _RST_N IN_N ESET_N SET_N K_IN IN_N ESET_N Work Processor 1 Work Page 23 RapidIO S Page 59 WP1_RST_CONF_N WP1_HRESET_REQ_N WP1_COP_TRST_N WP1_TRST_N WP1_COP_SRESET_N WP1_COP_HRESET_N WP1_HRESET_N WP1_SRESET_N WP1_RTC_CLK WP1_SYS_CLK RIO1_TXCLK_IN_N RIO1_TXCLK_IN WP1_G1_RESET_N WP1_RXD WP1_TXD DGND +1.5VGEther +2.5VGEther Vdd +2.5V +3.3V Work Processor 3 Work Page 47 TSI500_LS1_CLK TSI500_LS0_CLK TSI500_TXCLK_IN_N TSI500_TXCLK_IN TSI500_HW_RST_N TSI500_SW_RST_N TSI500_INT1_N TSI500_INT0_N RIO0_RD_N[0:7] RIO0_RD[0:7] RIO0_RFRAME_N RIO0_RFRAME RIO0_RCLK_N RIO0_RCLK RIO0_TD_N[0:7] RIO0_TD[0:7] RIO0_TFRAME_N RIO0_TFRAME RIO0_TCLK RIO0_TCLK_N WP3_RST_CONF_N WP3_HRESET_REQ_N WP3_COP_TRST_N WP3_TRST_N WP3_COP_SRESET_N WP3_COP_HRESET_N WP3_HRESET_N WP3_SRESET_N WP3_RTC_CLK WP3_SYS_CLK RIO3_TXCLK_IN_N RIO3_TXCLK_IN WP3_RXD WP3_TXD CGND DGND +1.5VGEther +2.5VGEther Vdd +2.5V +3.3V +12V witch

RIO3_TCLK_N RIO3_TCLK_N RIO3_TCLK RIO3_TCLK_N RIO1_RD_N[0:7] RIO3_TCLK RIO3_TFRAME RIO3_TCLK RIO1_RD_N[0:7] RIO1_RD_N[0:7] RIO3_TFRAME RIO3_TFRAME_N RIO3_TFRAME RIO1_RD[0:7] RIO3_TFRAME_N RIO3_TFRAME_N RIO1_RD[0:7] RIO1_RFRAME_N RIO1_RD[0:7] RIO3_TD[0:7] RIO1_RFRAME_N RIO1_RFRAME RIO1_RFRAME_N RIO3_TD[0:7] RIO3_TD[0:7] RIO1_RFRAME RIO1_RCLK RIO1_RFRAME RIO3_TD_N[0:7] RIO1_RCLK RIO1_RCLK_N RIO1_RCLK RIO3_TD_N[0:7] RIO3_TD_N[0:7] RIO1_RCLK_N RIO1_RCLK_N

RIO3_RCLK_N RIO1_TD_N[0:7] ADS_HRESET_N WP3_G1_RESET_N RIO3_RCLK_N RIO3_RCLK RIO3_RCLK_N RIO1_TD_N[0:7] RIO1_TD_N[0:7]

RIO3_RCLK RIO3_RFRAME RIO3_RCLK RIO1_TD[0:7] WP3_INT_N WP2_INT_N WP1_INT_N +5VSB_BP BP_INT_N RIO3_RFRAME RIO3_RFRAME_N RIO3_RFRAME RIO1_TD[0:7] RIO1_TFRAME_N RIO1_TD[0:7] +3.3V_BP ATX_BP +5V_BP WP3_INT_N WP2_INT_N WP1_INT_N RIO3_RFRAME_N RIO3_RFRAME_N RIO1_TFRAME_N RIO1_TFRAME RIO1_TFRAME_N BP_INT_N RIO3_RD[0:7] RIO1_TFRAME RIO1_TCLK RIO1_TFRAME +12V RIO3_RD[0:7] RIO3_RD[0:7] RIO1_TCLK RIO1_TCLK_N RIO1_TCLK +5V RIO3_RD_N[0:7] RIO1_TCLK_N RIO1_TCLK_N RIO3_RD_N[0:7] RIO3_RD_N[0:7] 3 3 WP3_G1_ ADS_HRESET_N RIO2_RFRAME_N RIO2_TFRAME_N ATX_BP +12V +3.3V_BP +5V_BP +5VSB_BP +5V BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RIO2_RD_N[0:7] RIO2_TD_N[0:7] RIO2_RFRAME RIO2_TFRAME RIO2_RCLK_N RESET_N RIO2_TCLK_N RIO2_RD[0:7] RIO2_TD[0:7] BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RIO2_RCLK RIO2_TCLK +1.2Vtsi500 tsi500_VDD +2.5Vtsi500 DGND +3.3V +1.2Vtsi500 tsi500_VDD +2.5Vtsi500 RIO2_TCLK RIO2_TFRAME RIO2_TFRAME_N RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME RIO2_RFRAME_N WP2_G1_ WP2_RST_CONF_N RIO2_TCLK_N RIO2_TD[0:7] RIO2_TD_N[0:7] RIO2_R RIO2_R +3.3V DGND D[0:7] D_N[0:7] ATX_BP SHUTDOWN VIA_RESET_R VIA_RESET_N VIA_ON 3.3V_Power_Good 5V_Power_Good DDR_Po Core_Power_Good WP3_RE WP2_RE WP1_RE WP3_HRESET_REQ_N WP3_COP_ WP3_T WP3_COP_SR WP3_COP_HRESET_N WP3_HRESET_N WP3_SRE PCI_RST_N SYS_RESET_N BP_HRESET_REQ_N BP_COP_ BP_TRST_N BP_COP_SR BP_COP_HRESET_N BP_HRESET_N BP_SRE SYSTEM_RESET_N +5VSB +3.3V ADS_HRESET_N VIA_INT PWR_OK USR4 DGND DGND RESET_N RST_N wer_Good SET_N SET_N SET_N SET_N TRST_N SET_N TRST_N ESET_N EQ_N ESET_N Work Processor 2 Work Page 35 RIO2_TCLK_N RIO2_TCLK RIO2_TFRAME RIO2_TFRAME_N RIO2_TD[0:7] RIO2_TD_N[0:7] RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME RIO2_RFRAME_N RIO2_RD[0:7] RIO2_RD_N[0:7] WP2_G1_RESET_N WP2_RST_CONF_N Page 67 Clocking Page 64 Reset ADS_HRESET_N VIA_INT ATX_BP SHUTDOWN VIA_RESET_REQ_N VIA_RESET_N VIA_ON 3.3V_Power_Good 5V_Power_Good DDR_Power_Good Core_Power_Good PWR_OK WP3_RESET_N WP2_RESET_N WP1_RESET_N WP3_HRESET_REQ_N WP3_COP_TRST_N WP3_TRST_N WP3_COP_SRESET_N WP3_COP_HRESET_N WP3_HRESET_N WP3_SRESET_N PCI_RST_N SYS_RESET_N BP_HRESET_REQ_N BP_COP_TRST_N BP_TRST_N BP_COP_SRESET_N BP_COP_HRESET_N BP_HRESET_N BP_SRESET_N SYSTEM_RESET_N DGND +5VSB USR4 DGND +3.3V TSI500_TXCLK_IN_N 2 2 RIO3_TXCLK_IN_N RIO2_TXCLK_IN_N RIO1_TXCLK_IN_N RIO0_TXCLK_IN_N TSI500_TXCLK_IN TSI500_LS1_CLK TSI500_LS0_CLK RIO3_TXCLK_IN RIO2_TXCLK_IN RIO1_TXCLK_IN RIO0_TXCLK_IN WP3_RTC_CLK WP2_RTC_CLK WP1_RTC_CLK WP3_SYS_CLK WP2_SYS_CLK WP1_SYS_CLK BP_RTC_CLK BP_SYS_CLK WP2_HRESET_REQ_N WP2_COP_HRESET_N WP2_COP_SRESET_N PCI_CLK VIA_CLK LA_CLK WP2_COP_TRST_N RIO2_TXCLK_IN_N WP2_HRESET_N WP2_SRESET_N RIO2_TXCLK_IN WP2_RTC_CLK WP2_SYS_CLK WP2_TRST_N +1.5VGEther +2.5VGEther WP3_INT_N WP2_INT_N WP1_INT_N WP2_HRESET_REQ_N WP2_COP_HRESET_N WP1_HRESET_REQ_N WP1_COP_HRESET_N WP2_COP_SRESET_N WP1_COP_SRESET_N WP2_RXD BP_INT_N WP2_TXD WP3_RST_CONF_N WP2_RST_CONF_N WP1_RST_CONF_N WP2_COP_TRST_N WP1_COP_TRST_N TSI500_HW_RST_N TSI500_SW_RST_N WP3_G1_RESET_N WP2_G1_RESET_N WP1_G1_RESET_N BP_RST_CONF_N BP_G2_RESET_N BP_G1_RESET_N DGND IO_LV_Power_On WP2_HRESET_N WP1_HRESET_N +2.5V +3.3V WP2_SRESET_N WP1_SRESET_N +12V Core_Power_On DDR_Power_On 3.3V_Power_On Vdd WP2_TRST_N WP1_TRST_N 5V_Power_On LA_CLK VIA_CLK PCI_CLK TSI5 TSI5 TSI500_ TSI5 RIO3_TXCLK_IN_N RIO3_TXCL RIO2_TXCLK_IN_N RIO2_TXCL RIO1_TXCLK_IN_N RIO1_TXCL RIO0_TXCLK_IN_N RIO0_TXCL PCI_INTA_N WP3_RTC_CLK WP2_RTC_CLK WP1_RTC_CLK BP_RTC_CLK WP3_SYS_CLK WP2_SYS_CLK WP1_SYS_CLK BP_SYS_CLK 00_LS1_CLK 00_LS0_CLK 00_TXCLK_IN PS_ON DLALE ID[3:0] LALE FLA8 TXCLK_IN_N LA8 WP2_HRESET_REQ_N WP2_COP_ WP2_T WP2_COP_SR WP2_COP_HRESET_N WP2_HRESET_N WP2_SRE WP2_RTC_CLK RIO2_TXCLK_IN_N RIO2_TXCL WP2_RXD WP2_TXD +1.5VGE +2.5VGE Vdd +2.5V +3.3V +12V WP2_SYS_CLK DGND K_IN K_IN K_IN K_IN RST_N ther ther SET_N K_IN BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N TRST_N ESET_N ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K WP3_G1_ WP2_G1_ WP1_G1_ BP_G2_ BP_G1_ Page Title : Page Monday, September 29, 2003 WP2_HRESET_REQ_N WP2_COP_SR WP2_COP_HRESET_N WP1_HRESET_REQ_N WP1_COP_SR WP1_COP_HRESET_N Torridon - RapidIO Enabled Multi-Pr WP2_COP_ WP1_COP_ TSI500_HW TSI500_ WP2_HRESET_N WP2_SRE WP1_HRESET_N WP1_SRE RESET_N RESET_N PCI_INTA_N IO_LV_Power_On 3.3V_Power_On DDR_Power_On 5V_Power_On Core_Power_On WP3_RST_CONF_N WP2_RST_CONF_N WP1_RST_CONF_N BP_RST_CONF_N ID[3:0] PS_ON RESET_N RESET_N RESET_N WP2_T WP1_T SW_RST_N o ee 0.6 Top Level TRST_N TRST_N _RST_N ESET_N ESET_N SET_N SET_N FLA8 LA8 DLALE LALE RST_N RST_N 1 1 ocessing System 372 of ilbride Rev A B C D

Figure A-1. Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B BP_HRESET_REQ_N BP_COP_SRESET_N BP_COP_HRESET_N RIO0_TXCLK_IN_N BP_COP_T RIO0_TXCLK_IN PCI_INTA_N BP_SYS_CLK BP_RTC_CLK TSI500_ TSI500_ BP_TRST_N BP_HRESET_N BP_SR WP3_INT_N WP2_INT_N WP1_INT_N BP_INT_N ID[3:0] ESET_N RST_N INT0_N INT1_N USR4 5 5 PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N TRIG_OUT MSRCID0 USR4 ID[3:0] DGND +3.3V RIO0_TXCLK_IN_N RIO0_TXCL BP_RTC_CLK TSI500_INT0_N TSI500_INT1_N BP_HRESET_REQ_N BP_COP_ BP_T BP_COP_SRESET_N BP_COP_HRESET_N BP_HRESET_N BP_SRESET_N BP_SYS_CLK BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RST_N TRST_N K_IN +3.3V DGND P- Power BP Page 17 BP - RIO Page 8 BP - CPM Page 13 BP - AUX Page 14 RIO0_TXCLK_IN_N RIO0_TXCLK_IN USR4 ID[3:0] BP_SYS_CLK BP_RTC_CLK PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N TRIG_OUT MSRCID0 TSI500_INT0_N TSI500_INT1_N BP_HRESET_REQ_N BP_COP_TRST_N BP_TRST_N BP_COP_SRESET_N BP_COP_HRESET_N BP_HRESET_N BP_SRESET_N BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N DGND +3.3V SYSTEM_RESET_N RIO0_RFRAME_N RIO0_TFRAME_N RIO0_RD_N[0:7] RIO0_TD_N[0:7] WP3_RESET_N WP2_RESET_N WP1_RESET_N RIO0_RFRAME RIO0_TFRAME RIO0_RCLK_N RIO0_TCLK_N RIO0_RD[0:7] RIO0_TD[0:7] SENSE_VDD SENSE_VSS SHUTDOWN RIO0_RCLK RIO0_TCLK G2_IRQ_N G1_IRQ_N I2C_SDA I2C_SCL DGND DGND CGND DGND +3.3V +3.3V MDIO +12V MDC Vdd SENSE_VSS SENSE_VDD +12V Vdd +3.3V RIO0_RCLK_N RIO0_RCLK RIO0_RFRAME_N RIO0_RFRAME RIO0_TCLK RIO0_TFRAME_N RIO0_TFRAME +3.3V SHUTDOWN SYSTEM_R WP3_RE WP2_RE WP1_RE RIO0_TCLK_N DGND DGND CGND DGND RIO0_R RIO0_R RIO0_TD_N[0:7] RIO0_TD[0:7] 4 4 D_N[0:7] D[0:7] SET_N SET_N SET_N MDC G2_IRQ_N G1_IRQ_N I2C_SCL I2C_SDA MDIO ESET_N +12V Vdd +3.3V +3.3V G2GTXCLK G1GTXCLK DGND DGND CGND DGND G2TXD[7:2] G1TXD[7:4] SENS SENSE_VDD E_VSS RIO0_R RIO0_R RIO0_RCLK_N RIO0_RCLK RIO0_RFRAME_N RIO0_RFRAME RIO0_TD_N[0:7] RIO0_TD[0:7] RIO0_TCLK_N RIO0_TCLK RIO0_TFRAME_N RIO0_TFRAME SHUTDOWN SYSTEM_RESET_N WP3_RE WP2_RE WP1_RE BP - TSEC Top Page 9 DDR SDRAM - BP Page 6 G2GTXCLK G1GTXCLK G2TXD[7:2] G1TXD[7:4] MDIO MDC G2_IRQ_N G1_IRQ_N I2C_SCL I2C_SDA D_N[0:7] D[0:7] SET_N SET_N SET_N BP_G2_RESET_N BP_G1_RESET_N +1.5VGEther +2.5VGEther CGND DGND DGND +3.3V +2.5V +3.3V BP_G2_ BP_G1_ +1.5 +2.5 +3.3V +2.5V +3.3V CGND DGND DGND VGEther VGEther RESET_N RESET_N 3 3 DGND +2.5V +3.3V CGND DGND +1.5 +2.5 +3.3V BP_G2_ BP_G1_ VGEther VGEther RESET_N RESET_N BP_RST_CONF_N SYS_RESET_N DLALE LALE LA_CLK DGND +3.3V DLALE LGPL2 LGPL1 LGPL0 LALE LCS_N[0:4] LWE_N[0:3] BLA[27:31] DGND +3.3V BP_RST_CONF_N SYS_RESET_N LA_CLK +3.3V DGND P- PCI BP Page 7 +3.3V DGND DGND +3.3V 2 - Config BP Page 15 BP - Local Bus Flash Page 5 2 BP_RST_CONF_N DGND +3.3V RESET_N LA_CLK DLALE LCS_N[0:4] LWE_N[0:3] LGPL2 LGPL1 LGPL0 LALE BLA[27:31] VIA_RESET_R PCI_REQ_N[1:0] PCI_GNT_N[1:0] PCI_DEVSEL_N PCI_FRAME_N PCI_REQ64_N PCI_ACK64_N PCI_PERR_N PCI_SERR_N PCI_STOP_N PCI_TRDY_N PCI_CBE[7:0] PCI_AD[63:0] PCI_IRDY_N VIA_RES VIA_ON VIA_CLK PCI_RST_N PCI_CLK PCI_PAR_N PCI_PAR64 VIA_INT EQ_N ET_N PCI_GNT_N1 LWE_N[0:3] G2GTXCLK G1GTXCLK G2TXD[7:2] G1TXD[7:4] LCS_N[0:4] TRIG_OUT BLA[27:31] MSRCID0 PCI_GNT_N1 LGPL2 LGPL1 LGPL0 DGND PCI_I PCI_I PCI_INTB_N PCI_INTA_N +3.3V LALE FLA8 CGND DGND LA8 VIA_RESET_R VIA_RESET_N VIA_ON VIA_CLK PCI_RST_N PCI_CLK PCI_REQ64_N PCI_ACK64_N PCI_ PCI_ PCI_PAR_N PCI_STOP_N PCI_IRDY_N PCI_TRDY_N PCI_FRAME_N VIA_INT PCI_PAR64 PCI_DEVSEL_N PCI_GNT_N[1:0] PCI_ PCI_C PCI_AD[63:0] +3.3V +5V -12V +12V NTD_N NTC_N PERR_N SERR_N REQ_N[1:0] BE_N[7:0] FLA8 LA8 +3.3V DGND ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K EQ_N LGPL2 LGPL1 LGPL0 LALE MSRCID0 TRIG_OUT PCI_GNT_N1 G2GTXCLK G1GTXCLK +3.3V +5V -12V +12V CGND DGND BLA[27 G2TXD[7:2] G1TXD[7:4] LCS_N[0:4] LWE_N[0:3] Page Title : Page Monday, September 29, 2003 Torridon - RapidIO Enabled Multi-Pr BP - PCI Expansion BP Page 16 DGND +3.3V :31] CGND DGND +3.3V +5V -12V +12V VIA_INT VIA_RESET_REQ_N VIA_RESET_N VIA_ON VIA_CLK PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N PCI_RST_N PCI_CLK PCI_PAR64 PCI_REQ64_N PCI_ACK64_N PCI_PERR_N PCI_SERR_N PCI_PAR_N PCI_DEVSEL_N PCI_STOP_N PCI_IRDY_N PCI_TRDY_N PCI_FRAME_N PCI_GNT_N[1:0] PCI_REQ_N[1:0] PCI_CBE[7:0] PCI_AD[63:0] otPoesr-TpLvl0.6 Boot Processor - Top Level LA8 FLA8 1 1 ocessing System 472 of ilbride Rev C D A B

Figure A-2. Boot Processor—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-3 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B LGPL4/LGTA/LUPWAIT/LPBSE LOCAL BUS LOCAL LCS7/DMA_DDONE2 LGPL2/LOE/LSDRAS LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LGPL3/LSDCAS LGPL0/LSDA10 LGPL1/LSDWE LSYNC_OUT 5 5 LWE3/LBS3 LWE2/LBS2 LWE1/LBS1 LWE0/LBS0 U2F MPC8560 LSYNC_IN LGPL5 LBCTL LCLK2 LCLK1 LCLK0 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LCKE LCS4 LCS3 LCS2 LCS1 LCS0 LDP3 LDP2 LDP1 LDP0 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 LALE LA31 LA30 LA29 LA28 LA27 U19 T21 T20 T19 T18 U18 V21 U23 V20 T28 V22 V18 U28 U27 N26 N25 N24 N23 N22 P18 P19 P20 P25 P26 R18 R21 R22 R23 R24 T22 V19 W26 W22 W20 Y26 Y22 P21 T26 AA28 AA27 Y21 AA26 AA23 AA22 AC28 AC27 AC26 AD28 AD27 AD26 T27 P28 P27 R28 R27 W28 W27 Y28 Y27 P24 T23 AB27 AB28 V23 V27 V28 U22 LWE_N3 LWE_N2 LWE_N1 LWE_N0 LBCTL LALE BLA31 BLA30 BLA29 BLA28 BLA27 LCS_N4 LCS_N3 LCS_N2 LCS_N1 LCS_N0 LGPL2 LGPL1 LGPL0 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 TP247 TP246 TP245 TP244 TP243 TP242 TP241 TP240 TP238 TP237 TP236 TP235 TP234 DLALE FLA8 LALE LWE_N[0:3] LGPL2 LGPL1 LGPL0 LCS_N[0:4] BLA[27:31] LA8 FLA8 DLALE LALE +3.3V Decoupling 1K R1304 +3.3V R1380 R1379 R764 R763

C422 Do Not Fit Do Not Fit 0.1uF +3.3V Decoupling C425

+3.3V 0.1uF C424 0R 0R 0R 0R 0.1uF +3.3V C426 0.1uF FLALE ILA8 4 4 LGPL2 LGPL1 LGPL0 LWE_N3 LWE_N2 LWE_N1 LWE_N0 LBCTL LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 FLALE LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LGPL2 LWE_N0 LWE_N2 LBCTL LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 FLALE LCS_N0 SN74ALVCH32973KR SN74ALVCH32973KR M1 G2 G1 H4 R2 N2 C2 R1 N1 H1 D1 C1 H3 A3 E2 A2 A4 P1 K1 E1 B1 A1 T4 T1 F1 T3 L2 L1 J3 J2 J4 J1 M1 G2 G1 H4 R2 N2 C2 R1 N1 H1 D1 C1 H3 A3 E2 A2 A4 P1 K1 E1 B1 A1 T4 T1 F1 T3 L2 L1 J3 J2 J4 J1 D8 D7 D6 D5 D4 D3 D2 D1 2TOE 1TOE 2DIR 1DIR 2A8 2A7 2A6 2A5 2A4 2A3 2A2 2A1 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 2LE 1LE 2LOE 1LOE U23 U20 D8 D7 D6 D5 D4 D3 D2 D1 2TOE 1TOE 2DIR 1DIR 2A8 2A7 2A6 2A5 2A4 2A3 2A2 2A1 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 2LE 1LE 2LOE 1LOE

B3 DGND B4 DGND B3 DGND D3 DGND B4 DGND D4 DGND 3V3 P4 D3 DGND E3 DGND 3V3 P3 D4 DGND 3V3 P4 E4 DGND BUS Transceiver 3V3 L4 +3.3V E3 DGND 3V3 P3 K3 DGND & Latch 3V3 L3 E4 DGND BUS Transceiver 3V3 L4 +3.3V K4 DGND 3V3 F4 K3 DGND & Latch 3V3 L3 M3 DGND 3V3 F3 K4 DGND 3V3 F4 M4 DGND 3V3 C4 M3 DGND 3V3 F3 N3 DGND 3V3 C3 M4 DGND 3V3 C4 N4 DGND N3 DGND 3V3 C3 R3 DGND N4 DGND R4 DGND R3 DGND R4 DGND 2Q8 2Q7 2Q6 2Q5 2Q4 2Q3 2Q2 2Q1 1Q8 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q1 2B8 2B7 2B6 2B5 2B4 2B3 2B2 2B1 1B8 1B7 1B6 1B5 1B4 1B3 1B2 1B1 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 2Q8 2Q7 2Q6 2Q5 2Q4 2Q3 2Q2 2Q1 1Q8 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q1 2B8 2B7 2B6 2B5 2B4 2B3 2B2 2B1 1B8 1B7 1B6 1B5 1B4 1B3 1B2 1B1 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 T6 R6 P6 N6 M6 L6 K6 J6 H6 G6 F6 E6 D6 C6 B6 A6 T5 R5 P5 N5 M5 L5 K5 J5 H5 G5 F5 E5 D5 C5 B5 A5 T2 P2 M2 K2 H2 F2 D2 B2 T6 R6 P6 N6 M6 L6 K6 J6 H6 G6 F6 E6 D6 C6 B6 A6 T5 R5 P5 N5 M5 L5 K5 J5 H5 G5 F5 E5 D5 C5 B5 A5 T2 P2 M2 K2 H2 F2 D2 B2 3 3 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 BLGPL2 BLWE_N0 BLWE_N2 BLCS_N0 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 TP341 TP340 TP339 TP338 TP337 TP336 TP335 LA8 BLWE_N0 BLWE_N2 BLA27 BLA28 BLA29 LA27 LA28 LA29 BLA27 BLA28 BLA29 LA27 LA28 LA29 LA_CLK R781 R359 R358 R357 R356 R355 R354 R780 R353 R352 R351 R350 R349 R348 Do Not Fit Do Not Fit RESET_N LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LA_CLK LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R RESET_N BLGPL2 ILA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 RESET_N BLGPL2 ILA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 BLCS_N0 BLCS_N0 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 MICTOR 38 SO +3.3V +3.3V D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A D14A D15A CLKA GND 5V P34 GND 43 42 41 40 39 12 28 26 11 12 28 26 11 10 15 16 17 48 18 19 20 21 22 23 24 25 37 10 15 16 17 48 18 19 20 21 22 23 24 25 37 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 2 2 CLKB D10B D11B D12B D13B D14B D15B SDA D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B SCL AM29LV641D U22 AM29LV641D U21 RESET OE CE WE A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VCC RESET OE CE WE A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VCC CKET 18 16 14 12 10 8 38 36 34 32 30 28 26 24 22 20 2 6 4

4M x 16 FLASH 4M x 16 FLASH LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 DQ15/A-1 DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10 DQ14 DQ13 DQ12 DQ11 DQ10 ACC ACC DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VSS VSS VSS VSS VIO VIO WP WP 27 46 27 46 13 13 45 45 43 41 39 36 34 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 32 30 44 42 40 38 35 33 31 29 14 14 47 47 LA_CLK +3.3V +3.3V +3.3V +3.3V 10K R131 10K R130 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K LA15 LA14 LA13 BLGPL2 BLWE_N0 LA31 LA30 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LA_CLK Decoupling Decoupling BLCS_N0 +3.3V +3.3V

Page Title : Page C423 C421 Friday, September 26, 2003

Torridon - RapidIO Enabled Multi-Pr 0.1uF 0.1uF LA27 LA28 LA29 otPoesr-LclBs-Fah0.6 Boot Processor - Local Bus Flash 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 MICTOR 38 SO D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A D14A D15A CLKA GND 5V P21 GND 43 42 41 40 39 CLKB D10B D11B D12B D13B D14B D15B TP177 TP176 TP175 SDA Decoupling D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B SCL 1 1 CKET +3.3V

+3.3V Power C1094 + 4 18 16 14 12 10 8 6 38 36 34 32 30 28 26 24 22 20 2 10uF,6.3V Tants ocessing System +3.3V DGND BLA31 BLA30 BLA29 BLA28 BLA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 572 DGND +3.3V of ilbride Rev C D A B

Figure A-3. Boot Processor—Local Bus—Flash

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-4 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B TP9 TP8 TP7 TP6 TP5 TP4

Decoupling VREF0 +2.5V +2.5V +2.5V +2.5V C584 C579 C562 C557 0.1uF 0.1uF 0.1uF 0.1uF 0MCK_N5 0MCK5 0MCK_N4 0MCK4 0MCK_N3 0MCK_3 0MCK_N2 0MCK2 0MCK_N1 0MCK1 0MCK_N0 0MCK0 0MCKE1 0MCKE0 0MCS3_N 0MCS2_N 0MCS1_N 0MCS0_N 0MCAS_N 0MRAS_N 0MWE_N 0MBA1 0MBA0 0MA14 0MA13 0MA12 0MA11 0MA10 0MA9 0MA8 0MA7 0MA6 0MA5 0MA4 0MA3 0MA2 0MA1 0MA0 0MDQS8 0MDQS7 0MDQS6 0MDQS5 0MDQS4 0MDQS3 0MDQS2 0MDQS1 0MDQS0 0MDM8 0MDM7 0MDM6 0MDM5 0MDM4 0MDM3 0MDM2 0MDM1 0MDM0 0MECC7 0MECC6 0MECC5 0MECC4 0MECC3 0MECC2 0MECC1 0MECC0 +2.5V +2.5V +2.5V +2.5V 2 1 C585 C580 C563 C558 +

0.1uF C1 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V

VTT0_Sence C586 C581 C564 C559 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V C587 C582 C565 C560 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V R911 R909 R907 R905 R903 R901 R899 R897 R895 R893 R891 R889 R887 R885 R883 R881 R879 R877 R875 R873 R871 R869 R867 R865 R863 R861 R859 R857 R855 R853 R851 R849 R847 R845 R843 R841 R839 R837 R835 R833 R831 R829 R827 R825 R823 R821 R819 R817 R815 R813 R811 R809 R807 R805 R803 R801 R799 R797 R795 R793 R791 R789 R787 R785 R783 C588 C583 C566 C561 4 3 2 1

5 0.1uF 0.1uF 0.1uF 0.1uF 5 VREF VSENSE GND NC U3 LP2995 LP2995 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R Place Near Pin N27 Decoupling Decoupling VREF0 0MSYNC_IN 0MSYNC_OUT VREF0 +2.5V VREF0

VDDQ C978 C1075 Decoupling + AVIN PVIN VTT

0.1uF VREF0 0NCK5 0NCK4 0NCK3 0NCK2 0NCK1 0NCK0 0CKE1 0CKE0 0CAS_N 0RAS_N 0BA1 0BA0 0A14 0A13 0A12 0A11 0A10 0A9 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0DQS8 0DQS7 0DQS6 0DQS5 0DQS4 0DQS3 0DQS2 0DQS1 0DQS0 0DM8 0DM7 0DM6 0DM5 0DM4 0DM3 0DM2 0DM1 0DM0 0ECC7 0ECC6 0ECC5 0ECC4 0ECC3 0ECC2 0ECC1 0ECC0 10uF,6.3V Tants C977 0CK5 0CK4 0CK3 0CK2 0CK1 0CK0 0CS3_N 0CS2_N 0CS1_N 0CS0_N 0WE_N

VREF0 0.1uF 5 8 6 7 C979 0.01uF M28 M21 M19 M20 G27 G16 G24 G14 G19 N27 N28 D20 H25 H15 H16 D17 D27 H23 C23 N19 C20 C13 H18 D25 H28 C21 N20 K14 E20 B15 A15 E28 E26 B19 B18 B25 K19 B24 A23 K21 B21 A22 B13 E16 E18 A19 A21 E19 F27 F28 F20 F17 F21 F14 F16 F24 L14 L26 L21 L24 L19 J20 J15 J16 J13 J14 J25 MVREF(GVdd/2) MSYNC_IN MSYNC_OUT MCK5- MCK5 MCK4- MCK4 MCK3- MCK3 MCK2- MCK2 MCK1- MCK1 MCK0- MCK0 MCKE1 MCKE0 MCS3- MCS2- MCS1- MCS0- MCAS- MRAS- MWE- MBA1 MBA0 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MDQS8 MDQS7 MDQS6 MDQS5 MDQS4 MDQS3 MDQS2 MDQS1 MDQS0 MDM8 MDM7 MDM6 MDM5 MDM4 MDM3 MDM2 MDM1 MDM0 MECC7 MECC6 MECC5 MECC4 MECC3 MECC2 MECC1 MECC0 U2B 2 1 MPC8560 47uF, Tants C2 Bulk Decoupling +2.5V +2.5V

2 1C1167 SDRAM DDR

220uF, Tants

2 1 +2.5V 220uF, Tants

VTT0 C1168 C3 2 1

220uF, Tants GVdd41 GVdd40 GVdd39 GVdd38 GVdd37 GVdd36 GVdd35 GVdd34 GVdd33 GVdd32 GVdd31 GVdd30 GVdd29 GVdd28 GVdd27 GVdd26 GVdd25 GVdd24 GVdd23 GVdd22 GVdd21 GVdd20 GVdd19 GVdd18 GVdd17 GVdd16 GVdd15 GVdd14 GVdd13 GVdd12 GVdd11 GVdd10 MDQ63 MDQ62 MDQ61 MDQ60 MDQ59 MDQ58 MDQ57 MDQ56 MDQ55 MDQ54 MDQ53 MDQ52 MDQ51 MDQ50 MDQ49 MDQ48 MDQ47 MDQ46 MDQ45 MDQ44 MDQ43 MDQ42 MDQ41 MDQ40 MDQ39 MDQ38 MDQ37 MDQ36 MDQ35 MDQ34 MDQ33 MDQ32 MDQ31 MDQ30 MDQ29 MDQ28 MDQ27 MDQ26 MDQ25 MDQ24 MDQ23 MDQ22 MDQ21 MDQ20 MDQ19 MDQ18 MDQ17 MDQ16 MDQ15 MDQ14 MDQ13 MDQ12 MDQ11 MDQ10 GVdd9 GVdd8 GVdd7 GVdd6 GVdd5 GVdd4 GVdd3 GVdd2 GVdd1 MDQ9 MDQ8 MDQ7 MDQ6 MDQ5 MDQ4 MDQ3 MDQ2 MDQ1 MDQ0 1.25V @ B12 A13 H13 F13 A11 D12 E13 D13 D14 E14 D15 C15 K13 C14 E15 G15 L15 A16 L16 G17 B16 C16 K16 K17 A18 C18 L18 M18 L17 D18 J18 N18 E21 H21 D22 G22 G21 J21 F22 B23 D23 A24 C25 D26 E23 C24 E25 C26 G26 H26 J23 J26 E27 F26 J28 K22 K26 K27 M23 M24 K24 L22 L27 M26 A28 B28 C28 D28 G28 L28 A27 J27 A26 A25 F25 K25 M25 D24 H24 G23 L23 B22 E22 J22 D21 N21 A20 G20 K20 D19 F19 H19 G18 B17 E17 J17 D16 F15 K15 A14 G13 L13 C12 F12 J12 1.5A +2.5V 0DQ63 0DQ62 0DQ61 0DQ60 0DQ59 0DQ58 0DQ57 0DQ56 0DQ55 0DQ54 0DQ53 0DQ52 0DQ51 0DQ50 0DQ49 0DQ48 0DQ47 0DQ46 0DQ45 0DQ44 0DQ43 0DQ42 0DQ41 0DQ40 0DQ39 0DQ38 0DQ37 0DQ36 0DQ35 0DQ34 0DQ33 0DQ32 0DQ31 0DQ30 0DQ29 0DQ28 0DQ27 0DQ26 0DQ25 0DQ24 0DQ23 0DQ22 0DQ21 0DQ20 0DQ19 0DQ18 0DQ17 0DQ16 0DQ15 0DQ14 0DQ13 0DQ12 0DQ11 0DQ10 0DQ9 0DQ8 0DQ7 0DQ6 0DQ5 0DQ4 0DQ3 0DQ2 0DQ1 0DQ0 4 4 R910 R908 R906 R904 R902 R900 R898 R896 R894 R892 R890 R888 R886 R884 R882 R880 R878 R876 R874 R872 R870 R868 R866 R864 R862 R860 R858 R856 R854 R852 R850 R848 R846 R844 R842 R840 R838 R836 R834 R832 R830 R828 R826 R824 R822 R820 R818 R816 R814 R812 R810 R808 R806 R804 R802 R800 R798 R796 R794 R792 R790 R788 R786 R784

Decoupling +2.5V +2.5V +2.5V C1204 C1197 C1190

0.1uF 0.1uF 0.1uF 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R +2.5V +2.5V +2.5V C1205 C1198 C1191 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1206 C1199 C1192 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1207 C1200 C1193 0MDQ63 0MDQ62 0MDQ61 0MDQ60 0MDQ59 0MDQ58 0MDQ57 0MDQ56 0MDQ55 0MDQ54 0MDQ53 0MDQ52 0MDQ51 0MDQ50 0MDQ49 0MDQ48 0MDQ47 0MDQ46 0MDQ45 0MDQ44 0MDQ43 0MDQ42 0MDQ41 0MDQ40 0MDQ39 0MDQ38 0MDQ37 0MDQ36 0MDQ35 0MDQ34 0MDQ33 0MDQ32 0MDQ31 0MDQ30 0MDQ29 0MDQ28 0MDQ27 0MDQ26 0MDQ25 0MDQ24 0MDQ23 0MDQ22 0MDQ21 0MDQ20 0MDQ19 0MDQ18 0MDQ17 0MDQ16 0MDQ15 0MDQ14 0MDQ13 0MDQ12 0MDQ11 0MDQ10 0MDQ9 0MDQ8 0MDQ7 0MDQ6 0MDQ5 0MDQ4 0MDQ3 0MDQ2 0MDQ1 0MDQ0 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1208 C1201 C1194 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1209 C1202 C1195 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1210 C1203 C1196 0.1uF 0.1uF 0.1uF I2C_SDA Place Near Pin 1 I2C_SCL Decoupling VREF0 C975 0.1uF 3 VREF0 3 C976 0.01uF +3.3V VddSPD I2C_SCL I2C_SDA 0MDQ59 0MDQ58 0MDQS7 0MDQ57 0MDQ56 0MDQ51 0MDQ50 0MDQS6 0MDQ49 0MDQ48 0MDQ43 0MDQ42 0MDQS5 0MDQ41 0MDQ40 0MDQ35 0MDQ34 0MDQS4 0MDQ33 0MDQ32 0MCS0_N 0MWE_N 0MBA0 0MA10 0MA1 0MA3 0MA5 0MA7 0MA9 0MA12 0MCKE1 0MCK_N0 0MCK0 0MECC3 0MECC2 0MDQS8 0MECC1 0MECC0 0MDQ27 0MDQ26 0MDQS3 0MDQ25 0MDQ24 0MDQ19 0MDQ18 0MDQS2 0MDQ17 0MDQ16 0MCK_N1 0MCK1 0MDQ11 0MDQ10 0MDQS1 0MDQ9 0MDQ8 0MDQ3 0MDQ2 0MDQS0 0MDQ1 0MDQ0 VREF0 +2.5V 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 P16 DDR SODIMM DDR Decoupling Decoupling VTT0 VTT0 C1011 C1019 0.1uF 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

0.1uF VTT0 VTT0 C1020 C1012 0.1uF 0.1uF VTT0 VTT0

+2.5V C1021 C1013 0.1uF 0.1uF VTT0 VTT0 C1022 C1014 0MDQ62 0MDQ53 0MDQ52 0MCK2 0MCK_N2 0MDQ47 0MDQ46 0MDM5 0MDQ45 0MDQ44 0MDQ39 0MDQ38 0MDM4 0MDQ37 0MDQ36 0MCS1_N 0MCAS_N 0MRAS_N 0MBA1 0MA0 0MA2 0MA4 0MA6 0MA8 0MA11 0MCKE0 0MECC7 0MECC6 0MDM8 0MECC5 0MECC4 0MDQ31 0MDQ30 0MDM3 0MDQ29 0MDQ28 0MDQ23 0MDQ22 0MDM2 0MDQ21 0MDQ20 0MDQ15 0MDQ14 0MDM1 0MDQ13 0MDQ12 0MDQ7 0MDQ6 0MDM0 0MDQ5 0MDQ4 VREF0 0MDQ63 0MDM7 0MDQ61 0MDQ60 0MDQ55 0MDQ54 0MDM6 0.1uF 0.1uF VTT0 VTT0 C1023 C1015 0.1uF 0.1uF Do Not Fit VTT0 VTT0 C1024 C1016 R14 R11 0.1uF 0.1uF

4K7 10K +3.3V VTT0 VTT0 R15 R12 C1025 C1017

2 4K7 10K 0.1uF 0.1uF 2

R16 R13 VTT0 VTT0 4K7 10K C1026 C1018 + 0.1uF 10uF,6.3V Tants MT18VDDT6472 SODIMM1 199(200) 41(42) 39(40) 1(2) 200-pin DDR SDRAM SODIMM 0MA1 0MA0 0MA3 0MA2 0MA5 0MA4 0MA7 0MA6 0MA9 0MA8 0MA12 0MA11 0MCKE1 0MCKE0 0MECC3 0MECC7 0MECC2 0MECC6 0MDQS8 0MDM8 0MECC1 0MECC5 0MECC0 0MECC4 0MDQ27 0MDQ31 0MDQ26 0MDQ30 0MDQS3 0MDM3 0MDQ25 0MDQ29 0MDQ24 0MDQ28 0MDQ19 0MDQ23 0MDQ18 0MDQ22 0MDQS2 0MDM2 0MDQ17 0MDQ21 0MDQ16 0MDQ20 0MDQ11 0MDQ15 0MDQ10 0MDQ14 0MDQS1 0MDM1 0MDQ9 0MDQ13 0MDQ8 0MDQ12 0MDQ3 0MDQ7 0MDQ2 0MDQ6 0MDQS0 0MDM0 0MDQ1 0MDQ5 0MDQ0 0MDQ4 Decoupling Decoupling VTT0 VTT0 C980 C567 0.1uF 0.1uF VTT0 VTT0 C981 C568

0.1uF 0.1uF 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 VTT0 VTT0 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN C982 C569 ae Sheet Date: Size : System RN225 RN223 RN28 RN26 RN20 RN16 RN12 RN6 C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 0.1uF 0.1uF VTT0 VTT0 C983 C570 + 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16

Page Title : Page 0.1uF Wednesday, October 01, 2003 VTT0 VTT0 Torridon - RapidIO Enabled Multi-Pr 10uF,6.3V Tants C571 0.1uF VTT0 VTT0_Sence Tap VTT Sence from middle Boot P C572 0.1uF VTT0

oesr-DRSRM0.6 rocessor - DDR SDRAM C573 0.1uF 0MA14 0MA13 0MCS3_N 0MCS2_N 0MDQ59 0MDQ63 0MDQ58 0MDQ62 0MDQS7 0MDM7 0MDQ57 0MDQ61 0MDQ56 0MDQ60 0MDQ51 0MDQ55 0MDQ50 0MDQ54 0MDQS6 0MDM6 0MDQ49 0MDQ53 0MDQ48 0MDQ52 0MDQ43 0MDQ47 0MDQ42 0MDQ46 0MDQS5 0MDM5 0MDQ41 0MDQ45 0MDQ40 0MDQ44 0MDQ35 0MDQ39 0MDQ34 0MDQ38 0MDQS4 0MDM4 0MDQ33 0MDQ37 0MDQ32 0MDQ36 0MCS0_N 0MCS1_N 0MWE_N 0MCAS_N 0MBA0 0MRAS_N 0MA10 0MBA1 VTT0 C574

1 0.1uF 1 +2.5V +3.3V Power VTT0 C575 0.1uF 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 VTT0 ocessing System +2.5V +3.3V DGND C576 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 0.1uF VTT0 RN224 RN29 RN27 RN21 RN17 RN13 RN7 C577

672 0.1uF 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 VTT0 DGND +2.5V +3.3V

C578 VTT0 0.1uF of ilbride Rev C D A B

Figure A-4. Boot Processor—DDR SDRAM

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 PCI_GNT_N[1:0] PCI_ REQ_N[1:0] 4 4 PCI_GNT_N1 PCI_GNT_N0 PCI_REQ_N1 PCI_REQ_N0 10K, RN RN201 1 2

3 +3.3V 4 5 6 10 7 8 9 PCI_ACK64_N PCI_REQ64_N PCI_ PERR_N R663 3 3 PCI_CBE[7:0] 4K7 PCI_SERR_N PCI_DEVSEL_N PCI_STOP_N PCI_IRDY_N PCI_FRAME_N PCI_PAR64 PCI_PAR_N PCI_TRDY_N PCI_ PCI_ PCI_ACK64_N PCI_REQ64_N PCI_IDSEL PCI_STOP_N PCI_IRDY_N PCI_TRDY_N PCI_FRAME_N PCI_PAR_N PCI_CBE7 PCI_CBE6 PCI_CBE5 PCI_CBE4 PCI_CBE3 PCI_CBE2 PCI_CBE1 PCI_CBE0 PCI_DEVSEL_N PCI_PAR64 SERR_N PERR_N AG10 AG13 AD13 AH10 AD10 AC10 AH13 AD11 AC12 AE13 AA11 AB10 W11 W14 AG6 AG5 AG4 AH5 AH8 AE6 AE5 AE4 AA9 AF6 AF3 AF5 Y11 V11 Y14 V14 PCI_GNT4 PCI_GNT3 PCI_GNT2 PCI_GNT1 PCI_GNT0 PCI_REQ4 PCI_REQ3 PCI_REQ2 PCI_REQ1 PCI_REQ0 PCI_SERR PCI_PERR PCI_ACK64 PCI_REQ64 PCI_IDSEL PCI_DEVSEL PCI_STOP PCI_IRDY PCI_TRDY PCI_FRAME PCI_PAR64 PCI_PAR PCI_C_BE7 PCI_C_BE6 PCI_C_BE5 PCI_C_BE4 PCI_C_BE3 PCI_C_BE2 PCI_C_BE1 PCI_C_BE0 U2A MPC8560 PCIX/PCI PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 AA14 AB14 AC14 AD14 AE14 AF14 AG14 AH14 V15 W15 Y15 AA15 AB15 AC15 AD15 AG15 AH15 V16 W16 AB16 AC16 AD16 AE16 AF16 V17 W17 Y17 AA17 AB17 AE17 AF17 AF18 AH6 AD7 AE7 AH7 AB8 AC8 AF8 AG8 AD9 AE9 AF9 AG9 AH9 W10 Y10 AA10 AE11 AF11 AG11 AH11 V12 W12 Y12 AB12 AD12 AE12 AG12 AH12 V13 Y13 AB13 AC13 2 2 PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_AD[63:0] ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Boot Pr cso C nefc 0.6 ocessor - PCI Interface 1 1 +3.3V Power ocessing System +3.3V DGND 772 DGND +3.3V of ilbride Rev C D A B

Figure A-5. Boot Processor—PCI Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-6 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B RIO0_TXCLK_ RIO0_TXCLK_IN IN_N 5 5 RIO0_TXCLK_ RIO0_TXCL K_IN IN_N AF25 AF24 MPC8560 RIO_TXCLK_IN- RIO_TXCLK_IN U2C RIO_RFRAME- RIO_TFRAME- RIO_RFRAME RIO_TFRAME RIO_RCLK- RIO_TCLK- RIO_RCLK RIO_TCLK RIO_RD7- RIO_RD6- RIO_RD5- RIO_RD4- RIO_RD3- RIO_RD2- RIO_RD1- RIO_RD0- RIO_TD7- RIO_TD6- RIO_TD5- RIO_TD4- RIO_TD3- RIO_TD2- RIO_TD1- RIO_TD0- RIO_RD7 RIO_RD6 RIO_RD5 RIO_RD4 RIO_RD3 RIO_RD2 RIO_RD1 RIO_RD0 RIO_TD7 RIO_TD6 RIO_TD5 RIO_TD4 RIO_TD3 RIO_TD2 RIO_TD1 RIO_TD0 AD23 AC22 AE22 AD21 AE20 AD19 AC18 AE18 AE25 AE24 AE26 AC23 AE23 AD22 AC21 AD20 AC19 AE19 AD18 AE21 AD24 AC24 AB24 AA24 W24 V24 U24 T24 AE27 AC20 Y24 Y25 AD25 AC25 AB25 AA25 W25 V25 U25 T25 RIO0_RD_N7 RIO0_RD7 RIO0_RD_N6 RIO0_RD6 RIO0_RD_N5 RIO0_RD5 RIO0_RD_N4 RIO0_RD4 RIO0_RD_N3 RIO0_RD3 RIO0_RD_N2 RIO0_RD2 RIO0_RD_N1 RIO0_RD1 RIO0_RD_N0 RIO0_RD0 RIO0_RFRAME_N RIO0_RFRAME RIO0_RCLK_N RIO0_RCLK RIO0_TFRAME_N RIO0_TFRAME RIO0_TCLK RIO0_TD_N7 RIO0_TD7 RIO0_TD_N6 RIO0_TD6 RIO0_TD_N5 RIO0_TD5 RIO0_TD_N4 RIO0_TD4 RIO0_TD_N3 RIO0_TD3 RIO0_TD_N2 RIO0_TD2 RIO0_TD_N1 RIO0_TD1 RIO0_TD_N0 RIO0_TD0 RIO0_TCLK_N 4 4 RIO0_RCLK RIO0_RCLK_N RIO0_RD0 RIO0_RD_N0 RIO0_RD2 RIO0_RD_N2 RIO0_RD4 RIO0_RD_N4 RIO0_RD6 RIO0_RD_N6 RIO0_RFRAME RIO0_RFRAME_N RIO0_TCLK RIO0_TFRAME RIO0_TFRAME_N RIO0_TCLK_N RIO0_TD0 RIO0_TD_N0 RIO0_TD2 RIO0_TD_N2 RIO0_TD4 RIO0_TD_N4 RIO0_TD6 RIO0_TD_N6 3 3 A10 A11 A12 A13 A14 A15 A10 A11 A12 A13 A14 A15 A10 A11 A12 A13 A14 A15 A10 A11 A12 A13 A14 A15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 A2 A3 A4 A5 A6 A7 A8 A9 P33 P32 P31 P30 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 P686 P686 P686 P686 0/6880 Probe 0/6880 Probe 0/6880 Probe 0/6880 Probe B10 B11 B12 B10 B11 B12 B10 B11 B12 B10 B11 B12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B10 B11 B12 B10 B11 B12 B10 B11 B12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B1 B2 B3 B4 B5 B6 B7 B8 B9 RIO0_RD1 RIO0 RIO0_RD3 RIO0 RIO0_RD5 RIO0 RIO0_RD7 RIO0 RIO0_TD1 RIO0_TD_N1 RIO0_TD3 RIO0_TD_N3 RIO0_TD5 RIO0_TD_N5 RIO0_TD7 RIO0_TD_N7 _RD_N1 _RD_N3 _RD_N5 _RD_N7 2 2 RIO0_RFRAME_N RIO0_RFRAME RIO0_RCLK_N RIO0_RCLK RIO0_RD[0:7] RIO0_R D_N[0:7] RIO0_TFRAME_N RIO0_TFRAME RIO0_TCLK RIO0_TCLK_N RIO0_TD7 RIO0_TD6 RIO0_TD5 RIO0_TD4 RIO0_TD3 RIO0_TD2 RIO0_TD1 RIO0_TD0 RIO0_TD_N7 RIO0_TD_N6 RIO0_TD_N5 RIO0_TD_N4 RIO0_TD_N3 RIO0_TD_N2 RIO0_TD_N1 RIO0_TD_N0 RIO0_RFRAME_N RIO0_RFRAME RIO0_RCLK_N RIO0_RCLK RIO0_RD_N7 RIO0_RD_N6 RIO0_RD_N5 RIO0_RD_N4 RIO0_RD_N3 RIO0_RD_N2 RIO0_RD_N1 RIO0_RD_N0 RIO0_RD7 RIO0_RD6 RIO0_RD5 RIO0_RD4 RIO0_RD3 RIO0_RD2 RIO0_RD1 RIO0_RD0 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr RIO0_TFRAME_N RIO0_TFRAME RIO0_TCLK_N RIO0_TCLK RIO0_TD[0:7] RIO0_TD_N[0:7] otPoesr-RpdOItrae0.6 Processor - RapidIO Interface Boot 1 1 Power ocessing System DGND 872 DGND of ilbride Rev C D A B

Figure A-6. Boot Processor—RapidIO Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 DGND +3.3V +3.3V DGND BP - TSEC Page 10 DGND +3.3V 4 4 G2RXD[7:0] G1RXD[7:0] G2GTXCLK G1GTXCLK G2TXD[7:0] G1TXD[7:0] G2RXCLK G1RXCLK MGTX125 G2TXCLK G1TXCLK G2RXER G2RXDV G1RXER G1RXDV G2TXER G2TXEN G1TXER G1TXEN G2CRS G1CRS G2COL G1COL BP_G2 BP_G1 G2_IRQ_N G1_IRQ_N G2TXD[7:2] G1TXD[7:4] _RESET_N _RESET_N MDC MDIO G2GTXCLK G1GTXCLK G2TXD[7:2] G1TXD[7:4] MGTX125 G2CRS G2RXCLK G2RXER G2RXDV G2GTXCLK G2TXCLK G2TXER G2TXEN BP_G2_ G2_IRQ_N MDC BP_G1_ G1_IRQ_N G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN MDIO G2COL G1COL G2RX G1RX G2TXD[7:0] G1TXD[7:0] 3 3 D[7:0] D[7:0] RESET_N RESET_N MDC MDIO BP - TSEC - PHY1 - BP Page 11 BP - TSEC - PHY2 - BP Page 12 G2COL G2CRS G2RXCLK G2RXER G2RXDV G2GTXCLK G2TXCLK G2TXER G2TXEN G2RXD[7:0] G2TXD[7:0] BP_G2_RESET_N G2_IRQ_N MDC MDIO MDC MDIO BP_G1_RESET_N G1_IRQ_N MGTX125 G1COL G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN G1RXD[7:0] G1TXD[7:0] +1.5VGEther +2.5VGEther +1.5VGEther +2.5VGEther DGND CGND DGND +3.3V +3.3V +1.5VGEther +2.5VGEther +3.3V +1.5VGEther +2.5VGEther +3.3V DGND CGND DGND 2 2 +1.5V +2.5V +3.3V +1.5V +2.5V +3.3V DGND CGND DGND GEther GEther GEther GEther ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 05, 2003 Torridon - RapidIO Enabled Multi-Pr otPoesr-GgBt tentItrae-Tp0.6 Processor - GigaByte Ethernet Interface Top Boot 1 1 ocessing System 972 of ilbride Rev C D A B

Figure A-7. Boot Processor—GigaByte Ethernet Interface—Top

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-8 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B +3.3V H10 C5 E7 A4 LVdd4 LVdd3 LVdd2 LVdd1 b Clocking GbE TSEC2 TSEC1 U2G TSEC2_GTX_CLK TSEC1_GTX_CLK EC_GTX_CLK125 MPC8560 TSEC2_RX_CLK TSEC1_RX_CLK TSEC2_TX_CLK TSEC1_TX_CLK TSEC2_RX_ER TSEC2_RX_DV TSEC1_RX_ER TSEC1_RX_DV TSEC2_TX_ER TSEC2_TX_EN TSEC1_TX_ER TSEC1_TX_EN TSEC2_RXD7 TSEC2_RXD6 TSEC2_RXD5 TSEC2_RXD4 TSEC2_RXD3 TSEC2_RXD2 TSEC2_RXD1 TSEC2_RXD0 TSEC1_RXD7 TSEC1_RXD6 TSEC1_RXD5 TSEC1_RXD4 TSEC1_RXD3 TSEC1_RXD2 TSEC1_RXD1 TSEC1_RXD0 TSEC2_TXD7 TSEC2_TXD6 TSEC2_TXD5 TSEC2_TXD4 TSEC2_TXD3 TSEC2_TXD2 TSEC2_TXD1 TSEC2_TXD0 TSEC1_TXD7 TSEC1_TXD6 TSEC1_TXD5 TSEC1_TXD4 TSEC1_TXD3 TSEC1_TXD2 TSEC1_TXD1 TSEC1_TXD0 TSEC2_CRS TSEC1_CRS TSEC2_COL TSEC1_COL 5 5 C10 B6 E2 F8 G7 E10 D6 B10 A10 J10 K11 J11 H11 G11 E11 A6 F7 D7 C7 B7 A7 G8 E8 D11 B11 B8 C8 F9 E9 C9 B9 A9 H9 G10 F10 D4 B4 D3 D5 B5 A5 F6 E6 A8 H8 E5 D2 D9 C3 D10 C6 R183 R182 R181 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 RN104 RN99 22R, RN 22R, RN G1RXCLK G1RXER G1RXDV R186 R185 R184 MGTX125 G2CRS G2RXCLK G2RXER G2RXDV G2RXD7 G2RXD6 G2RXD5 G2RXD4 G2RXD3 G2RXD2 G2RXD1 G2RXD0 G1CRS G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 G2COL G1COL 22R 0.1W 22R 0.1W 22R 0.1W 22R 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 Decoupling +3.3V G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0

C699 0.1W 22R 0.1W 22R 0.1W 22R 0.1uF G2TXD7 G2TXD6 G2TXD5 G2TXD4 G2TXD3 G2TXD2 G2TXD1 G2TXD0 +3.3V G2GTXCLK G2TXCLK G2TXER G2TXEN G1GTXCLK G1TXCLK G1TXER G1TXEN C700 G1RX 0.1uF G2RX +3.3V C701 D[7:0] 0.1uF D[7:0] +3.3V C702 0.1uF G1COL G1CRS G1RXCLK G1RXER G1RXDV MGTX125 G2COL G2CRS G2RXCLK G2RXER G2RXDV G2GTXCLK G2TXCLK G2TXER G2TXEN G1GTXCLK G1TXCLK G1TXER G1TXEN G1TXD[7:0]

Decoupling +3.3V C1095 +

4 10uF,6.3V Tants 4 G2RXD0 G2RXD1 G2RXD2 G2RXD3 G2RXD4 G2RXD5 G2RXD6 G2RXD7 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G2RXD0 G2RXD1 G2RXD2 G2RXD3 G2RXD4 G2RXD5 G2RXD6 G2RXD7 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G2RXD[7:0] G1RXD[7:0] 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 3R RN 330R, RN107 RN 330R, RN102 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 RN105 RN 220R, RN100 2R RN 220R, 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 100pF, CN 100pF, CN 100pF, 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 +3.3V +3.3V 100pF, CN 100pF, CN 100pF, CN7 CN3 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 CN5 CN1 3 3 G2TXD0 G2TXD1 G2TXD2 G2TXD3 G2TXD4 G2TXD5 G2TXD6 G2TXD7 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 G2TXD[7:0] G2TXD0 G2TXD1 G2TXD2 G2TXD3 G2TXD4 G2TXD5 G2TXD6 G2TXD7 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 3R RN 330R, RN108 RN 330R, RN103 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 RN106 RN101 2R RN 220R, RN 220R, G2TXD[7:0] G1TXD[7:0] 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 100pF, CN 100pF, CN 100pF, 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 +3.3V +3.3V 100pF, CN 100pF, CN 100pF, CN8 CN4 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 CN6 CN2 2 2 MGTX125 G2RXCLK G2GTXCLK G2TXEN G1RXCLK G1GTXCLK G1TXEN 220R R187 220R R579 220R R573 220R R567 220R R561 220R R555 220R R549 +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V

330R R188 330R R580 330R R574 330R R568 330R R562 330R R556 330R R550

100pF C136 100pF C875 100pF C872 100pF C869 100pF C866 100pF C863 100pF C860 G2CRS G2RXDV G2TXER G1CRS G1RXDV G1TXER 220R R581 220R R575 220R R569 220R R563 220R R557 220R R551 ae Sheet Date: Size : System +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K

Page Title : Page 330R R582 330R R576 330R R570 330R R564 330R R558 330R R552 Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr 100pF C876 100pF C873 100pF C870 100pF C867 100pF C864 100pF C861 Boot P G2RXER G2TXCLK G1RXER G1TXCLK G2COL G1COL +3.3V Power oesr-GgBt tentItrae0.6 rocessor - GigaByte Ethernet Interface 220R R583 220R R577 220R R571 220R R565 220R R559 220R R553 +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V DGND 1 1

330R R584 330R R578 330R R572 330R R566 330R R560 330R R554

100pF C877 100pF C874 100pF C871 100pF C868 100pF C865 100pF C862 ocessing System 072 10 +3.3V DGND of ilbride Rev C D A B

Figure A-8. Boot Processor—GigaByte Ethernet Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B MDIO MDC MDC MDIO BP_G1_RESET_N 5 5 1K R1312 +3.3V 1K R1313 G1RXD[7:0] G1TXD[7:0] G1GTXCLK +3.3V MGTX125 G1RXCLK G1_IRQ_N R1299 G1TXCLK G1TXER G1TXEN G1CRS G1COL G1RXER G1RXDV 10K C262 C261 +1.5VGEther BP_G1_RE 18pF 18pF G1RXCLK G1RXER G1RXDV

3 2 G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0 G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 0.01uF C50 MGTX125 G1TXCLK G1TXER G1TXEN G1CRS G1GTXCLK G1_IRQ_N G1COL

4 1 SET_N 0.1uF C54

R118 R116 R113 0.1W 22R R105 R104 R103 0.01uF C51 8 7 6 5 4 3 2 1 25MHz Y4 22R, RN 0.1uF C55

0.01uF C52 RN64 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R R111 0.1uF C56 GROUND Separate 9 10 11 12 13 14 15 16 0R 0.01uF C53 22R 0.1W 22R R121 0.1uF C57 0.01uF C30

U17 mill trace must be 50 0.1uF C35 G2 G1 H2 H1 D8 C9 C8 D9 K2 E9 K3 A1 E1 B2 B4 A3 A2 A4 A5 B3 B9 A9 B8 A8 B7 A7 B6 B5 A6 E8 F7 F2 F1 J2 J1 +3.3V +3.3V 0.01uF C31 VSSC XTAL1 XTAL2 SEL_2_5V RESET COMA TXD_7 TXD_6 TXD_5 TXD_4 TXD_3 TXD_2 TXD_1 TXD_0 TX_CLK TX_ER TX_EN CRS COL GTX_CLK CLK125 RXD_7 RXD_6 RXD_5 RXD_4 RXD_3 RXD_2 RXD_1 RXD_0 RX_CLK RX_ER RX_DV MDIO MDC INT 0.1uF C36 4 4 0.01uF C32 R1305 K7 LED_YELLOW 0R R1306 CONFIG_6 0.1uF C37 J7 CONFIG_5

2 1 0R R1307 L9 1.5V E3 0R R1308 CONFIG_4 DVDDL 0.01uF C33 K9 CONFIG_3 DVDDL H3

LD3 330R 0R R1309 K8 CONFIG_2 DVDDL D7

R126 0R R1310 J9 G7 0.1uF C38 0R R1311 CONFIG_1 DVDDL J8 CONFIG_0

0R 0.01uF C34 +2.5VGEther

H9 2.5V M3 LED_TX AVDDL 0.1uF C39 F8 LED_LINK10 AVDDL L2 G8 B1

LED_LINK1000 AVDDL 3PIN_FERRITE H8 LED_RX AVDDL M7 0.1uF C419 3 G9 LED_DPLX AVDDL M8

330R F9 88E1011S LED_LINK100 G1AVDDH R129 AVDDH N5 L5 M6 49R9 2 HDAC_N R322 49R9 HDAC_P M5 TP43 M4 R323 1 LED_YELLOW TP44 CTRL25 TP41 E2 CTRL_15 DVDDH G3 2 1 M2 F3 2K49 R122 RSET DVDDH TP42 0.01uF C40

LD5 330R 3.3V M9 TDI VDDO H7

R127 0.1uF C45 M1 TRST VDDO J3 R123 4K7 L1 TMS VDDO C5

10K 0.01uF C41 L8 TDO VDDO C6 K1 E7 LED_RED TCK VDDO 0.1uF C46 2 1

R324 0.01uF C42 G6 DGND DGND G4

LD6 330R J6 DGND DGND D6 R125 +3.3V 0.1uF C47 H4 DGND DGND L7 F4 L6 DGND DGND 0.01uF C43 G5 DGND DGND K6 E4 L5 LED_YELLOW DGND DGND 0.1uF C48 D5 DGND DGND K5 2 1 D4 DGND DGND J5 C4 L4 0.01uF C44 LD1 DGND DGND C7 DGND DGND E6

3 0.1uF C49 +3.3V 3 E5 DGND DGND L3 H6 DGND DGND J4 F6 DGND DGND K4 H5 DGND DGND F5 SOUT_M SOUT_P SCLK_M SCLK_P MDI3_M MDI2_M MDI1_M MDI0_M MDI3_P MDI2_P MDI1_P MDI0_P SIN_M SIN_P D2 C3 D1 C2 N8 N6 N3 N1 D3 C1 N9 N7 N4 N2 CONFIG6 SEL_BDT INT_POL 75/50 OHMCONFIG6 SEL_BDT INT_POL 75/50 CONFIG5 DIS_FC DIS_SLEEP HWCFG_ CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_ CONFIG3 ANEG[0] ENA_XC D CONFIG2 ANEG[3] ANEG[2] A CONFIG1 ENA_PAUSE PHYADR[4] PHY OFG 0 1 1 0 CONFIG6 0 0 CONFIG5 1 0 CONFIG4 1 0 CONFIG3 0 CONFIG2 1 CONFIG1 0 CONFIG0 0 Bit[2] Bit[1] Bit[0] Pin CONFIG0 PHYADR[2] PHYADR[1] PHY Bit[2] Bit[1] Bit[0] Pin

C770.01uF C720.01uF C670.01uF C590.01uF R117 49R9 49R9 R110 49R9 49R9 R106 49R9 49R9 R99 49R9 49R9 R112 R107 R100 R96 CONFIG6 VSS CONFIG5 VDDO CONFIG4 VDDO CONFIG3 VSS CONFIG2 LED_LINK10 CONFIG1 VSS CONFIG0 VSS Pin Setting BP_PH1_M3 BP_PH1_P3 BP_PH1_M2 BP_PH1_P2 BP_PH1_M1 BP_PH1_P1 BP_PH1_M0 BP_PH1_P0 IS_125 NEG[1] ADR[3] ADR[0] MODE[3] MODE[0] 2 2 D4A D2A 10A 1A 2A 4A 3A 6A 5A 8A 7A 9A RJG5-7G05 VSS 0 0 VSS 0 0 0 LED_TX 0 1 1 LED_RX 0 0 1LED_DUPLEX 0 1 0LED_LINK1000 1 0 0LED_LINK100 1 1 1LED_LINK10 1 0 1 VDD0 1 1 Bit[2:0] Pin P5A 1:1 1:1 1:1 1:1 D3A D1A 11A ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K +3.3V Page Title : Page Monday, September 29, 2003 Torridon - RapidIO Enabled Multi-Pr +1.5VGEther +2.5VGEther LED flashing => Transmitting or Rece LED off => Link Down LED on => Link Up LED_TX is used as a global activity indica NOTE: When PHY register 24.2:0='111', LED off => Link Down LED on => Link Up LED_LINK1000 is used as a global link indica NOTE: When PHY register 24.4:3='01', Boot ProcessorBoot - Gig +3.3V Power +1.5VGEther +2.5VGEther +3.3V DGND 1 1 CGND Bt tentItrae-PY 0.6 aByte Ethernet Interface - PHY1 ocessing System +1.5VGEther +2.5VGEther +3.3V CGND DGND 172 11 iving of ilbride tor. tor. Rev C D A B

Figure A-9. Boot Processor—GigaByte Ethernet Interface—PHY1

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-10 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B BP_G2_ RESET_N G2RXD[7:0] G2TXD[7:0] 5 +3.3V 5 R1300 G2GTXCLK 10K G2RXCLK G2_IRQ_N G2TXCLK G2TXER G2TXEN G2CRS G2COL G2RXER G2RXDV MDIO MDC C264 C263 BP_G2_RES +1.5VGE 18pF 18pF ther MDC 3 2 MDIO 0.01uF C100 G2TXD7 G2TXD6 G2TXD5 G2TXD4 G2TXD3 G2TXD2 G2TXD1 G2TXD0 G2TXCLK G2TXER G2TXEN G2CRS G2GTXCLK G2RXD7 G2RXD6 G2RXD5 G2RXD4 G2RXD3 G2RXD2 G2RXD1 G2RXD0 G2RXER G2RXDV G2_IRQ_N G2COL G2RXCLK ET_N 4 1 0.1uF C104

0.01uF C101 8 7 6 5 4 3 2 1 25MHz Y5 22R 22R 22R R141 R140 R139 22R, RN

0R 0R 0R 0.1uF C105

R153 R151 R148 0.01uF C102 TP49 RN69 0.1uF C106 GROUND Separate 9 10 11 12 13 14 15 16 0R 0.01uF C103 R156 0.1W 0.1W 0.1W 0.1uF C107 0.01uF C80

U25 mill trace must be 50 0.1uF C85 G2 G1 H2 H1 D8 C9 C8 D9 K2 E9 K3 A1 E1 B2 B4 A3 A2 A4 A5 B3 B9 A9 B8 A8 B7 A7 B6 B5 A6 E8 F7 F2 F1 J2 J1 +3.3V 0.01uF C81 VSSC XTAL1 XTAL2 SEL_2_5V RESET COMA TXD_7 TXD_6 TXD_5 TXD_4 TXD_3 TXD_2 TXD_1 TXD_0 TX_CLK TX_ER TX_EN CRS COL GTX_CLK CLK125 RXD_7 RXD_6 RXD_5 RXD_4 RXD_3 RXD_2 RXD_1 RXD_0 RX_CLK RX_ER RX_DV MDIO MDC INT +3.3V 0.1uF C86

0.01uF C82 R1314 K7 LED_YELLOW 0R R1315 CONFIG_6 0.1uF C87 J7 CONFIG_5

2 1 0R R1316 L9 3.3V 1.5V E3 0R R1317 CONFIG_4 DVDDL 0.01uF C83 K9 CONFIG_3 DVDDL H3

LD9 330R 0R R1318 K8 CONFIG_2 DVDDL D7

R161 0R R1319 0.1uF C88 J9 CONFIG_1 DVDDL G7

4 0R R1320 4 J8 CONFIG_0

0R 0.01uF C84 +2.5

H9 LED_TX 2.5V AVDDL M3

0.1uF C89 VGEther F8 LED_LINK10 AVDDL L2 G8 B1

LED_LINK1000 AVDDL 3PIN_FERRITE H8 LED_RX AVDDL M7 3

88E1011S 0.1uF C420 G9 LED_DPLX AVDDL M8

330R F9 LED_LINK100 G2AVDDH L6 R164 AVDDH N5 M6 49R9 2 HDAC_N R325 49R9 HDAC_P M5 TP50 M4 R326 1 LED_YELLOW TP51 CTRL25 TP47 E2 CTRL_15 DVDDH G3 2 1 M2 F3 2K49 R157 RSET DVDDH 0.01uF C90

LD11 330R TP48 M9 TDI VDDO H7

R162 0.1uF C95 M1 TRST VDDO J3 R158 4K7 L1 TMS VDDO C5

10K 0.01uF C91 L8 TDO VDDO C6 K1 E7 LED_RED TCK VDDO 0.1uF C96 2 1

R327 0.01uF C92 G6 DGND DGND G4

LD12 330R +3.3V J6 DGND DGND D6

R160 0.1uF C97 H4 DGND DGND L7 F4 L6 DGND DGND 0.01uF C93 G5 DGND DGND K6 E4 L5 LED_YELLOW DGND DGND 0.1uF C98 D5 DGND DGND K5 2 1 D4 DGND DGND J5 C4 L4 0.01uF C94 LD7 DGND DGND C7 DGND DGND E6

0.1uF C99 +3.3V E5 DGND DGND L3 H6 DGND DGND J4 F6 DGND DGND K4 H5 DGND DGND F5 SOUT_M SOUT_P SCLK_M SCLK_P MDI3_M MDI2_M MDI1_M MDI0_M MDI3_P MDI2_P MDI1_P MDI0_P SIN_M SIN_P 3 3 N9 N7 N4 N2 D2 C3 D1 C2 D3 N8 N6 N3 N1 C1

C1270.01uF C1220.01uF C1170.01uF C1090.01uF R152 49R9 49R9 R146 49R9 49R9 R142 49R9 49R9 R135 49R9 49R9 R147 R143 R136 R132 OFG 0 1 1 0 CONFIG6 0 0 CONFIG5 1 0 CONFIG4 1 1 CONFIG3 0 CONFIG2 1 CONFIG1 0 CONFIG0 0 Bit[2] Bit[1] Bit[0] Pin OHMCONFIG6 SEL_BDT INT_POL 75/50 CONFIG5 DIS_FC DIS_SLEEP HWCFG_ CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_ CONFIG3 ANEG[0] ENA_XC D CONFIG2 ANEG[3] ANEG[2] A CONFIG1 ENA_PAUSE PHYADR[4] PHY CONFIG0 PHYADR[2] PHYADR[1] PHY Bit[2] Bit[1] Bit[0] Pin BP_PH2_M3 BP_PH2_P3 BP_PH2_M2 BP_PH2_P2 BP_PH2_M1 BP_PH2_P1 BP_PH2_M0 BP_PH2_P0 D4B D2B 10B LED flashing => Transmitting or Rece LED off => Link Down LED on => Link Up LED_TX is used as a global activity indica NOTE: When PHY register 24.2:0='111', LED off => Link Down LED on => Link Up LED_LINK1000 is used as a global link indica NOTE: When PHY register 24.4:3='01', 1B 2B 4B 3B 6B 5B 8B 7B 9B RJG5- CONFIG6 VSS CONFIG5 VDDO CONFIG4 VDDO CONFIG3 VSS CONFIG2 LED_LINK10 CONFIG1 VSS CONFIG0 LED_TX Pin Setting 7G05 2 2 IS_125 NEG[1] ADR[3] ADR[0] P5B 1:1 1:1 1:1 1:1 MODE[3] MODE[0] VSS 0 0 VSS 0 0 0 LED_TX 0 1 1 LED_RX 0 0 1LED_DUPLEX 0 1 0LED_LINK1000 1 0 0LED_LINK100 1 1 1LED_LINK10 1 0 1 VDD0 1 1 Bit[2:0] Pin iving D3B D1B tor. tor. +3.3V ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Monday, September 29, 2003 Torridon - RapidIO Enabled Multi-Pr Boot ProcessorBoot - Gig +1.5VGEther +2.5VGEther +3.3V Power DGND 1 1 +1.5VGEther +2.5VGEther +3.3V Bt tentItrae-PY 0.6 aByte Ethernet Interface - PHY2 ocessing System 272 12 DGND +1.5VGEther +2.5VGEther +3.3V of ilbride Rev C D A B

Figure A-10. Boot Processor—GigaByte Ethernet Interface—PHY2

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B SYSTEM_RESET_N WP3_RESET_N WP2_RESET_N WP1_RESET_N SHUTDOWN 5 5 ID[3:0] USR4 ID3 ID2 ID1 ID0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 ID3 ID2 ID1 ID0 SYSTEM_RESET_N SHUTDOWN WP3_RESET_N WP2_RESET_N WP1_RESET_N USR4 M10 N11 N10 P10 P11 L11 L10 M1 M2 M3 M6 M7 M8 M9 R7 R6 R5 R4 R3 R2 R1 N9 N8 N7 N6 N5 N4 N1 H2 H1 P1 P2 P3 P4 P5 P6 P7 P8 P9 K1 K2 K3 K6 K7 K8 L9 L8 L5 L4 L3 L2 L1 J8 J7 J6 J5 J4 J3 J2 J1 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17/FEC_RX_DV PB16/FEC_RX_ER PB15/FEC_TX_ER PB14/FEC_TX_EN PB13/FEC_COL PB12/FEC_CRS PB11/FEC_RXD3 PB10/FEC_RXD2 PB9/FEC_RXD1 PB8/FEC_RXD0 PB7/FEC_TXD0 PB6/FEC_TXD1 PB5/FEC_TXD2 PB4/FEC_TXD3 PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 U2H MPC8560

Alt. DUART CPM Alt. 10/100 Eth.Alt. DUART PD30/UART_SOUT0 PD27/UART_SOUT1 PC17/FEC_RX_CLK PC18/FEC_TX_CLK PD29/UART_RTS0 PD26/UART_RTS1 PC15/UART_CTS0 PC13/UART_CTS1

PD31/UART_SIN0 PD28/UART_SIN1 Alt. 10/100 Eth. 4 4 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PC31 PC30 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC16 PC14 PC12 PC11 PC10 PD9 PD8 PD7 PD6 PD5 PD4 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SYSTEM_RESET_N SHUTDOWN ID3 ID2 ID1 ID0 V6 V9 AE3 AD2 AE2 AD5 AC1 AC2 AC3 AC4 AC7 AB6 AB5 AB3 AB2 AB1 AA1 AA2 AA3 AA4 AA7 AA8 Y9 W9 W8 W7 W6 W3 W2 W1 V1 V2 V3 V4 V5 U10 U8 U4 U3 U2 Y6 Y5 Y4 Y3 Y2 Y1 U1 T1 T4 T5 T6 T9 R11 R10 R9 R8 AD6 AD1 U9 U7 DEBUG_RXD DEBUG_TXD

R1321 10K R1322 10K R1323 10K

R1324 +3.3V 10K R1325 10K R1326 10K DEBUG_TXD DEBUG_RXD 3 3 0.1uF C252 +3.3V 0.1uF C250 C5 D2 C4 C3 C2 C6 D1 C1 B4 B3 B2 A6 B5 A3 A2 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 NC7 NC6 NC5 NC4 NC3 NC2 NC1 Tin Rout FORCEON FORCEOFF C2- C2+ C1- C1+ U38 +3.3V Do Not Fit E1 GND Vcc A1 INVALID MAX3229 NC10 NC11 NC12 NC13 NC14 Tout NC8 NC9

R249 R245 0.1uF C248 Rin V+ V- 4K7 10K Vl R250 R246 E3 D5 B6 D6 E4 E6 A4 A5 D3 D4 E5 E2 4K7 10K B1 R251 R247 4K7 10K

R252 R248 +3.3V

4K7 10K +3.3V

R770 R766 0.1uF C251 4K7 10K R771 R767

4K7 10K 0.1uF C254 R772 R768 4K7 10K C249

R773 R769 0.1uF 4K7 10K 2 2 GND RXD TXD 5 9 4 8 3 7 2 6 1

11 10 CONNECTOR DB9-P CONNECTOR P6 1000pF C253 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Wednesday, October 01, 2003 Torridon - RapidIO Enabled Multi-Pr Boot Processor - Communications Decoupling +3.3V

0.1uF C842 1 1 +3.3V Power ocessing System +3.3V CGND DGND 372 13 CGND DGND +3.3V oue0.6 Module of ilbride Rev C D A B

Figure A-11. Boot Processor—Communications Processor Module

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-12 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 MSRCID0 TRIG_OUT MDC MDIO +3.3V +3.3V R632 R631 +3.3V TP40 TP157 TP156 TP155 TP154 TP153 +3.3V TP36 BP_HRESET_N BP_HRESET_REQ_N BP_SRESET_N CHKSTOP_OUT_N CHKSTOP_IN_N 9 4K7 4K7 R95 R94 4K7 R93 R92 R84 0R 0R MDC MDIO ASLEEP MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT THERM1 THERM0 CLK_OUT 4K7 4K7 AG20 AG19 AG18 AG22 AG28 AH16 AH20 AH28 AH27 AH26 AH25 AB22 AE28 AF20 AF22 AF28 AG2 AG1 M11 AH3 AH2 AH1 N12 G1 G2 G3 E1 A3 A2 B2 B1 F4 F2 F5 F3 F1 J9 HRESET HRESET_REQ SRESET CKSTP_OUT CKSTP_IN ASLEEP TEST_SEL(Draco/Dracom) LSSD_MODE MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT/READY/QUIESCE TRIG_IN L2_TSTCLK THERM1 THERM0 CLK_OUT L1_TSTCLK EC_MDIO EC_MDC NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 U2D MPC8560 AUXILIARY FUNCTION PIC CLOCKING 4 4 SPARES Eth.MI IRQ11/DMA_DDONE3 IRQ10/DMA_DACK3 SYS. CNTRL SYS. JTAG IRQ9/DMA_DREQ3 I2C ANALOG DMA DMA_DDONE1 DMA_DDONE0 DMA_DREQ1 DMA_DREQ0 DMA_DACK1 DMA_DACK0 PWR Mng. PWR DFT IRQ_OUT SYSCLK SPARE4 SPARE3 SPARE2 SPARE1 IIC_SDA IIC_SCL TRST IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 MCP TMS TDO UDE RTC TCK TDI DEBUG AH23 AF23 AF19 AH21 C1 AF1 U11 T11 AB20 AG25 AA19 Y19 AA21 AG24 AB18 Y18 AA18 AB23 AH22 AF21 AG23 G6 H7 G5 H6 G4 H5 AB21 AH24 AF26 Y20 AG16 AG17 AG21 TSI500_ TSI500_ G2_IRQ_N G1_IRQ_N PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N IRQ0_N MCP_N BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N UDE_N I2C_SDA I2C_SCL BP_RTC_CLK BP_SYS_CLK +3.3V 10K, RN RN62 TCK TMS BP_TRST_N TDO TDI

INT1_N INT0_N 1 TP35 TP34 TP33 TP32 2 3

4K7 R623 +3.3V 1 4 5 +3.3V 2 6 10 3 7 5 4 8

4K7 R624 10 6 9 BP_SYS_CLK BP_RTC_CLK 7 8 9 RN63 I2C_SCL 10K, RN I2C_SDA 3 3 WP3_INT_N WP2_INT_N WP1_INT_N TSI500_ TSI500_ G2_IRQ_N G1_IRQ_N PCI_I PCI_I PCI_INTB_N BP_INT_N PCI_INTA_N NTD_N NTC_N INT1_N INT0_N CHKSTOP_OUT_N BP_COP_HRESET_N BP_COP_SR TMS TCK TDO TDI ESET_N +3.3V 2 2 10K R85 BP_HRESET_REQ_N BP_COP_ BP_TRST_N BP_COP_SR BP_COP_HRESET_N BP_HRESET_N BP_SRE 10K R86 SET_N TRST_N 10K R87 ESET_N 10K R88 15 13 11 9 7 5 3 1 2x8 Header HD2 16 14 12 10 8 6 4 2 KEY KEY +3.3V BP_HRESET_REQ_N BP_COP_T BP_TRST_N BP_COP_SRE BP_COP_HRESET_N BP_HRESET_N BP_SRESET_N 10K R89 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 2K R90 RST_N Page Title : Page Friday, September 26, 2003 SET_N 10K R91 Torridon - RapidIO Enabled Multi-Pr CHKSTOP_IN_N BP_COP_T otPro Boot RST_N esr-Axlr ucin 0.6 cessor - Auxilary Functions 1 1 +3.3V Power ocessing System +3.3V DGND 472 14 DGND +3.3V of ilbride Rev C D A B

Figure A-12. Boot Processor—Auxiliary Functions

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5

"CONFIGURATION" Proce Memory PCI/RIO TSEC RIO Proce BIST Unused ssor PCI PCI LB RIO ssor "Debug Enable" "Host/Agent 0" "Host/Agent 1" "TSEC2 Mode" "TSEC1 Mode" "I/O "BIST Enable" "BIST "Unu "LB Hold 1" "Device ID7" "CPU Boot" Loc.2" "ROM Loc.1" "ROM Loc.0" "ROM "LB Hold 0" "PCI Hold 1" "PCI Hold 0" "Device "Device "Device "Device "Device "RIO Clk 1" "RIO Clk 0" "Core "Sys "Sys "Sys "Sys "Device "Core "Device Impd" sed" PLL3" PLL2" PLL1" PLL0" PLL1" PLL0" ID6" ID4" ID3" ID2" ID1" ID5" ID0" 4 4 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 SW DIP-8 SW SW17 DIP-8 SW SW16 DIP-8 SW SW15 DIP-8 SW SW14 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 10K, RN RN115 10K, RN RN113 1 1 2 2

3 +3.3V 3 +3.3V 4 5 4 5 6 10 6 10 7 7

BP_RST_CONF_N 8 8 9 9 10K, RN RN116 10K, RN RN114 1 1 2 2

3 +3.3V 3 +3.3V 4 5 4 5 6 10 6 10 7 7 8 8 9 9 3 3 24 25 48 24 25 48 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 1 1 U19 U18 OE4 4A4 4A3 4A2 4A1 OE3 3A4 3A3 3A2 3A1 OE2 2A4 2A3 2A2 2A1 OE1 1A4 1A3 1A2 1A1 OE4 4A4 4A3 4A2 4A1 OE3 3A4 3A3 3A2 3A1 OE2 2A4 2A3 2A2 2A1 OE1 1A4 1A3 1A2 1A1

4 DGND 4 DGND 10 DGND 74ALVT16244 10 DGND 74ALVT16244 15 DGND 3V3 7 +3.3V 15 DGND 3V3 7 +3.3V 21 DGND 3V3 18 21 DGND 3V3 18 28 DGND 3V3 31 28 DGND 3V3 31 34 DGND 3V3 42 34 DGND 3V3 42 39 DGND 39 DGND 45 DGND 4Y4 4Y3 4Y2 4Y1 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 45 DGND 4Y4 4Y3 4Y2 4Y1 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 23 22 20 19 17 16 14 13 12 11 9 8 6 5 3 2 23 22 20 19 17 16 14 13 12 11 9 8 6 5 3 2 R741 R740 R738 R737 R736 R735 R734 R733 R732 R731 Do Not Fit 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R BLA27 LWE_N1 LWE_N0 LWE_N2 LWE_N3 G2TXD4 G2TXD5 G2TXD6 G2TXD7 G1TXD4 G1TXD5 G1TXD6 G1TXD7 LGPL1 LGPL0 LGPL2 LALE BLA31 BLA30 BLA29 BLA28 BLA27 MSRCID0 LWE_N3 LWE_N2 PCI_GNT_N1 TRIG_OUT LCS_N2 LCS_N1 LCS_N0 LCS_N4 LCS_N3 G2GTXCLK G1GTXCLK G2TXD2 G2TXD3 TP228 G2TXD2 G2TXD3 G2TXD4 G2TXD5 G2TXD6 G2TXD7 LCS_N[0:4] LWE_N[0:3] G1TXD[ LGPL1 LGPL0 LGPL2 LALE BLA[27:31] MSRCID0 PCI_GNT_N1 G2GTXCLK G1GTXCLK TRIG_OUT 2 2 7:4] G2TXD[7:2] Add R733,R734 Remove R731,R732,R735,R736,R737,R738,R740 For Rev 2 silicon; Note : Configuration shown is for Rev 1 Sili ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K

Decoupling Page Title : Page +3.3V Friday, September 05, 2003

Torridon - RapidIO Enabled Multi-Pr C771 0.1uF +3.3V C772

Boot Processor - Configura 0.1uF +3.3V C773 0.1uF 1 1 +3.3V Power ,R741 con. ocessing System in0.6 tion +3.3V DGND 572 15 DGND +3.3V of ilbride Rev C D A B

Figure A-13. Boot Processor—Power On Configuration

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-14 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 4 4 PCI_CLK PCI_RST_N PCI_PAR64 PCI_ACK64_N PCI_REQ64_N PCI_ PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N PCI_STOP_N PCI_PAR_N PCI_DEVSEL_N PCI_ PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_GNT_N[1:0] PCI_ PCI_CBE[7:0] PCI_AD[63:0] PERR_N SERR_N REQ_N[1:0] PCI_CLK PCI_RST_N PCI_ACK64_N PCI_REQ64_N PCI_ PCI_I PCI_I PCI_INTB_N PCI_INTA_N PCI_STOP_N PCI_PAR_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_PAR64 PCI_ PCI_GNT_N[1:0] PCI_ PCI_CBE[7:0] PCI_AD[63:0] PCI_DEVSEL_N PERR_N SERR_N REQ_N[1:0] NTD_N NTC_N VIA_RESET_R VIA_RES VIA_ON VIA_CLK VIA_INT EQ_N ET_N 3 3 VIA_RESET_REQ_N VIA_RESET_N VIA_ON VIA_CLK PCI_INTA_N PCI_STOP_N PCI_PAR_N PCI_ PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_GNT_N0 PCI_REQ_N0 VIA_INT PCI_DEVSEL_N PCI_CBE[3:0] PCI_AD[31:0] PCI_GNT_N1 PCI_REQ_N1 SERR_N BP - PCI Slot BP Page 21 Southbridge Page 17 VIA_INT VIA_RESET_REQ_N VIA_RESET_N VIA_ON VIA_CLK PCI_INTA_N PCI_STOP_N PCI_PAR_N PCI_DEVSEL_N PCI_SERR_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_GNT_N0 PCI_REQ_N0 PCI_CBE[3:0] PCI_AD[31:0] PCI_CLK PCI_RST_N PCI_PAR64 PCI_ACK64_N PCI_REQ64_N PCI_PERR_N PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N PCI_STOP_N PCI_PAR_N PCI_DEVSEL_N PCI_SERR_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_GNT_N1 PCI_REQ_N1 PCI_CBE[7:0] PCI_AD[63:0] CGND DGND DGND +3.3V +3.3V +12V +12V -12V +5V +5V +3.3V +5V +12V +3.3V +5V +12V -12V CGND DGND DGND 2 2 +3.3V +5V +12V +3.3V +5V +12V -12V CGND DGND DGND ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Tuesday, October 07, 2003 Torridon - RapidIO Enabled Multi-Pr otPoesr-PIEpnin0.6 Processor - PCI Expansion Boot 1 1 ocessing System 672 16 of ilbride Rev C D A B

Figure A-14. Boot Processor—PCI Expansion

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 VIA_RESET_REQ_N 4 VIA_ON VIA_CLK VIA_RESET_N PCI_INTA_N PCI_GNT_N0 PCI_REQ_N0 PCI_PAR_N PCI_ PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N 4 PCI_CBE[3:0] PCI_AD[31:0] VIA_INT SERR_N CGND DGND DGND +5V +3.3V +3.3V +5V +12V DACK5_N DACK3_N VIA_CLK VIA_RESET_N +5V +3.3V VIA_ON VIA_RESET_R PCI_INTA_N PCI_GNT_N0 PCI_REQ_N0 PCI_PAR_N PCI_ PCI_STOP_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N +3.3V +5V +12V VIA_INT PCI_DEVSEL_N CGND DGND DGND PCI_CBE[3:0] PCI_AD[31:0] SERR_N EQ_N SB - SIDE,ISA,Per Page 19 SB - PCI,PIDE,AC97 - SB Page 18 DACK5_N DACK3_N CGND +5V DGND +3.3V VIA_ON VIA_INT VIA_RESET_REQ_N VIA_CLK VIA_RESET_N PCI_INTA_N PCI_GNT_N0 PCI_REQ_N0 PCI_PAR_N PCI_SERR_N PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_CBE[3:0] PCI_AD[31:0] DGND +3.3V +5V +12V ipheral SDDACK_N PDDACK_N SDDIOW_N PDDIOW_N SDDIOR_N PDDIOR_N SDD[15:0] SDCS3_N SDCS1_N PDCS3_N PDCS1_N PDD[15:0] DACK5_N DACK3_N USBDT1+ USBDT0+ SDD_IRQ PDD_IRQ USBDT1- USBDT0- RSTDRV USBCLK SDA[2:0] PDA[2:0] SDDRQ PDDRQ SDRDY PDRDY OC1_N OC0_N S_80P P_80P 3 3 SDDRQ SDDA SDRDY SDDIOW_N SDCS3_N SDCS1_N S_80P P_80P PDDRQ PDDA PDRDY PDDIOW_N PDCS3_N PDCS1_N SDDIOR_N PDDIOR_N SDA[2:0] PDD[ PDA[2:0] OC1_N OC0_N USBDT1- USBDT1+ USBDT0- USBDT0+ USBCLK SDD_IRQ PDD_IRQ RSTDRV SDD[ 15:0] CK_N CK_N 15:0] DACK5_N DACK3_N SB - IO SB Page 20 OC1_N OC0_N USBDT1- USBDT1+ USBDT0- USBDT0+ USBCLK SDD_IRQ PDD_IRQ RSTDRV SDD[15:0] SDDRQ SDDACK_N SDRDY SDDIOW_N SDDIOR_N SDCS3_N SDCS1_N SDA[2:0] S_80P P_80P PDDRQ PDDACK_N PDRDY PDDIOW_N PDDIOR_N PDCS3_N PDCS1_N PDD[15:0] PDA[2:0] DGND +3.3V +5V +3.3V +5V DGND 2 2 +3.3V +5V DGND Size : System ae Sheet Date: C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page T Tuesday, October 07, 2003 Torridon - RapidIO Enabled Multi-Pr itle : otbig 0.6 Southbridge 1 1 ocessing System 772 17 of ilbride Rev C D A B

Figure A-15. Southbridge—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-16 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B PCI_INTA_N PCI_INTA_N FAN2 FAN1 INTD_N INTC_N INTB_N INTA_N 5 5 4K7,5% RN185 1 2 3

4 5 +3.3V 6 10 7 8 9 C899 C898 PCI_AD18 10pF 10pF PCI_AD13

2 1 R1377 R652 +3.3V Do Not Fit 32KHz Y12 33R D13 VIA_RESET_R 2 33R PCI_GNT_N0 PCI_REQ_N0 PCI_PAR_N PCI_S PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_CBE[3:0] PCI_AD[31:0] 4 3 2 1 MBRS130L VIA_CLK PDRDY PDDIOW_N PDDRQ PDDACK_N PDCS3_N PDCS1_N HEADE PDDIOR_N PDD[15:0] 1 ERR_N HD33 PDA[2:0] EQ_N 4 0.1uF C900 4 R4x1

3 1 JP19 2 VIA_CLK INTD_N INTC_N INTB_N INTA_N VIA_RESET_R PCI_GNT_N0 PCI_REQ_N0 PCI_PAR_N PCI_ PCI_STOP_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_CBE3 PCI_CBE2 PCI_CBE1 PCI_CBE0 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PDD15 PDD14 PDD13 PDD12 PDD11 PDD10 PCI_DEVSEL_N PDD9 PDD8 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 PDRDY PDDIOW_N PDDRQ PDDA PDCS3_N PDCS1_N PDA2 PDA1 PDA0 PDDIOR_N SERR_N +3.3V CK_N +3.3V EQ_N M20 M16 M15 M18 M19 M17 G18 G16 G17 G20 G19 C17 D17 C19 N18 N17 R14 R11 N15 H15 R10 C20 C18 D18 D19 D20 H16 H17 H18 H19 H20 N16 N19 N20 R16 R18 R20 R19 R17 B17 A16 B16 K15 E16 A17 B18 A18 B19 A19 A20 B20 E17 E18 E19 E20 K16 K17 K18 K19 K20 P17 P19 P20 P18 P16 F20 F19 F18 F17 F16 T17 T19 T20 T18 T16 L19 L18 L20 L16 L17 J19 J15 J16 J17 J18 J20 W5 R8 R7 R9 Y6 Y5 VT82C686B VCC VCC VCC VCC VCC VCC VCC VCC VCC VBAT VCCS VCCS RTCX2 RTCX1 PCICLK PINTD PINTC PINTB PINTA PCIRST GNT REQ IDSEL PAR SERR DEVSEL STOP TRDY IRDY FRAME C_BE3 C_BE2 C_BE1 C_BE0 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PDRDY PDIOW PDIOR PDDRQ PDDACK PDCS3 PDCS1 PDA2 PDA1 PDA0 PDD15 PDD14 PDD13 PDD12 PDD11 PDD10 PDD9 PDD8 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 U76A SUSA/APICACK/GPO1 PCI, PIDE, AC97 CHAS/GPIOC/GPIO10 SUSB/APICCS/GPO2 FAN2/GPIOB/GPIO9 LID/APICREQ/GPI3 PME/GPI5/THRM CPUSTP/GPO4 SUSST1/GPO3 BATLOW/GPI2 PCISTP/GPO5 SDD5/-ACRST SMBALT/GPI6 GPIOA/GPIO8 SDD4/SDOUT SDD0/BITCLK SDD13/JBB1 SDD12/JBB2 SDD11/JAB1 SDD10/JAB2 SDD2/SDIN2 SDD14/MSO SDD3/SYNC SDD1/SDIN SDD15/MSI RING/GPI7 SLP/GPO7 GPI1/IRQ8 SMBDATA SDD9/JAX SDD8/JAY SDD7/JBX SDD6/JBY GNDHWM VCCHWM PWRBTN RSMRST SDDACK SMBCLK CLKRUN CPURST SUSCLK STPCLK PWRGD EXTSMI SDDRQ SDRDY SDIOW SDCS3 SDCS1 TSEN2 TSEN1 GPIOD IGNNE SDIOR GPO0 SUSC SPKR FERR 3 3 VREF A20M SDA2 SDA1 SDA0 FAN1 INTR IN2B IN2A GND GND GND GND GND IN12 INIT NMI SMI IN5 U12 U9 T10 Y17 V17 Y13 W13 U8 V14 V15 Y15 U14 W15 Y19 Y14 T12 W6 V13 U13 R15 P15 L15 G15 F15 V16 Y16 W18 T9 T6 T13 U15 W8 Y18 R13 T14 R12 W17 U16 W16 T15 W14 Y20 V20 U20 V18 U19 V5 T8 Y9 W9 V9 W10 U10 V6 Y11 U11 T11 V11 Y10 V10 V12 Y12 W11 W12 W7 U6 T7 Y8 V7 V8 Y7 W20 W19 V19 U18 U17 U7 0.1uF C905 R651 SDRDY SDDIOW_N SDDRQ SDDA SDCS3_N SDCS1_N ACRST_N SDOUT SYNC SDIN BITCLK SDA2 SDA1 SDA0 SDDIOR_N SDIN2 R657 R656 10K R659 CK_N 10K, RN 10K, RN181 S_80P VIA_RESET_N VIA_ON EXTSMI_N P_80P 100R +3.3V 1 10uF,6.3V Tants TP196 TP195 TP194 TP193 TP192 TP191 TP190 TP189 TP188 TP187 TP186 TP185 TP184 2 FAN2 FAN1 3 + 10K 10K 4 5 +3.3V C904 6 10 1 1

+12V 7

Ferrite L23 Ferrite L22 8 SDRDY SDDIOW_N SDDRQ SDDA SDCS3_N SDCS1_N SDA[2:0] SDDIOR_N

R658 R655 R679 53K,1% R680 9 CK_N Bead Bead 10K, RN RN182

2 2 1 10K 10K 10K +3.3V 0.1uF C903 2 3 S_80P VIA_RES VIA_ON P_80P

4 5 +3.3V

10K, RN RN183 6 10 1 7 +5V

ET_N 2 8 3 9

16K,1% R654 4 5 +3.3V

R678 R677 R676 R653 6 10 7 8 9 4K7 4K7 10K 10K, RN RN184 0R

0.1uF C902 1 VIA_INT DACK5_N DACK3_N

2 2 2 3

4 5 +3.3V 6 10 7 8 9 VIA_INT ACRST_N SDOUT SYNC SDIN BITCLK SDIN2 DACK5_N DACK3_N 4 3 2 1 HEADE 15 13 11 9 7 5 3 1 HD29 2x8 Header HD37 R4x1 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 16 14 12 10 8 6 4 2 Page Title : Page Tuesday, October 07, 2003 Torridon - RapidIO Enabled Multi-Pr +12V +5V B-PIPD,C70.6 PCI,PIDE,AC97 - SB +3.3V 1 1 Power +3.3V +5V +12V ocessing System +3.3V +5V +12V DGND 872 18 DGND +3.3V +5V +12V of ilbride Rev C D A B

Figure A-16. Southbridge—PCI, PIDE, AC97

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 10K, RN RN199 1 2 3

5 4 5 +3.3V 5 6 10 7 8 9

C908 0.1uF 1 gnd Vdd +3.3V 2 4 14.318MHz OUT CLK Y13 10K, RN RN196 10K, RN RN190 OC0_N_PU OC1_N_PU 1 1

3 2 2 3 3

4 5 +3.3V 4 5 +3.3V 6 10 6 10 7 7 8 8

R704 9 9 R705 10K, RN RN197 10K, RN RN191 1 1 0R 0R 2 2 3 3

4 5 +3.3V 4 5 +3.3V 6 10 6 10 OC0_N OC1_N

SDD_IRQ PDD_IRQ 7 7 RSTDRV 8 8 9 9 4 4K7,5% RN198 10K, RN RN192 4 1 1 2 2 OC0_N_PU OC1_N_PU 3 3 SDD[15:0]

4 5 4 5 +3.3V 6 10 6 10 7 7 8 8 9 9 DACK5_N DACK3_N SDD_IRQ PDD_IRQ 14.318M RSTDRV TP227 TP226 TP223 TP218 TP214 TP212 TP210 TP209 TP208 TP207 TP204 TP203 SDD15 SDD14 SDD13 SDD12 SDD11 SDD10 SDD9 SDD8 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 HZ_CLK +3.3V D12 E12 F14 F13 F12 F10 W4 W3 W2 W1 M6 M5 M1 M4 M2 M3 G1 G2 G3 G4 U5 U4 C2 D1 N2 D2 N6 H6 H4 H5 H1 H2 N4 D3 N5 N3 N1 R1 R2 R3 R4 R5 U1 U2 U3 B1 A1 V4 E3 E1 K6 K5 K4 K3 E4 A2 B2 E2 P2 P1 Y4 V3 Y3 Y2 Y1 K1 K2 P3 P4 P5 V1 V2 F7 F5 T1 T2 T3 T4 T5 F4 F1 F3 F2 L4 L2 L1 L3 L5 J6 J1 J2 J3 J4 J5 VT82C686B VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SOE/GPO13 XDIR/GPO12 IRQ15 IRQ14 IRQ11 IRQ10 IRQ9 IRQ7 *IRQ6/SLPBTN IRQ5 IRQ4 IRQ3 IRTX/GPO14 IRRX/GPO15 BCLK OSC RSTDRV TC IOCHK/GPI0 IOCHRDY MEMCS16 IOCS16 SMEMW SMEMR MEMW MEMR IOW IOR REFRESH SBHE BALE AEN DRQ7 DRQ6 DRQ5 DRQ3 DRQ1 DRQ0 DACK7 DACK6 DACK5 DACK3 DACK1 DACK0 SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 LA23 LA22 LA21 LA20 SA19 SA18 SA17 SA16 *SA15/SDD15 *SA14/SDD14 *SA13/SDD13 *SA12/SDD12 *SA11/SDD11 *SA10/SDD10 *SA9/SDD9 *SA8/SDD8 *SA7/SDD7 *SA6/SDD6 *SA5/SDD5 *SA4/SDD4 *SA3/SDD3 *SA2/SDD2 *SA1/SDD1 *SA0/SDD0 U76B *DRQ2/OC1/SERIRQ/GPIOE SIDE, ISA, *DACK2/OC0/GPIOF *ROMCS/KBCS *KBCK/KA20G MSDT/IRQ12 PERIPHERAL KBDT/KBRC MSCK/IRQ1 DRVDEN1 DRVDEN0 *USBCLK DSKCHG WRTPRT *USBP3+ *USBP2+ *USBP1+ *USBP0+ GNDUSB VCCUSB STROBE AUTOFD *USBP3- *USBP2- *USBP1- *USBP0- TRAK00 3 3 WGATE WDATA ERROR SLCTIN RDATA HDSEL INDEX MTR1 MTR0 DCD2 DCD1 BUSY RXD2 DSR2 RXD1 DSR1 PRD7 PRD6 PRD5 PRD4 PRD3 PRD2 PRD1 PRD0 STEP DTR2 DTR1 CTS2 RTS2 TXD2 CTS1 RTS1 TXD1 SLCT PINIT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ACK DS0 DS1 DIR RI2 RI1 PE E6 B4 D4 B3 E5 B10 B12 A13 E14 D14 C14 B14 A14 D15 B15 D6 D9 D5 C5 D10 A11 E13 C3 R6 P6 M12 M11 M10 M9 L12 L11 L10 L9 L6 K12 K11 K10 K9 J12 J11 J10 J9 G6 F11 F6 A5 B5 A4 C4 A3 F8 D13 F9 C13 C6 C7 B6 A6 E7 B7 A7 E8 D8 C8 B8 A8 E9 D7 C1 G5 H3 C9 A10 C10 A9 E10 B9 E11 A12 C12 C11 B11 D11 D16 E15 C16 C15 A15 B13 0.1uF C907 MSDT MSCLK KBDT KBCLK OC0_N OC1_N USBDT1- USBDT1+ USBDT0- USBDT0+ USBCLK 10K, RN RN186 1

TP225 TP224 TP222 TP221 TP220 TP219 TP217 TP216 TP215 TP213 TP211 10uF,6.3V Tants TP202 TP201 TP200 TP199 TP198 TP197 2 3 +

4 5 +3.3V C906 6 10

L25 L24 7

1 1 8 OC0_N OC1_N USBDT1- USBDT1+ USBDT0- USBDT0+ USBCLK

Ferrite Bead Ferrite Bead Ferrite 9 10K, RN RN187 1 2 2

+3.3V 2 Decoupling 3

+3.3V 4 5 +3.3V C1089 6 10 0.1uF 7

+3.3V 8 C1090 9 0.1uF +3.3V

C1091 10K, RN RN188 0.1uF 1

+3.3V 2 C1092 3

0.1uF 4 5 +3.3V

2 6 10 2 7 8 9

Decoupling 10K, RN RN189

+3.3V 1 C1093 2 + 3

10uF,6.3V Tants 4 5 +3.3V 6 10 7

10K, RN RN195 8 1 9 2 3

4 5 +3.3V 6 10 7 8

9 PolyFuse ae Sheet Date: Size : System +5V C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K

tce PS2 Stacked 2 1 F3 Page Title : Page Wednesday, October 01, 2003 Torridon - RapidIO Enabled Multi-Pr 10 12 2 4 6 8 P35 G1 Bottom Top

SB - SIDE,ISA,Per G2 G3 G4 G5 1 3 5 7 9 11 1 Power 1 pea 0.6 ipheral +3.3V +5V +5V R1327 ocessing System R1328 4K7 R1329 4K7 +3.3V +5V CGND DGND R1330 4K7 4K7 972 19 KBDT KBCLK MSDT MSCLK of +3.3V +5V CGND DGND ilbride Rev C D A B

Figure A-17. Southbridge—Side, ISA, Peripheral

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-18 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B SDA[2:0] PDA[2:0] SDD[15:0] PDD[15:0] SDD_IRQ SDDACK_N SDRDY SDDIOR_N SDDIOW_N SDDRQ PDD_IRQ PDDACK_N PDRDY PDDIOR_N PDDIOW_N PDDRQ 5 5 PDRDY PDDIOW_N PDDIOR_N SDD_IRQ SDDACK_N SDRDY SDDIOW_N SDDRQ PDD_IRQ PDDACK_N PDDRQ SDDIOR_N SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 SDA0 SDA1 PDA0 PDA1 +5V +5V 1K R685 1K R643 +5V +5V 10K R686 10K R644 4K7 R689 R687 4K7 R647 R645 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 +5V RN210 RN208 +5V RN179 RN177 33R, RN 33R, RN 33R, RN 33R, RN 1K R690 1K R649 10K 10K 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 1 1 MMSD4148T1 D15 MMSD4148T1 D12 Shrouded H Shrouded H 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 2 2 9 7 5 3 1 9 7 5 3 1 P24 P23 SHD_LED PHD_LED SHD_LED eader 20x2 eader 20x2 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

2 1 R688 R646 HD23 4 R648 4 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Header LED Hard Disk 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 RN211 RN180 33R, RN 33R, RN 470R 470R RN209 RN178 33R, RN 33R, RN 470R 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 +5V 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 SDCS1_N SDCS3_N S_80P SDD15 SDD14 SDD13 SDD12 SDD11 SDD10 PDCS1_N PDCS3_N P_80P PDD15 PDD14 PDD13 PDD12 PDD11 PDD10 SDA2 PDA2 SDD9 SDD8 PDD9 PDD8 Secondary Hard Disk Primary Hard Disk SDCS1_N SDCS3_N S_80P PDCS1_N PDCS3_N P_80P 74ACT14 4 2 74ACT14 U75B U75A +3.3V 7 14 7 14 3 1 VCC RSTDRV RSTDRV +3.3V Drive Drive 3 3 RSTDRV OC0_N

OC0_N Decoupling +3.3V

C974 USBDT1+ USBDT0+ USBDT1- USBDT0- 0.1uF C946 USBD0- USBD0+ 1000pF

R697 560K

R699 R695 15K R702 15K USBDT1- USBDT1+ USBDT0- USBDT0+ 2 2

C950 470K +

10uF,6.3V Tants 1 +5V gnd Vdd C952 2 Ferrite Bead1 2 1 +3.3V

0.1uF L27 PolyFuse 2 4 F1 C942 48MHz

47pF OUT CLK Y14 L29 1 9 7 5 3 1

2x5 Header C947 C943 3 Ferrite Bead Ferrite HD27 1uF,10V 47pF

C944 47pF 10 8 6 4 2

C948 R782

2 1uF,10V C945 47pF R694 R693 R692 R691 +5V C953 2 Ferrite Bead1 2 1 22R 0.1W 22R 0.1uF L28 PolyFuse F2 R696 27R 27R 27R 27R C951 USBCLK + ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 10uF,6.3V Tants 470K Page Title : Page

Wednesday, October 01, 2003 R700 15K USBD0- USBD1+ USBD0+ USBD1- Torridon - RapidIO Enabled Multi-Pr R701 15K R698 560K USBCLK otbig O0.6 Southbridge - IO USBD1- USBD1+ C949 1000pF OC1_N 1 1 +3.3V +5V Power USB ocessing System OC1_N +3.3V +5V DGND 072 20 DGND +3.3V +5V of ilbride Rev C D A B

Figure A-18. Southbridge—IO

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B PCI_CBE[7:0] PCI_AD[63:0] PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N PCI_RST_N PCI_CLK PCI_PAR64 PCI_PAR_N PCI_PERR_N PCI_SERR_N PCI_DEVSEL_N PCI_STOP_N PCI_IRDY_N PCI_FRAME_N PCI_REQ64_N PCI_ACK64_N PCI_GNT_N1 PCI_REQ_N1 PCI_TRDY_N 5 5 PCI_GNT_N1 PCI_CBE7 PCI_CBE6 PCI_CBE5 PCI_CBE4 PCI_CBE3 PCI_CBE2 PCI_CBE1 PCI_CBE0 PCI_INTD_N PCI_INTC_N PCI_INTB_N PCI_INTA_N PCI_RST_N PCI_CLK PCI_PAR_N PCI_PERR_N PCI_SERR_N PCI_STOP_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_REQ64_N PCI_ACK64_N PCI_REQ_N1 PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_PAR64 PCI_DEVSEL_N PCI_AD33 PCI_AD35 PCI_AD37 PCI_AD39 PCI_AD41 PCI_AD43 PCI_AD45 PCI_AD47 PCI_AD49 PCI_AD51 PCI_AD53 PCI_AD55 PCI_AD57 PCI_AD59 PCI_AD61 PCI_AD63 PCI_CBE4 PCI_CBE6 PCI_ACK64_N PCI_AD1 PCI_AD3 PCI_AD5 PCI_AD7 PCI_AD8 PCI_M PCI_AD10 PCI_AD12 PCI_AD14 PCI_CBE1 PCI_ PCI_ PCI_IRDY_N PCI_CBE2 PCI_AD17 PCI_AD19 PCI_AD21 PCI_AD23 PCI_CBE3 PCI_AD25 PCI_AD27 PCI_AD29 PCI_AD31 PCI_REQ_N1 PCI_CLK PCI_INTD_N PCI_INTB_N PCI_DEVSEL_N 4 4 SERR_N PERR_N 66EN +3.3V +5V -12V B94 B93 B92 B91 B90 B89 B88 B87 B86 B85 B84 B83 B82 B81 B80 B79 B78 B77 B76 B75 B74 B73 B72 B71 B70 B69 B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 PCI CONNE P26 GND Reserved7 Reserved6 GND AD[33] AD[35] +3.3V AD[37] AD[39] GND AD[41] AD[43] GND AD[45] AD[47] +3.3V AD[49] AD[51] GND AD[53] AD[55] GND AD[57] AD[59] +3.3V AD[61] AD[63] GND C/BE[4]# C/BE[6]# GND Reserved5 +5V +5V ACK64# +3.3V AD[01] GND AD[03] AD[05] +3.3V AD[07] AD[08] GND GND M66EN AD[10] AD[12] GND AD[14] C/BE[1]# +3.3V SERR# +3.3V PERR# LOCK# GND DEVSEL# +3.3V IRDY# GND C/BE[2]# AD[17] +3.3V AD[19] AD[21] GND AD[23] C/BE[3]# +3.3V AD[25] AD[27] GND AD[29] AD[31] +3.3V REQ# GND CLK GND Reserved4 PRSNT2# Reserved3 PRSNT1# INTD# INTB# +5V +5V TDO GND TCK -12V KEY KEY Reserved9 Reserved8 Reserved2 Reserved1

CTOR 64 Bit PCI_32_bit_3.3V FRAME# C/BE[5]# C/BE[7]# C/BE[0]# REQ64# 3.3Vaux SDONE STOP# TRDY# PAR64 TRST# AD[32] AD[34] AD[36] AD[38] AD[40] AD[42] AD[44] AD[46] AD[48] AD[50] AD[52] AD[54] AD[56] AD[58] AD[60] AD[62] AD[00] AD[02] AD[04] AD[06] AD[09] AD[11] AD[13] AD[15] AD[16] AD[18] AD[20] AD[22] AD[24] AD[26] AD[28] AD[30] IDSEL INTC# INTA# PME# SBO# GNT# +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V RST# +12V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND TMS PAR KEY KEY +5V +5V +5V +5V TDI A94 A92 A11 A9 A40 A34 A41 A17 A4 A65 A64 A52 A15 A60 A38 A93 A90 A87 A81 A78 A72 A69 A63 A56 A51 A50 A48 A42 A37 A35 A30 A24 A18 A84 A75 A66 A59 A53 A45 A39 A33 A27 A21 A16 A10 A67 A1 A26 A7 A36 A3 A19 A2 A14 A6 A91 A89 A88 A86 A85 A83 A82 A80 A79 A77 A76 A74 A73 A71 A70 A68 A58 A57 A55 A54 A49 A47 A46 A44 A32 A31 A29 A28 A25 A23 A22 A20 A62 A61 A8 A5 A43 +12V R729 +5V +3.3V 33R 3 3 PCI_INTC_N PCI_INTA_N PCI_AD32 PCI_AD34 PCI_AD36 PCI_AD38 PCI_AD40 PCI_AD42 PCI_AD44 PCI_AD46 PCI_AD48 PCI_AD50 PCI_AD52 PCI_AD54 PCI_AD56 PCI_AD58 PCI_AD60 PCI_AD62 PCI_CBE5 PCI_CBE7 PCI_REQ64_N PCI_AD0 PCI_AD2 PCI_AD4 PCI_AD6 PCI_CBE0 PCI_AD9 PCI_AD11 PCI_AD13 PCI_AD15 PCI_PAR_N PCI_STOP_N PCI_TRDY_N PCI_FRAME_N PCI_AD16 PCI_AD18 PCI_AD20 PCI_AD22 PCI_AD19 PCI_AD24 PCI_AD26 PCI_AD28 PCI_AD30 PCI_GNT_N1 PCI_RST_N PCI_PAR64 PCI_ACK64_N PCI_REQ64_N PCI_ PCI_ PCI_STOP_N PCI_IRDY_N PCI_TRDY_N PCI_FRAME_N PCI_DEVSEL_N SERR_N PERR_N PCI_M 66EN 10K, RN RN213 1 2 3

4 5 +3.3V

2 6 10 2 R1383 0R 7 8 9 +3.3V 10K R728 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Monday, September 29, 2003 Torridon - RapidIO Enabled Multi-Pr otPoesr-PIEpnin0.6 Processor - PCI Expansion Boot 1 1 Power +3.3V +5V +12V -12V ocessing System +3.3V +5V +12V -12V DGND 172 21 DGND +3.3V +5V +12V -12V of ilbride Rev C D A B

Figure A-19. Boot Processor—PCI Slot

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-20 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 +3.3V AG27 AC17 AC11 AB11 AB26 AA20 AA16 AE15 AA12 AE10 AF10 AF12 W21 W19 W13 AG7 AG3 M12 AC9 AD8 AC6 AD3 AC5 AD4 AH4 G12 AA6 AB4 AB9 AE8 AB7 AA5 AE1 H12 C11 AF4 AF2 U26 R25 U20 R19 AF7 P12 V10 Y23 P22 K10 T12 F11 T10 W5 W4 M4 M5 G9 D8 U6 C4 H4 C2 N2 U5 H3 N3 D1 K9 Y8 V7 K5 B3 E3 V8 Y7 E4 K4 T8 T3 T7 T2 L6 L7 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 OVdd42 OVdd41 OVdd40 OVdd39 OVdd38 OVdd37 OVdd36 OVdd35 OVdd34 OVdd33 OVdd32 OVdd31 OVdd30 OVdd29 OVdd28 OVdd27 OVdd26 OVdd25 OVdd24 OVdd23 OVdd22 OVdd21 OVdd20 OVdd19 OVdd18 OVdd17 OVdd16 OVdd15 OVdd14 OVdd13 OVdd12 OVdd11 OVdd10 OVdd9 OVdd8 OVdd7 OVdd6 OVdd5 OVdd4 OVdd3 OVdd2 OVdd1 U2I MPC8560 POWER GND99 GND98 GND97 GND96 GND95 GND94 GND93 GND92 GND91 GND90 GND89 GND88 GND87 GND86 GND85 GND84 GND83 GND82 GND81 GND80 GND79 GND78 GND77 GND76 GND75 GND74 GND73 GND72 GND71 GND70 GND69 GND68 GND67 GND66 GND65 GND64 GND63 GND62 GND61 GND60 GND59 GND58 GND57 GND56 GND55 GND54 GND53 GND52 GND51 GND50 GND49 GND48 GND47 GND46 GND45 GND44 GND43 GND42 GND41 GND40 4 4 K28 B27 C27 H27 M27 AF27 B26 R26 V26 AG26 G25 L25 E24 J24 F23 K23 P23 W23 C22 H22 M22 U21 B20 H20 L20 R20 C19 J19 AB19 F18 K18 W18 A17 C17 H17 N17 R17 U17 AD17 M16 P16 T16 U16 Y16 N15 R15 U15 AF15 B14 H14 M14 P14 T14 N13 R13 U13 AA13 AF13 A12 E12

Decoupling +3.3V +3.3V +3.3V C829 C822 C815 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C830 C823 C816 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C831 C824 C817 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C832 C825 C818 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C833 C826 C819

0.1uF 0.1uF 0.1uF Vdd +3.3V +3.3V +3.3V C834 C827 C820 M17 M15 M13 N16 R16 N14 R14 U14 R12 U12 P17 P15 P13 0.1uF 0.1uF 0.1uF T17 T15 T13 +3.3V +3.3V +3.3V C835 C828 C821 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 U2E 0.1uF 0.1uF 0.1uF MPC8560 +3.3V

C955 Supply CORE &PLL 3 3 10uF, 6.3V SENSE_VDD SENSE_VSS

Bulk Decoupling Decoupling AVdd3 AVdd2 AVdd1 +3.3V +3.3V 2 1C1116 C1085 + L12 AH17 AH18 AH19 220uF, Tants 10uF,6.3V Tants K12 +3.3V 2 1C1117

220uF, Tants SENSE SENSE_VDD _VSS SENS SENSE_VDD E_VSS

Decoupling Vdd Vdd C1106 C807 0.1uF 0.1uF

Vdd Vdd C1261 C1260 C1259 C1107 C808 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Vdd Vdd C320 C318 C316 C1108 C809 0.1uF 0.1uF 2.2uF 2.2uF 2.2uF Vdd Vdd C1109 C810 C321 C319 C317 0.1uF 0.1uF

2 Vdd Vdd 2.2uF 10R 2.2uF 10R 2.2uF 10R 2

C1110 C811 R272 R271 R270 0.1uF 0.1uF Vdd Vdd

C1111 C812 Vdd Vdd Vdd 0.1uF 0.1uF Vdd Vdd C1112 C813 0.1uF 0.1uF Vdd Vdd C1113 C814 0.1uF 0.1uF Vdd C954

10uF, 6.3V

Bulk Decoupling Decoupling Vdd Vdd 2 1C1114 C1084 + 220uF, Tants 10uF,6.3V Tants ae Sheet Date: Size : System Vdd C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 2 1C1115 HS1 10-THMA-01

Page Title : Page 220uF, Tants Wednesday, October 01, 2003 Torridon - RapidIO Enabled Multi-Pr 12V fan Header for Boot Processor - 2 1 HD22 1 1 oe 0.6 Power 1 Power Bead Ferrite L30 Vdd +3.3V +12V ocessing System S2 S1 DO57 DO57 Vdd +3.3V +12V DGND 2 +12V 272 22 of Vdd +3.3V +12V DGND ilbride Rev C D A B

Figure A-20. Boot Processor—Power

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B WP1_HRESET_REQ_N WP1_COP_SRES WP1_COP_HRESET_N WP1_COP_ WP1_HRESET_N WP1_SRE WP1_SYS_CLK WP1_RTC_CLK WP1_T BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N 5 5 +3.3V_BP TRST_N RST_N SET_N DGND DGND +5V +3.3V ET_N IRQ7_N IRQ6_N +3.3V_BP +5V WP1_RTC_CLK MSRCID0 WP1_HRESET_REQ_N WP1_COP_T WP1_TRST_N WP1_COP_SR WP1_COP_HRESET_N WP1_HRESET_N WP1_SRES +3.3V WP1_SYS_CLK DGND DGND BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N ET_N RST_N ESET_N WP1 - AUX Page 27 WP1 - CPM Page 31 DGND +3.3V_BP +5V WP1_SYS_CLK WP1_RTC_CLK MSRCID0 WP1_HRESET_REQ_N WP1_COP_TRST_N WP1_TRST_N WP1_COP_SRESET_N WP1_COP_HRESET_N WP1_HRESET_N WP1_SRESET_N IRQ7_N IRQ6_N DGND +3.3V BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RIO1_TXCLK_IN_N RIO1_TXCL K_IN G1_IRQ_N RIO1_TXCLK_IN_N RIO1_TXCL WP1_RXD WP1_TXD I2C_SDA I2C_SCL MDIO MDC 4 4 K_IN WP1 - RIO Page 26 RIO1_TXCLK_IN_N RIO1_TXCLK_IN WP1_RXD WP1_TXD G1GTXCLK MDC G1_IRQ_N I2C_SCL I2C_SDA MDIO G2TXD[7:2] G1TXD[7:4] WP1 - TSEC Top Page 23 WP1 - DDR SDRAM Page 20 RIO1_RFRAME_N RIO1_TFRAME_N G1GTXCLK G2TXD[7:2] G1TXD[7:4] MDIO MDC G1_IRQ_N I2C_SCL I2C_SDA RIO1_RD_N[0:7] RIO1_TD_N[0:7] RIO1_RFRAME WP1_RXD WP1_TXD RIO1_TFRAME RIO1_RCLK_N RIO1_TCLK_N RIO1_RD[0:7] RIO1_TD[0:7] RIO1_RCLK RIO1_TCLK RIO1_RCLK_N RIO1_RCLK RIO1_RFRAME_N RIO1_RFRAME RIO1_TCLK RIO1_TFRAME_N RIO1_TFRAME WP1_G1_RESET_N RIO1_TCLK_N RIO1_R RIO1_R RIO1_TD_N[0:7] RIO1_TD[0:7] +1.5VGEther +2.5VGEther D_N[0:7] D[0:7] DGND DGND +3.3V +2.5V +3.3V 3 3 WP1_G1_ +1.5 +2.5 +3.3V +2.5V +3.3V DGND DGND RIO1_RD_N[0:7] RIO1_R RIO1_RCLK_N RIO1_RCLK RIO1_RFRAME_N RIO1_RFRAME RIO1_TD_N[0:7] RIO1_TD[0:7] RIO1_TCLK_N RIO1_TCLK RIO1_TFRAME_N RIO1_TFRAME VGEther VGEther RESET_N D[0:7] +2.5V +3.3V DGND +1.5VGE +2.5VGE +3.3V DGND WP1_G1_ ther ther RESET_N WP1_RST_CONF_N ADS_HRESET_N DGND LGPL2 LGPL1 LGPL0 LALE ADS_HRESET_N BLA[27:31] LCS_N[0:2] LWE_N[2:3] +3.3V 2 2 WP1_RST_CONF_N +3.3V DGND WP1 - Page 33 WP1 - Local Bus Page 24 WP1 - PCI Page 25 - Power WP1 Page 34 WP1_RST_CONF_N DGND +3.3V ADS_HRESET_N LGPL2 LGPL1 LGPL0 LALE BLA[27:31] LCS_N[0:2] LWE_N[2:3] Config ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K LWE_N[2:3] G1GTXCLK G2TXD[7:2] G1TXD[7:4] LCS_N[0:2] +5VSB_BP BLA[27:31] +3.3V_BP MSRCID0 ATX_BP +5V_BP IRQ7_N IRQ6_N LGPL2 LGPL1 LGPL0 Page T DGND DGND Monday, September 08, 2003 +3.3V +3.3V LALE +12V +12V Torridon - RapidIO Enabled Multi-Pr +5V Vdd itle : okPoesr1-TpLvl0.6 Processor 1 - Top Level Work +3.3V_BP +3.3V +5V +5V_BP +5VSB_BP +12V +12V Vdd +3.3V DGND DGND G1GTXCLK LGPL2 LGPL1 LGPL0 LALE MSRCID0 G2TXD[7:2] G1TXD[7:4] LCS_N[0:2] LWE_N[2:3] BLA[27 ATX_BP IRQ7_N IRQ6_N 1 1 :31] ocessing System DGND +12V Vdd +3.3V ATX_BP DGND +3.3V_BP +3.3V +5V +5V_BP +5VSB_BP +12V 372 23 of ilbride Rev C D A B

Figure A-21. Work Processor 1—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-22 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B LGPL4/LGTA/LUPWAIT/LPBSE LOCAL BUS LOCAL LCS7/DMA_DDONE2 LGPL2/LOE/LSDRAS 5 5 LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LGPL3/LSDCAS LGPL0/LSDA10 LGPL1/LSDWE LSYNC_OUT LWE3/LBS3 LWE2/LBS2 LWE1/LBS1 LWE0/LBS0 U1F MPC8560 LSYNC_IN LGPL5 LBCTL LCLK2 LCLK1 LCLK0 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LCKE LCS4 LCS3 LCS2 LCS1 LCS0 LDP3 LDP2 LDP1 LDP0 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 LALE LA31 LA30 LA29 LA28 LA27 U19 T27 V20 T28 V21 V18 U28 U27 N26 N25 N24 N23 N22 P18 P19 P20 P25 P26 R18 R21 R22 R23 R24 T22 V19 W26 W22 W20 Y26 Y22 U23 V22 P21 T26 AA28 AA27 Y21 AA26 AA23 AA22 AC28 AC27 AC26 AD28 AD27 AD26 P28 P27 R28 R27 W28 W27 Y28 Y27 P24 T23 AB27 AB28 V23 V27 V28 U22 T21 T20 T19 T18 U18 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 LBCTL LALE LCLK2 BLA31 BLA30 BLA29 BLA28 BLA27 LWE_N3 LWE_N2 LWE_N1 LWE_N0 LGPL5 LGPL4 LGPL3 LGPL2 LGPL1 LGPL0 LCS_N7 LCS_N6 LCS_N2 LCS_N1 LCS_N0 TP272 TP271 LALE LCS_N[0:2] BLA[27:31] LWE_N[2:3] LGPL2 LGPL1 LGPL0 +3.3V

Decoupling 4 1K R1331 4 +3.3V C544 0.1uF +3.3V C545 0.1uF

Decoupling +3.3V C541 0.1uF +3.3V C542 0.1uF LALE LBCTL LWE_N1 LWE_N0 LBCTL LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LALE LCLK2 LGPL5 LGPL4 LGPL3 LGPL2 LGPL1 LGPL0 LBCTL LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 LALE LCS_N7 LCS_N6 LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 M1 M1 G2 G1 G2 G1 H4 H4 R2 N2 C2 R1 N1 H1 D1 C1 H3 R2 N2 C2 R1 N1 H1 D1 C1 H3 A3 A3 E2 A2 A4 P1 K1 E1 B1 A1 E2 A2 A4 P1 K1 E1 B1 A1 T4 T4 T1 F1 T3 T1 F1 T3 L2 L1 L2 L1 J3 J3 J2 J4 J1 J2 J4 J1 SN74ALVCH32973KR SN74ALVCH32973KR D8 D7 D6 D5 D4 D3 D2 D1 2TOE 1TOE 2DIR 1DIR 2A8 2A7 2A6 2A5 2A4 2A3 2A2 2A1 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 2LE 1LE 2LOE 1LOE D8 D7 D6 D5 D4 D3 D2 D1 2TOE 1TOE 2DIR 1DIR 2A8 2A7 2A6 2A5 2A4 2A3 2A2 2A1 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 2LE 1LE 2LOE 1LOE 3V3 P4 3V3 P4 3V3 P3 3V3 P3 3V3 L4 +3.3V 3V3 L4 +3.3V BUS Transceiver 3V3 L3 BUS Transceiver 3V3 L3 & Latch 3V3 F4 & Latch 3V3 F4 3V3 F3 3V3 F3 2Q8 2Q7 2Q6 2Q5 2Q4 2Q3 2Q2 2Q1 1Q8 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q1 2Q8 2Q7 2Q6 2Q5 2Q4 2Q3 2Q2 2Q1 1Q8 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q1 2B8 2B7 2B6 2B5 2B4 2B3 2B2 2B1 1B8 1B7 1B6 1B5 1B4 1B3 1B2 1B1 C4 2B8 2B7 2B6 2B5 2B4 2B3 2B2 2B1 1B8 1B7 1B6 1B5 1B4 1B3 1B2 1B1 C4 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 3V3 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 3V3 3V3 C3 3V3 C3 T6 R6 P6 N6 M6 L6 K6 J6 H6 G6 F6 E6 D6 C6 B6 A6 T6 R6 P6 N6 M6 L6 K6 J6 H6 G6 F6 E6 D6 C6 B6 A6 T5 R5 P5 N5 M5 L5 K5 J5 H5 G5 F5 E5 D5 C5 B5 A5 T5 R5 P5 N5 M5 L5 K5 J5 H5 G5 F5 E5 D5 C5 B5 A5 T2 P2 M2 K2 H2 F2 D2 B2 T2 P2 M2 K2 H2 F2 D2 B2 U66 U64 3 3 BLALE BLBCTL BLWE_N1 BLWE_N0 BLCLK2 BLGPL5 BLGPL4 BLGPL3 BLGPL2 BLGPL1 BLGPL0 BLCS_N7 BLCS_N6 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 ATX_BP BLA31 BLA30 BLA29 BLA28 BLA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 ATX_BP +5V +3.3V +12V B32 A32 B31 A31 B30 A30 B29 A29 B28 A28 B27 A27 B26 A26 B25 A25 B24 A24 B23 A23 B22 A22 B21 A21 B20 A20 B19 A19 B18 A18 B17 A17 B16 A16 B15 A15 B14 A14 B13 A13 B12 A12 B11 A11 B10 A10 CONN RCPT B9 A9 B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 P4D cPCI_J2_J5 P28 BCD AB ABCD P4A cPCI_J2_J5 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 100x2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 C32 D32 C31 D31 C30 D30 C29 D29 C28 D28 C27 D27 C26 D26 C25 D25 C24 D24 C23 D23 C22 D22 C21 D21 C20 D20 C19 D19 C18 D18 C17 D17 C16 D16 C15 D15 C14 D14 C13 D13 C12 D12 C11 D11 C10 D10 C9 D9 C8 D8 C7 D7 C6 D6 C5 D5 C4 D4 C3 D3 C2 D2 C1 D1 2 2 +3.3V_BP +3.3V_BP ADS_HRESET_N +5V_BP +5V_BP IRQ7_N BLGPL5 IRQ6_N BLGPL4 BLGPL3 BLGPL2 BLGPL1 BLGPL0 BLWE_N1 BLWE_N0 BLCLK2 BLCS_N7 BLCS_N6 LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 BLBCTL LD0 BLALE P4E cPCI_J2_J5 P4B cPCI_J2_J5 IRQ7_N IRQ6_N E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 ADS_HRESET_N E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 +3.3V_BP +3.3V_BP ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K +5V_BP +5V_BP Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr P4F cPCI_J2_J5 okPoesr1-LclBs0.6 Work Processor 1 - Local Bus P4C cPCI_J2_J5 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 +3.3V_BP +5V_BP +5VSB_BP Power C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 +3.3V +5V +12V Decoupling 1 1 +3.3V

C1083 +3.3V_BP +3.3V +3.3V_BP + DGND 10uF,6.3V Tants ocessing System +5V +5V_BP +5VSB_BP +12V +5V_BP 472 24 +5VSB_BP of +3.3V +3.3V_BP +5V +5V_BP +5VSB_BP +12V DGND ilbride ATX_BP Rev C D A B

Figure A-22. Work Processor 1—Local Bus

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B

Decoupling VREF1 +2.5V +2.5V +2.5V +2.5V TP23 TP22 TP21 TP20 TP19 TP18 C616 C611 C594 C589 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V 2 1 C617 C612 C595 C590 +

0.1uF C20 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V 1MCK_N5 1MCK5 1MCK_N4 1MCK4 1MCK_N3 1MCK_3 1MCK_N2 1MCK2 1MCK_N1 1MCK1 1MCK_N0 1MCK0 1MCKE1 1MCKE0 1MCS3_N 1MCS2_N 1MCS1_N 1MCS0_N 1MCAS_N 1MRAS_N 1MWE_N 1MBA1 1MBA0 1MA14 1MA13 1MA12 1MA11 1MA10 1MA9 1MA8 1MA7 1MA6 1MA5 1MA4 1MA3 1MA2 1MA1 1MA0 1MDQS8 1MDQS7 1MDQS6 1MDQS5 1MDQS4 1MDQS3 1MDQS2 1MDQS1 1MDQS0 1MDM8 1MDM7 1MDM6 1MDM5 1MDM4 1MDM3 1MDM2 1MDM1 1MDM0 1MECC7 1MECC6 1MECC5 1MECC4 1MECC3 1MECC2 1MECC1 1MECC0

VTT1_Sence C618 C613 C596 C591 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V C619 C614 C597 C592 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V C620 C615 C598 C593 4 3 2 1

5 0.1uF 0.1uF 0.1uF 0.1uF 5 VREF VSENSE GND NC U8 LP2995 R1040 R1038 R1036 R1034 R1032 R1030 R1028 R1026 R1024 R1022 R1020 R1018 R1016 R1014 R1012 R1010 R1008 R1006 R1004 R1002 R1000 R998 R996 R994 R992 R990 R988 R986 R984 R982 R980 R978 R976 R974 R972 R970 R968 R966 R964 R962 R960 R958 R956 R954 R952 R950 R948 R946 R944 R942 R940 R938 R936 R934 R932 R930 R928 R926 R924 R922 R920 R918 R916 R914 R912 LP2995

Decoupling Decoupling VREF1 +2.5V VDDQ 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R C987 C1076 Place Near Pin N27 + AVIN PVIN

VTT 0.1uF

10uF,6.3V Tants VREF1 Decoupling 1MSYNC_IN 1MSYNC_OUT VREF1 VREF1 5 6 7 8

C988 VREF1 0.01uF C986 1NCK5 1NCK4 1NCK3 1NCK2 1NCK1 1NCK0 1CKE1 1CKE0 1CAS_N 1RAS_N 1BA1 1BA0 1A14 1A13 1A12 1A11 1A10 1A9 1A8 1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0 1DQS8 1DQS7 1DQS6 1DQS5 1DQS4 1DQS3 1DQS2 1DQS1 1DQS0 1DM8 1DM7 1DM6 1DM5 1DM4 1DM3 1DM2 1DM1 1DM0 1ECC7 1ECC6 1ECC5 1ECC4 1ECC3 1ECC2 1ECC1 1ECC0 0.1uF 1CK5 1CK4 1CK3 1CK2 1CK1 1CK0 1CS3_N 1CS2_N 1CS1_N 1CS0_N 1WE_N

2 1 M28 M21 M19 M20 G27 G16 G24 G14 G19 N27 N28 D20 H25 H15 H16 D17 D27 H23 C23 N19 C20 C13 H18 D25 H28 C21 N20 47uF, Tants K14 E20 B15 A15 E28 E26 B19 B18 B25 K19 B24 A23 K21 B21 A22 B13 E16 E18 A19 A21 E19 F27 F28 F20 F17 F21 F14 F16 F24 L14 L26 L21 L24 L19 J20 J15 J16 J13 J14 J25 C18 Bulk Decoupling +2.5V +2.5V MVREF(GVdd/2) MSYNC_IN MSYNC_OUT MCK5- MCK5 MCK4- MCK4 MCK3- MCK3 MCK2- MCK2 MCK1- MCK1 MCK0- MCK0 MCKE1 MCKE0 MCS3- MCS2- MCS1- MCS0- MCAS- MRAS- MWE- MBA1 MBA0 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MDQS8 MDQS7 MDQS6 MDQS5 MDQS4 MDQS3 MDQS2 MDQS1 MDQS0 MDM8 MDM7 MDM6 MDM5 MDM4 MDM3 MDM2 MDM1 MDM0 MECC7 MECC6 MECC5 MECC4 MECC3 MECC2 MECC1 MECC0 U1B 2 1C1169 MPC8560

220uF, Tants

2 1 +2.5V 220uF, Tants

C19 VTT1 2 1C1170 SDRAM DDR

220uF, Tants 1.25V @ GVdd41 GVdd40 GVdd39 GVdd38 GVdd37 GVdd36 GVdd35 GVdd34 GVdd33 GVdd32 GVdd31 GVdd30 GVdd29 GVdd28 GVdd27 GVdd26 GVdd25 GVdd24 GVdd23 GVdd22 GVdd21 GVdd20 GVdd19 GVdd18 GVdd17 GVdd16 GVdd15 GVdd14 GVdd13 GVdd12 GVdd11 GVdd10 MDQ63 MDQ62 MDQ61 MDQ60 MDQ59 MDQ58 MDQ57 MDQ56 MDQ55 MDQ54 MDQ53 MDQ52 MDQ51 MDQ50 MDQ49 MDQ48 MDQ47 MDQ46 MDQ45 MDQ44 MDQ43 MDQ42 MDQ41 MDQ40 MDQ39 MDQ38 MDQ37 MDQ36 MDQ35 MDQ34 MDQ33 MDQ32 MDQ31 MDQ30 MDQ29 MDQ28 MDQ27 MDQ26 MDQ25 MDQ24 MDQ23 MDQ22 MDQ21 MDQ20 MDQ19 MDQ18 MDQ17 MDQ16 MDQ15 MDQ14 MDQ13 MDQ12 MDQ11 MDQ10 GVdd9 GVdd8 GVdd7 GVdd6 GVdd5 GVdd4 GVdd3 GVdd2 GVdd1 MDQ9 MDQ8 MDQ7 MDQ6 MDQ5 MDQ4 MDQ3 MDQ2 MDQ1 MDQ0 1.5A J28 K22 K26 K27 M23 M24 K24 L22 L27 M26 A28 B28 C28 D28 G28 L28 A27 J27 A26 A25 F25 K25 M25 D24 H24 G23 L23 B22 E22 J22 D21 N21 A20 G20 K20 D19 F19 H19 G18 B17 E17 J17 B12 A13 H13 F13 A11 D12 E13 D13 D14 E14 D15 C15 K13 C14 E15 G15 L15 A16 L16 G17 B16 C16 K16 K17 A18 C18 L18 M18 L17 D18 J18 N18 E21 H21 D22 G22 G21 J21 F22 B23 D23 A24 C25 D26 E23 C24 E25 C26 G26 H26 J23 J26 E27 F26 D16 F15 K15 A14 G13 L13 C12 F12 J12 4 +2.5V 4 1DQ63 1DQ62 1DQ61 1DQ60 1DQ59 1DQ58 1DQ57 1DQ56 1DQ55 1DQ54 1DQ53 1DQ52 1DQ51 1DQ50 1DQ49 1DQ48 1DQ47 1DQ46 1DQ45 1DQ44 1DQ43 1DQ42 1DQ41 1DQ40 1DQ39 1DQ38 1DQ37 1DQ36 1DQ35 1DQ34 1DQ33 1DQ32 1DQ31 1DQ30 1DQ29 1DQ28 1DQ27 1DQ26 1DQ25 1DQ24 1DQ23 1DQ22 1DQ21 1DQ20 1DQ19 1DQ18 1DQ17 1DQ16 1DQ15 1DQ14 1DQ13 1DQ12 1DQ11 1DQ10 1DQ9 1DQ8 1DQ7 1DQ6 1DQ5 1DQ4 1DQ3 1DQ2 1DQ1 1DQ0

Decoupling +2.5V +2.5V +2.5V R1039 R1037 R1035 R1033 R1031 R1029 R1027 R1025 R1023 R1021 R1019 R1017 R1015 R1013 R1011 R1009 R1007 R1005 R1003 R1001 R999 R997 R995 R993 R991 R989 R987 R985 R983 R981 R979 R977 R975 R973 R971 R969 R967 R965 R963 R961 R959 R957 R955 R953 R951 R949 R947 R945 R943 R941 R939 R937 R935 R933 R931 R929 R927 R925 R923 R921 R919 R917 R915 R913 C1225 C1218 C1211 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1226 C1219 C1212 0.1uF 0.1uF 0.1uF 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R +2.5V +2.5V +2.5V C1227 C1220 C1213 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1228 C1221 C1214 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1229 C1222 C1215 0.1uF 0.1uF 0.1uF 1MDQ63 1MDQ62 1MDQ61 1MDQ60 1MDQ59 1MDQ58 1MDQ57 1MDQ56 1MDQ55 1MDQ54 1MDQ53 1MDQ52 1MDQ51 1MDQ50 1MDQ49 1MDQ48 1MDQ47 1MDQ46 1MDQ45 1MDQ44 1MDQ43 1MDQ42 1MDQ41 1MDQ40 1MDQ39 1MDQ38 1MDQ37 1MDQ36 1MDQ35 1MDQ34 1MDQ33 1MDQ32 1MDQ31 1MDQ30 1MDQ29 1MDQ28 1MDQ27 1MDQ26 1MDQ25 1MDQ24 1MDQ23 1MDQ22 1MDQ21 1MDQ20 1MDQ19 1MDQ18 1MDQ17 1MDQ16 1MDQ15 1MDQ14 1MDQ13 1MDQ12 1MDQ11 1MDQ10 1MDQ9 1MDQ8 1MDQ7 1MDQ6 1MDQ5 1MDQ4 1MDQ3 1MDQ2 1MDQ1 1MDQ0 +2.5V +2.5V +2.5V C1230 C1223 C1216 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1231 C1224 C1217 0.1uF 0.1uF 0.1uF 3 I2C_SDA Place Near Pin 1 3 I2C_SCL Decoupling VREF1 C984 0.1uF VREF1 C985 0.01uF +3.3V VddSPD I2C_SCL I2C_SDA 1MDQ59 1MDQ58 1MDQS7 1MDQ57 1MDQ56 1MDQ51 1MDQ50 1MDQS6 1MDQ49 1MDQ48 1MDQ43 1MDQ42 1MDQS5 1MDQ41 1MDQ40 1MDQ35 1MDQ34 1MDQS4 1MDQ33 1MDQ32 1MCS0_N 1MWE_N 1MBA0 1MA10 1MA1 1MA3 1MA5 1MA7 1MA9 1MA12 1MCKE1 1MCK_N0 1MCK0 1MECC3 1MECC2 1MDQS8 1MECC1 1MECC0 1MDQ27 1MDQ26 1MDQS3 1MDQ25 1MDQ24 1MDQ19 1MDQ18 1MDQS2 1MDQ17 1MDQ16 1MCK_N2 1MCK2 1MDQ11 1MDQ10 1MDQS1 1MDQ9 1MDQ8 1MDQ3 1MDQ2 1MDQS0 1MDQ1 1MDQ0 VREF1 +2.5V 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11

9 7 5 3 1 Decoupling Decoupling P17 VTT1 VTT1 DDR SODIMM DDR C1035 C1027 0.1uF 0.1uF VTT1 VTT1 C1036 C1028

200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0.1uF 0.1uF VTT1 VTT1 C1037 C1029 0.1uF 0.1uF +2.5V VTT1 VTT1 C1038 C1030 0.1uF 0.1uF VTT1 VTT1 1MDQ63 1MDQ62 1MDM7 1MDQ61 1MDQ60 1MDQ55 1MDQ54 1MDM6 1MDQ53 1MDQ52 1MCK1 1MCK_N1 1MDQ47 1MDQ46 1MDM5 1MDQ45 1MDQ44 1MDQ39 1MDQ38 1MDM4 1MDQ37 1MDQ36 1MCS1_N 1MCAS_N 1MRAS_N 1MBA1 1MA0 1MA2 1MA4 1MA6 1MA8 1MA11 1MCKE0 1MECC7 1MECC6 1MDM8 1MECC5 1MECC4 1MDQ31 1MDQ30 1MDM3 1MDQ29 1MDQ28 1MDQ23 1MDQ22 1MDM2 1MDQ21 1MDQ20 1MDQ15 1MDQ14 1MDM1 1MDQ13 1MDQ12 1MDQ7 1MDQ6 1MDM0 1MDQ5 1MDQ4 VREF1 C1039 C1031 0.1uF 0.1uF VTT1 VTT1 Do Not Fit

2 C1040 C1032 2 0.1uF 0.1uF

R65 R62 VTT1 VTT1

4K7 10K +3.3V C1041 C1033 R66 R63 0.1uF 0.1uF

4K7 10K VTT1 VTT1 R67 R64 C1042 C1034 4K7 10K + 0.1uF 10uF,6.3V Tants MT18VDDT6472 SODIMM2 199(200) 41(42) 39(40) 1(2) 200-pin DDR SDRAM SODIMM 1MA1 1MA0 1MA3 1MA2 1MA5 1MA4 1MA7 1MA6 1MA9 1MA8 1MA12 1MA11 1MCKE1 1MCKE0 1MECC3 1MECC7 1MECC2 1MECC6 1MDQS8 1MDM8 1MECC1 1MECC5 1MECC0 1MECC4 1MDQ27 1MDQ31 1MDQ26 1MDQ30 1MDQS3 1MDM3 1MDQ25 1MDQ29 1MDQ24 1MDQ28 1MDQ19 1MDQ23 1MDQ18 1MDQ22 1MDQS2 1MDM2 1MDQ17 1MDQ21 1MDQ16 1MDQ20 1MDQ11 1MDQ15 1MDQ10 1MDQ14 1MDQS1 1MDM1 1MDQ9 1MDQ13 1MDQ8 1MDQ12 1MDQ3 1MDQ7 1MDQ2 1MDQ6 1MDQS0 1MDM0 1MDQ1 1MDQ5 1MDQ0 1MDQ4

Decoupling Decoupling VTT1

VTT1 C599 C989 0.1uF 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 ae Sheet Date: Size : System VTT1 C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 0.1uF

VTT1 C600 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN C990 0.1uF Page Title : Page VTT1 RN228 RN226

0.1uF RN60 RN58 RN52 RN48 RN44 RN38 Wednesday, October 01, 2003 VTT1 Torridon - RapidIO Enabled Multi-Pr C601 C991 0.1uF 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16

0.1uF VTT1

VTT1 C602 VTT1

Work Pr C992 0.1uF + VTT1

10uF,6.3V Tants C603 VTT1_Sence

0.1uF Tap VTT Sence from middle cso D DA 0.6 ocessor 1 - DDR SDRAM VTT1 C604 0.1uF 1MA14 1MA13 1MCS3_N 1MCS2_N 1MDQ59 1MDQ63 1MDQ58 1MDQ62 1MDQS7 1MDM7 1MDQ57 1MDQ61 1MDQ56 1MDQ60 1MDQ51 1MDQ55 1MDQ50 1MDQ54 1MDQS6 1MDM6 1MDQ49 1MDQ53 1MDQ48 1MDQ52 1MDQ43 1MDQ47 1MDQ42 1MDQ46 1MDQS5 1MDM5 1MDQ41 1MDQ45 1MDQ40 1MDQ44 1MDQ35 1MDQ39 1MDQ34 1MDQ38 1MDQS4 1MDM4 1MDQ33 1MDQ37 1MDQ32 1MDQ36 1MCS0_N 1MCS1_N 1MWE_N 1MCAS_N 1MBA0 1MRAS_N 1MA10 1MBA1 1 VTT1 1 C605 0.1uF VTT1

+2.5V +3.3V Power C606 ocessing System 0.1uF VTT1

C607 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 +2.5V +3.3V DGND 27R, RN 0.1uF 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN VTT1 572 25

C608 RN227 RN61 RN59 RN53 RN49 RN45 RN39 0.1uF VTT1 of

C609 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 ilbride +2.5V +3.3V DGND

0.1uF VTT1 VTT1 C610

Rev 0.1uF C D A B

Figure A-23. Work Processor 1—DDR SDRAM

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-24 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 RIO1_TXCLK_ RIO1_TXC IN_N LK_IN RIO1_TXCLK_IN_N RIO1_TXCL K_IN AF25 AF24 4 4 MPC8560 RIO_TXCLK_IN- RIO_TXCLK_IN U1C RIO_RFRAME- RIO_TFRAME- RIO_RFRAME RIO_TFRAME RIO_RCLK- RIO_TCLK- RIO_RCLK RIO_TCLK RIO_RD7- RIO_RD6- RIO_RD5- RIO_RD4- RIO_RD3- RIO_RD2- RIO_RD1- RIO_RD0- RIO_TD7- RIO_TD6- RIO_TD5- RIO_TD4- RIO_TD3- RIO_TD2- RIO_TD1- RIO_TD0- RIO_RD7 RIO_RD6 RIO_RD5 RIO_RD4 RIO_RD3 RIO_RD2 RIO_RD1 RIO_RD0 RIO_TD7 RIO_TD6 RIO_TD5 RIO_TD4 RIO_TD3 RIO_TD2 RIO_TD1 RIO_TD0 Y25 AD23 AC22 AE22 AD21 AE20 AD19 AC18 AE18 AE25 AD25 AC25 AB25 AA25 W25 V25 U25 T25 AE26 AE27 Y24 AC23 AE23 AD22 AC21 AD20 AC19 AE19 AD18 AE24 AE21 AD24 AC24 AB24 AA24 W24 V24 U24 T24 AC20 RIO1_RD_N7 RIO1_RD7 RIO1_RD_N6 RIO1_RD6 RIO1_RD_N5 RIO1_RD5 RIO1_RD_N4 RIO1_RD4 RIO1_RD_N3 RIO1_RD3 RIO1_RD_N2 RIO1_RD2 RIO1_RD_N1 RIO1_RD1 RIO1_RD_N0 RIO1_RD0 RIO1_RFRAME_N RIO1_RFRAME RIO1_RCLK_N RIO1_RCLK RIO1_TFRAME_N RIO1_TFRAME RIO1_TCLK RIO1_TD_N7 RIO1_TD7 RIO1_TD_N6 RIO1_TD6 RIO1_TD_N5 RIO1_TD5 RIO1_TD_N4 RIO1_TD4 RIO1_TD_N3 RIO1_TD3 RIO1_TD_N2 RIO1_TD2 RIO1_TD_N1 RIO1_TD1 RIO1_TD_N0 RIO1_TD0 RIO1_TCLK_N 3 3 RIO1_RFRAME_N RIO1_RFRAME RIO1_RCLK_N RIO1_RCLK RIO1_ RIO1_R RD[0:7] D_N[0:7] RIO1_TFRAME_N RIO1_TF RIO1_TCLK RIO1_TCLK_N RIO1_TD7 RIO1_TD6 RIO1_TD5 RIO1_TD4 RIO1_TD3 RIO1_TD2 RIO1_TD1 RIO1_TD0 RIO1_TD_N7 RIO1_TD_N6 RIO1_TD_N5 RIO1_TD_N4 RIO1_TD_N3 RIO1_TD_N2 RIO1_TD_N1 RIO1_TD_N0 RIO1_RFRAME_N RIO1_RCLK_N RIO1_RFRAME RIO1_RCLK RAME RIO1_RD_N7 RIO1_RD_N6 RIO1_RD_N5 RIO1_RD_N4 RIO1_RD_N3 RIO1_RD_N2 RIO1_RD_N1 RIO1_RD_N0 RIO1_RD7 RIO1_RD6 RIO1_RD5 RIO1_RD4 RIO1_RD3 RIO1_RD2 RIO1_RD1 RIO1_RD0 RIO1_TFRAME_N RIO1_TFRAME RIO1_TCLK_N RIO1_TCLK RIO1_TD[0:7] RIO1_TD_N[0:7] 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Work rcso aiI nefc 0.6 Processor 1 - RapidIO Interface 1 1 ocessing System 672 26 of ilbride Rev C D A B

Figure A-24. Work Processor 1—RapidIO Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 4 4 AG10 AG13 AD13 AH10 AD10 AC10 AH13 AD11 AC12 AE13 AA11 AB10 W11 W14 AG6 AG5 AG4 AH5 AH8 AE6 AE5 AE4 AA9 AF6 AF3 AF5 Y11 V11 Y14 V14 PCI_GNT4 PCI_GNT3 PCI_GNT2 PCI_GNT1 PCI_GNT0 PCI_REQ4 PCI_REQ3 PCI_REQ2 PCI_REQ1 PCI_REQ0 PCI_SERR PCI_PERR PCI_ACK64 PCI_REQ64 PCI_IDSEL PCI_DEVSEL PCI_STOP PCI_IRDY PCI_TRDY PCI_FRAME PCI_PAR64 PCI_PAR PCI_C_BE7 PCI_C_BE6 PCI_C_BE5 PCI_C_BE4 PCI_C_BE3 PCI_C_BE2 PCI_C_BE1 PCI_C_BE0 U1A MPC8560 PCIX/PCI PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 3 3 AA14 AB14 AC14 AD14 AE14 AF14 AG14 AH14 V15 W15 Y15 AA15 AB15 AC15 AD15 AG15 AH15 V16 W16 AB16 AC16 AD16 AE16 AF16 V17 W17 Y17 AA17 AB17 AE17 AF17 AF18 AH6 AD7 AE7 AH7 AB8 AC8 AF8 AG8 AD9 AE9 AF9 AG9 AH9 W10 Y10 AA10 AE11 AF11 AG11 AH11 V12 W12 Y12 AB12 AD12 AE12 AG12 AH12 V13 Y13 AB13 AC13 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Pro esr1-PIItrae0.6 cessor 1 - PCI Interface 1 1 ocessing System 772 27 of ilbride Rev C D A B

Figure A-25. Work Processor 1—PCI Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-26 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 DGND +3.3V 4 4 DGND +3.3V WP1 - TSEC Page 29 DGND +3.3V G1RXD[7:0] G1GTXCLK G1TXD[7:0] G2TXD[7:2] G1RXCLK MGTX125 G1TXCLK G1RXER G1RXDV G1TXER G1TXEN G1CRS G1COL WP1_G1_ G2TXD[7:2] G1TXD[7:4] G1_IRQ_N RESET_N MDC MDIO 3 3 G1GTXCLK G1TXD[7:4] G2TXD[7:2] MGTX125 MDC WP1_G1_ G1_IRQ_N G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN MDIO G1COL G1RX G1TXD[7:0] D[7:0] RESET_N WP1 - Page 30 MDC MDIO WP1_G1_RESET_N G1_IRQ_N MGTX125 G1COL G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN G1RXD[7:0] G1TXD[7:0] TSEC - PHY +1.5VGEther +2.5VGEther DGND +3.3V +1.5VGEther +2.5VGEther +3.3V DGND 2 2 DGND +1.5VGEther +2.5VGEther +3.3V ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Monday, September 08, 2003 Torridon - RapidIO Enabled Multi-Pr Work Processor 1 - GigaByte Ethernet Interface Top Work 1 1 ocessing System 872 28 of ilbride Rev 0.6 C D A B

Figure A-26. Work Processor 1—GigaByte Ethernet Interface—Top

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 +3.3V

Decoupling H10 C5 E7 A4 +3.3V C630 0.1uF LVdd4 LVdd3 LVdd2 LVdd1 +3.3V Clocking GbE TSEC2 TSEC1

C631 U1G 0.1uF +3.3V TSEC2_GTX_CLK TSEC1_GTX_CLK EC_GTX_CLK125

C632 MPC8560 TSEC2_RX_CLK TSEC1_RX_CLK TSEC2_TX_CLK TSEC1_TX_CLK TSEC2_RX_ER TSEC2_RX_DV TSEC1_RX_ER TSEC1_RX_DV

0.1uF TSEC2_TX_ER TSEC2_TX_EN TSEC1_TX_ER TSEC1_TX_EN TSEC2_RXD7 TSEC2_RXD6 TSEC2_RXD5 TSEC2_RXD4 TSEC2_RXD3 TSEC2_RXD2 TSEC2_RXD1 TSEC2_RXD0 TSEC1_RXD7 TSEC1_RXD6 TSEC1_RXD5 TSEC1_RXD4 TSEC1_RXD3 TSEC1_RXD2 TSEC1_RXD1 TSEC1_RXD0 TSEC2_TXD7 TSEC2_TXD6 TSEC2_TXD5 TSEC2_TXD4 TSEC2_TXD3 TSEC2_TXD2 TSEC2_TXD1 TSEC2_TXD0 TSEC1_TXD7 TSEC1_TXD6 TSEC1_TXD5 TSEC1_TXD4 TSEC1_TXD3 TSEC1_TXD2 TSEC1_TXD1 TSEC1_TXD0 +3.3V TSEC2_CRS TSEC1_CRS TSEC2_COL TSEC1_COL C633 0.1uF C10 B6 F8 G7 E2 D10 C6 D11 B11 B8 C8 E10 D6 A8 H8 E5 D2 B10 A10 J10 K11 J11 H11 G11 E11 A6 F7 D7 C7 B7 A7 G8 E8 F9 E9 C9 B9 A9 H9 G10 F10 D4 B4 D3 D5 B5 A5 F6 E6 D9 C3 R371 R370 R369 8 7 6 5 4 3 2 1 RN153 22R, RN G1RXCLK G1RXER G1RXDV MGTX125 G2TXD7 G2TXD6 G2TXD5 G2TXD4 G2TXD3 G2TXD2 G1CRS G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 G1COL 22R 0.1W 22R 0.1W 22R 0.1W 22R 9 10 11 12 13 14 15 16 4 4 G1GTXCLK G1TXCLK G1TXER G1TXEN G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0 G1RX D[7:0] G2TXD[7:2] G1COL G1CRS G1RXCLK G1RXER G1RXDV MGTX125 G1GTXCLK G1TXCLK G1TXER G1TXEN G1TXD[7:0] MGTX125 220R R372 +3.3V

330RR373

100pF C427 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G1RXD[7:0] 8 7 6 5 4 3 2 1 3 RN 330R, RN156 3 8 7 6 5 4 3 2 1 RN154 9 10 11 12 13 14 15 16 2R RN 220R, 9 10 11 12 13 14 15 16 100pF, CN 4 3 2 1 4 3 2 1 +3.3V 100pF, CN CN11 5 6 7 8 5 6 7 8 CN9 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 8 7 6 5 4 3 2 1 3R RN 330R, RN157 8 7 6 5 4 3 2 1 RN155 G1TXD[7:0] 9 10 11 12 13 14 15 16 2R RN 220R, 9 10 11 12 13 14 15 16 100pF, CN 100pF, 4 3 2 1 4 3 2 1 +3.3V 100pF, CN 2 2 CN12 G1RXCLK G1GTXCLK G1TXEN 5 6 7 8 5 6 7 8 CN10 220R R543 220R R537 220R R531 +3.3V +3.3V +3.3V

330R R544 330R R538 330R R532

100pF C857 100pF C854 100pF C851 G1CRS G1RXDV G1TXER 220R R545 220R R539 220R R533 +3.3V +3.3V +3.3V ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 330R R546 330R R540 330R R534

100pF C858 100pF C855 100pF C852 Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr G1RXER G1TXCLK G1COL Work 220R R547 220R R541 220R R535 Power rcso iayeEhre nefc 0.6 Processor 1 - GigaByte Ethernet Interface +3.3V +3.3V +3.3V +3.3V

330R R548 330R R542 330R R536 1 1 DGND 100pF C859 100pF C856 100pF C853 +3.3V ocessing System 972 29 DGND +3.3V of ilbride Rev C D A B

Figure A-27. Work Processor 1—GigaByte Ethernet Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-28 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B MDIO MDC WP1_G1_ 5 5 RESET_N MDC MDIO 1K R1332 +3.3V +3.3V R1302

10K 1K R1333 G1RXD[7:0] G1TXD[7:0] G1GTXCLK MGTX125 G1RXCLK G1_IRQ_N WP1_G1_ G1TXCLK G1TXER G1TXEN G1CRS G1COL G1RXER G1RXDV C463 C462 RESET_N +1.5VG 18pF 18pF Ether G1TXCLK G1TXER G1TXEN G1RXCLK G1RXER G1RXDV

3 2 G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0 G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 0.01uF C449 MGTX125 G1CRS G1GTXCLK G1_IRQ_N G1COL

4 1 0.1uF C454

R395 R393 R392 R386 R385 R384 0.01uF C450 8 7 6 5 4 3 2 1 25MHz Y9 22R, RN 0.1uF C455

0.01uF C451 RN163 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R R390 0.1uF C456 GROUND Separate 9 10 11 12 13 14 15 16 22R 0.1W 22R 4 4 0R 0.01uF C452 R396 0.1uF C457 0.01uF C429 U60

mill trace must be 50 0.1uF C434 G2 G1 H2 H1 D8 C9 C8 D9 K2 E9 K3 A1 E1 B2 B4 A3 A2 A4 A5 B3 B9 A9 B8 A8 B7 A7 B6 B5 A6 E8 F7 F2 F1 J2 J1 +3.3V 0.01uF C430 VSSC XTAL1 XTAL2 SEL_2_5V RESET COMA TXD_7 TXD_6 TXD_5 TXD_4 TXD_3 TXD_2 TXD_1 TXD_0 TX_CLK TX_ER TX_EN CRS COL GTX_CLK CLK125 RXD_7 RXD_6 RXD_5 RXD_4 RXD_3 RXD_2 RXD_1 RXD_0 RX_CLK RX_ER RX_DV MDIO MDC INT +3.3V 0.1uF C435

0.01uF C431 LED_YELLOW R1334 K7 0R R1335 CONFIG_6 0.1uF C436 2 1 J7 CONFIG_5

0R R1336 L9 1.5V E3 LD22 0R R1337 CONFIG_4 DVDDL 0.01uF C432 K9 CONFIG_3 DVDDL H3

330R 0R R1338 K8 CONFIG_2 DVDDL D7

R402 0R R1339 J9 G7 0.1uF C437 0R R1340 CONFIG_1 DVDDL J8 CONFIG_0

0R 0.01uF C433 +2.5VGEther

H9 3.3V 2.5V M3 LED_TX AVDDL 0.1uF C438 F8 LED_LINK10 AVDDL L2 G8 B1

LED_LINK1000 AVDDL 3PIN_FERRITE H8 LED_RX AVDDL M7 0.1uF C453 3 G9 LED_DPLX AVDDL M8

330R F9 88E1011S LED_LINK100 G1AVDDH L19 R405 AVDDH N5 M6 49R9 2 HDAC_N R379 49R9 HDAC_P M5 TP143 M4 R380 1 LED_YELLOW TP144 CTRL25 TP141 E2 CTRL_15 DVDDH G3 2 1 M2 F3 2K49 R398 RSET DVDDH TP142 0.01uF C439

LD24 330R M9 TDI VDDO H7

R403 0.1uF C444 M1 TRST VDDO J3 R399 4K7 L1 TMS VDDO C5

10K 0.01uF C440 L8 TDO VDDO C6 K1 E7 LED_RED TCK VDDO 0.1uF C445 2 1 R397 3 0.01uF C441 3 G6 DGND DGND G4

LD25 330R J6 DGND DGND D6 R401 +3.3V 0.1uF C446 H4 DGND DGND L7 F4 L6 DGND DGND 0.01uF C442 G5 DGND DGND K6 E4 L5 LED_YELLOW DGND DGND 0.1uF C447 D5 DGND DGND K5 2 1 D4 DGND DGND J5 C4 L4 0.01uF C443 LD20 DGND DGND C7 DGND DGND E6

0.1uF C448 +3.3V E5 DGND DGND L3 H6 DGND DGND J4 F6 DGND DGND K4 H5 DGND DGND F5 SOUT_M SOUT_P SCLK_M SCLK_P MDI3_M MDI2_M MDI1_M MDI0_M MDI3_P MDI2_P MDI1_P MDI0_P SIN_M SIN_P CONFIG6 SEL_BDT INT_POL 75/50 OHMCONFIG6 SEL_BDT INT_POL 75/50 CONFIG5 DIS_FC DIS_SLEEP HWCFG_ CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_ CONFIG3 ANEG[0] ENA_XC D CONFIG2 ANEG[3] ANEG[2] A CONFIG1 ENA_PAUSE PHYADR[4] PHY OFG 0 1 1 0 CONFIG6 0 0 CONFIG5 1 0 CONFIG4 1 0 CONFIG3 0 CONFIG2 1 CONFIG1 0 CONFIG0 0 Bit[2] Bit[1] Bit[0] Pin CONFIG0 PHYADR[2] PHYADR[1] PHY Bit[2] Bit[1] Bit[0] Pin D2 C3 D1 C2 N8 N6 N3 N1 D3 C1 N9 N7 N4 N2

C4610.01uF C4600.01uF C4590.01uF C4580.01uF R394 49R9 49R9 R389 49R9 49R9 R387 49R9 49R9 R382 49R9 49R9 R391 R388 R383 R381 2 CONFIG6 VSS CONFIG5 VDDO CONFIG4 VDDO CONFIG3 VSS CONFIG2 LED_LINK10 CONFIG1 VSS CONFIG0 VSS Pin Setting 2 IS_125 NEG[1] ADR[3] ADR[0] WP1_PH1_M3 WP1_ WP1_PH1_M2 WP1_ WP1_PH1_M1 WP1_ WP1_PH1_M0 WP1_ MODE[3] MODE[0] PH1_P3 PH1_P2 PH1_P1 PH1_P0 VSS 0 0 VSS 0 0 0 LED_TX 0 1 1 LED_RX 0 0 1LED_DUPLEX 0 1 0LED_LINK1000 1 0 0LED_LINK100 1 1 1LED_LINK10 1 0 1 VDD0 1 1 Bit[2:0] Pin D4C D2C 10C 1C 2C 4C 3C 6C 5C 8C 7C 9C RJG5-7G05 P5C 1:1 1:1 1:1 1:1 ae Sheet Date: Size : System LED flashing => Transmitting or Rece LED off => Link Down LED on => Link Up LED_TX is used as a global activity indica NOTE: When PHY register 24.2:0='111', LED off => Link Down LED on => Link Up LED_LINK1000 is used as a global link indica NOTE: When PHY register 24.4:3='01', C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Tuesday, September 30, Torridon - RapidIO Enabled Multi-Pr D3C D1C +1.5V +2.5V Work ProcessorWork 1 - +3.3V Power GEther GEther +3.3V 2003 1 1 +1.5VGEther +2.5VGEther +3.3V DGND iayeEhre nefc H 0.6 GigaByte Ethernet Interface - PHY iving ocessing System tor. tor. 072 30 +1.5VGEther +2.5VGEther +3.3V DGND of ilbride Rev C D A B

Figure A-28. Work Processor 1—GigaByte Ethernet Interface—PHY

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 UTOPIA_TxEnb_N UTOPI UTOPIA_RxEnb_N UTOPIA_RxSOC UTOPIA_Rx UTOPIA_TXD8 UTOPIA_TXD9 UTOPIA_TXD10 UTOPIA_TXD11 UTOPIA_TXD12 UTOPIA_TXD13 UTOPIA_TXD14 UTOPIA_TXD15 UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 UTOPIA_TxSOC A_TxClav RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD9 RXD8 Clav 5 5 M10 N11 N10 P10 P11 L11 L10 M1 M2 M3 M6 M7 M8 M9 R7 R6 R5 R4 R3 R2 R1 N9 N8 N7 N6 N5 N4 N1 H2 H1 P1 P2 P3 P4 P5 P6 P7 P8 P9 K1 K2 K3 K6 K7 K8 L9 L8 L5 L4 L3 L2 L1 J8 J7 J6 J5 J4 J3 J2 J1 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17/FEC_RX_DV PB16/FEC_RX_ER PB15/FEC_TX_ER PB14/FEC_TX_EN PB13/FEC_COL PB12/FEC_CRS PB11/FEC_RXD3 PB10/FEC_RXD2 PB9/FEC_RXD1 PB8/FEC_RXD0 PB7/FEC_TXD0 PB6/FEC_TXD1 PB5/FEC_TXD2 PB4/FEC_TXD3 PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 U1H MPC8560

Alt. DUART CPM Alt. 10/100 Eth.Alt. DUART PD30/UART_SOUT0 PD27/UART_SOUT1 PC17/FEC_RX_CLK PC18/FEC_TX_CLK PD29/UART_RTS0 PD26/UART_RTS1 PC15/UART_CTS0 PC13/UART_CTS1

PD31/UART_SIN0 PD28/UART_SIN1 Alt. 10/100 Eth. PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PC31 PC30 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC16 PC14 PC12 PC11 PC10 PD9 PD8 PD7 PD6 PD5 PD4 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 V6 AE2 AD5 V9 AE3 AD2 AC1 AC2 AC3 AC4 AC7 AB6 AB5 AB3 AB2 AB1 AA1 AA2 AA3 AA4 AA7 AA8 Y9 W9 W8 W7 W6 W3 W2 W1 V1 V2 V3 V4 V5 U10 U8 U4 U3 U2 Y6 Y5 Y4 Y3 Y2 Y1 U1 T1 T4 T5 T6 T9 R11 R10 R9 R8 AD6 AD1 U9 U7 WP1_RXD WP1_TXD UTOPI UTOPIA_TXD7 UTOPIA_ UTOPIA_ UTOPIA_TXD6 UTOPIA_ UTOPIA_ UTOPIA_TXD5 UTOPIA_ UTOPIA_ UTOPIA_TxADD4 UTOPI UTOPIA_RxPrty UTOPI UTOPIA_ UTOPIA_ PD9 PD8 UTOPIA_TxADD3 UTOPIA_TXD4 UTOPIA_TXD3 PD4 UTOPIA_ UTOPIA_TXCLK UTOPIA_TxADD0 UTOPI UTOPIA_TxADD1 UTOPI UTOPIA_TXD2 UTOPIA_TXD1 UTOPIA_TXD0 UTOPIA_TxADD2 UTOPI PC5 PC4 PC3 PC2 PC1 PC0 PD13 PD12 PD11 PD10 PC31 PC30 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC19 PC18 PC17 PC16 PC11 A_RxADD3 A_RxADD4 A_TxPrty A_RxADD0 A_RxADD1 A_RxADD2 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RXCLK 4 4 WP1_RXD WP1_TXD P7A cPCI_J3 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 +3.3V_BP UTOPIA_TXD0 UTOPIA_TXD2 UTOPIA_TXD4 UTOPIA_TXD6 UTOPIA_TXD8 UTOPIA_TXD10 UTOPIA_TXD12 UTOPIA_TXD14 UTOPI UTOPIA_TxADD0 UTOPIA_TxADD2 UTOPIA_TxADD4 UTOPIA_TxSOC +5V A_TxClav PA0 PA1 PA2 PA3 PA4 PD4 PA5 UTOPIA_TXD3 PA6 UTOPIA_TXD4 PA7 UTOPIA_TxADD3 PA8 PD8 PA9 PD9 UTOPIA_RXD8 UTOPIA_RXD9 UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_RXD0 UTOPIA_ UTOPIA_RXD1 UTOPIA_ UTOPI UTOPIA_ UTOPIA_RxPrty UTOPIA_TXD15 UTOPI UTOPIA_TXD14 UTOPIA_TxADD4 UTOPIA_TXD13 UTOPIA_RXD2 UTOPIA_TXD12 UTOPIA_RXD3 UTOPIA_TXD11 UTOPIA_TXD5 UTOPIA_TXD10 UTOPIA_RXD4 UTOPIA_TXD9 UTOPIA_RXD5 UTOPIA_TXD8 UTOPIA_TXD6 UTOPIA_Rx UTOPIA_RXD6 UTOPIA_RxSOC UTOPIA_RXD7 UTOPIA_RxEnb_N UTOPIA_TXD7 UTOPI UTOPI WP1_TXD UTOPIA_TxE WP1_RXD PD10 PD11 PD12 PD13 UTOPIA_TxSOC 3 P7B 3 cPCI_J3 A_TxPrty A_RxADD4 A_RxADD3 A_TxClav B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 B9 B8 B7 B6 B5 B4 B3 B2 B1 TP332 Clav nb_N B9 B8 B7 B6 B5 B4 B3 B2 B1 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 +3.3V_BP B32 A32 B31 A31 B30 A30 B29 A29 B28 A28 B27 A27 B26 A26 B25 A25 B24 A24 B23 A23 B22 A22 B21 A21 B20 A20 B19 A19 B18 A18 B17 A17 B16 A16 B15 A15 B14 A14 B13 A13 B12 A12 B11 A11 B10 A10 CONN RCPT B9 A9 B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 UTOPIA_TXD1 UTOPIA_TXD3 UTOPIA_TXD5 UTOPIA_TXD7 UTOPIA_TXCLK UTOPIA_TXD9 UTOPIA_TXD11 UTOPIA_TXD13 UTOPIA_TXD15 UTOPIA_TxE UTOPI UTOPIA_TxADD1 UTOPIA_TxADD3 P29 BCD AB ABCD A_TxPrty 100x2 nb_N C32 D32 C31 D31 C30 D30 C29 D29 C28 D28 C27 D27 C26 D26 C25 D25 C24 D24 C23 D23 C22 D22 C21 D21 C20 D20 C19 D19 C18 D18 C17 D17 C16 D16 C15 D15 C14 D14 C13 D13 C12 D12 C11 D11 C10 D10 C9 D9 C8 D8 C7 D7 C6 D6 C5 D5 C4 D4 C3 D3 C2 D2 C1 D1 P7C cPCI_J3 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 TP333 PC0 PC1 PC2 PC3 PB4 PC4 PB5 PC5 PB6 UTOPI PB7 UTOPIA_TxADD2 PB8 UTOPIA_TXD0 PB9 UTOPIA_TXD1 PB10 UTOPIA_TXD2 PB11 PB12 UTOPI PB13 UTOPIA_TxADD1 PB14 UTOPI PB15 UTOPIA_TxADD0 PB16 PB17 PB18 PB19 PB20 UTOPIA_TXCLK PB21 UTOPIA_ PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PC11 PC16 PC17 PC18 PC19 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 A_RxADD2 A_RxADD1 A_RxADD0 RXCLK P7D cPCI_J3 2 2 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 +3.3V_BP UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_RxEnb_N UTOPIA_Rx UTOPI UTOPI A_RxADD1 A_RxADD3 RXD1 RXD3 RXD5 RXD7 RXCLK RXD9 RXD11 RXD13 RXD15 Prty P7E cPCI_J3 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 +3.3V_BP Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Processor 1 - Communications Processor Work Processor 1 - Communications UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA UTOPIA_Rx UTOPI UTOPI UTOPI UTOPIA_ UTOPIA_ UTOPIA_ UTOPIA_ A_RxADD0 A_RxADD2 A_RxADD4 _RxSOC RXD8 RXD10 RXD12 RXD14 RXD0 RXD2 RXD4 RXD6 Clav 1 +3.3V_BP Power 1 +5V P7F cPCI_J3 S10 ocessing System +3.3V_BP +5V DGND S9 S8 S7 S6 S5 S4 S3 S2 S1 F9 F8 F7 F6 F5 F4 F3 F2 F1 F10 172 31 of +3.3V_BP +5V DGND ilbride oue0.6 Module Rev C D A B

Figure A-29. Work Processor 1—Communications Processor Module

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-30 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 2 JP39 1 MSRCID0 MDC MDIO +3.3V +3.3V R634 R633 +3.3V TP80 TP162 TP161 TP160 TP159 TP158 +3.3V TP76 WP1_HRESET_N WP1_HRESET_REQ_N WP1_SRES CHKSTOP_OUT_N CHKSTOP_IN_N 204K7 4K7 R220 R219 4K7 R218 R217 R209 0R 0R MDC MDIO ASLEEP MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT THERM1 THERM0 CLK_OUT ET_N 4K7 4K7 AG20 AG19 AG18 AG22 AG28 AH16 AH20 AH28 AH27 AH26 AH25 AB22 AE28 AF20 AF22 AF28 AG2 AG1 M11 AH3 AH2 AH1 N12 G3 G1 G2 E1 A3 A2 B2 B1 F4 F2 F5 F3 F1 J9 HRESET HRESET_REQ SRESET CKSTP_OUT CKSTP_IN ASLEEP TEST_SEL(Draco/Dracom) LSSD_MODE MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT/READY/QUIESCE TRIG_IN L2_TSTCLK THERM1 THERM0 CLK_OUT L1_TSTCLK EC_MDIO EC_MDC NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 U1D MPC8560 AUXILIARY FUNCTION PIC CLOCKING 4 4 SPARES Eth.MI IRQ11/DMA_DDONE3 IRQ10/DMA_DACK3 SYS. CNTRL SYS. JTAG IRQ9/DMA_DREQ3 I2C ANALOG DMA DMA_DDONE1 DMA_DDONE0 DMA_DREQ1 DMA_DREQ0 DMA_DACK1 DMA_DACK0 PWR Mng. PWR DFT IRQ_OUT SYSCLK SPARE4 SPARE3 SPARE2 SPARE1 IIC_SDA IIC_SCL TRST IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 MCP TMS TDO UDE RTC TCK TDI DEBUG AH23 AF23 AF19 AB20 AG25 AA19 Y19 AA21 AG24 AB18 Y18 AA18 AF21 AH22 AH21 C1 AF1 U11 T11 AG23 G6 H7 G5 H6 G4 H5 AB21 AH24 AF26 Y20 AG16 AG17 AB23 AG21 IRQ11_N IRQ10_N IRQ9_N IRQ8_N IRQ7_N IRQ6_N IRQ2_N G1_IRQ_N IRQ0_N MCP_N WP1_INT_N BP_INT_N WP3_INT_N WP2_INT_N UDE_N I2C_SDA I2C_SCL WP1_RTC_CLK WP1_SYS_CLK 10K, RN RN143 TCK TMS WP1_T TDO TDI 1 TP75 TP74 TP73 TP72 2 3 RST_N

4 5 +3.3V

4K7 R625 +3.3V 6 10 7 8

10K R706 9 WP1_SYS_CLK WP1_RTC_CLK 4K7 R626 +3.3V +3.3V

1 I2C_SCL

I2C_SDA 2 3 5 4 10 6 7

3 8 3 9 RN144 10K, RN WP1_INT_N IRQ7_N IRQ6_N BP_INT_N WP3_INT_N WP2_INT_N G1_IRQ_N CHKSTOP_OUT_N WP1_COP_HRESET_N WP1_COP_SR TMS TCK TDO TDI ESET_N +3.3V 10K R210 10K R211 10K R212 10K R213 15 13 11 9 7 5 3 1 2 2 2x8 Header HD10 16 14 12 10 8 6 4 2 WP1_HRESET_REQ_N WP1_COP_ WP1_T WP1_COP_SR WP1_COP_HRESET_N WP1_HRESET_N WP1_SRE KEY KEY +3.3V RST_N SET_N 10K R214 TRST_N ESET_N 2K R215 10K R216 CHKSTOP_IN_N WP1_COP_ TRST_N ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K WP1_HRESET_R WP1_COP_T WP1_TRST_N WP1_COP_SR WP1_COP_HRES WP1_HRESET_N WP1_SRE Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr SET_N RST_N ESET_N EQ_N ET_N Work P oesr1-Axlr ucin 0.6 rocessor 1 - Auxilary Functions 1 1 +3.3V Power ocessing System +3.3V DGND 272 32 DGND +3.3V of ilbride Rev C D A B

Figure A-30. Work Processor 1—Auxiliary Functions

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B

"CONFIGURATION" RIO Processor TSEC Memory 5 PCI/RIO Processor 5 RIO "Device "Device "Device "Device "Device "Device "Device "Device "RIO Clk 1" "RIO Clk 0" "Core "Sys "Sys "Sys "Sys "TSEC1 Mode" "Debug Enable" "Host/Agent 1" "Host/Agent 0" "CPU Boot" Loc.2" "ROM Loc.1" "ROM Loc.0" "ROM "Core PLL3" PLL2" PLL1" PLL0" PLL1" PLL0" ID7" ID6" ID5" ID4" ID3" ID2" ID1" ID0" 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 SW DIP-8 SW SW8 DIP-8 SW SW7 DIP-8 SW SW6 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 10K, RN RN65 1 2

3 +3.3V 4 5

WP1_RST_CONF_N 6 10 7 8

4 9 4 10K, RN RN67 10K, RN RN66 1 1 2 2

3 +3.3V 3 +3.3V 4 5 4 5 6 10 6 10 7 7 8 8 9 9 74LVC 19 24 25 48 17 15 13 11 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 1 1 8 6 4 2 U28 U27 2OE 2A4 2A3 2A2 2A1 1OE 1A4 1A3 1A2 1A1 OE4 4A4 4A3 4A2 4A1 OE3 3A4 3A3 3A2 3A1 OE2 2A4 2A3 2A2 2A1 OE1 1A4 1A3 1A2 1A1 H244 4 DGND 10 DGND 74ALVT16244 +3.3V +3.3V VCC 15 7

GND DGND 3V3 10 20 21 DGND 3V3 18 28 DGND 3V3 31 34 DGND 3V3 42 39 DGND 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 45 DGND 4Y4 4Y3 4Y2 4Y1 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 3 5 7 9 12 14 16 18 23 22 20 19 17 16 14 13 12 11 9 8 6 5 3 2 R748 R747 R746 R745 R744 R743 R742 Do Not Fit 0R 0R G2TXD5 G2TXD6 G2TXD7 G1TXD4 G1TXD5 G1TXD6 G1TXD7 0R 0R 0R 0R 0R LGPL1 LGPL0 LGPL2 LALE BLA31 BLA30 BLA29 BLA28 BLA27 3 3 G1GTXCLK MSRCID0 LWE_N3 LWE_N2 G2TXD4 BLA27 LCS_N2 LCS_N1 LCS_N0 G2TXD2 G2TXD3 G2TXD[7:4] G1TXD[7:4] LGPL1 LGPL0 LGPL2 LALE BLA[27:31] G1GTXCLK MSRCID0 LWE_N[2:3] LCS_N[0:2] G2TXD2 G2TXD3 G2TXD4 G2TXD5 G2TXD6 G2TXD7 2 2 G2TXD[7:2] Add R742,R743 Remove R744,R745,R746,R747, For Rev 2 silicon; Note : Configuration shown is for Rev 1 Sili ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K

Decoupling Page Title : Page +3.3V Monday, September 08, 2003

Torridon - RapidIO Enabled Multi-Pr C849 0.1uF R748 +3.3V C850

okPoesr1-Cniuain0.6 Work Processor 1 - Configuration 0.1uF con. 1 1 +3.3V Power ocessing System +3.3V DGND 372 33 DGND +3.3V of ilbride Rev C D A B

Figure A-31. Work Processor 1—Power On Configuration

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-32 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 +3.3V AG27 AC17 AC11 AB11 AB26 AA20 AA16 AE15 AA12 AE10 AF10 AF12 W21 W19 W13 AG7 AG3 M12 AC9 AD8 AC6 AD3 AC5 AD4 AH4 G12 AA6 AB4 AB9 AE8 AB7 AA5 AE1 H12 C11 AF4 AF2 U26 R25 U20 R19 AF7 P12 V10 Y23 P22 K10 T12 F11 T10 W5 W4 M4 M5 G9 D8 U6 C4 H4 C2 N2 U5 H3 N3 D1 K9 Y8 V7 K5 B3 E3 V8 Y7 E4 K4 T8 T3 T7 T2 L6 L7 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 OVdd42 OVdd41 OVdd40 OVdd39 OVdd38 OVdd37 OVdd36 OVdd35 OVdd34 OVdd33 OVdd32 OVdd31 OVdd30 OVdd29 OVdd28 OVdd27 OVdd26 OVdd25 OVdd24 OVdd23 OVdd22 OVdd21 OVdd20 OVdd19 OVdd18 OVdd17 OVdd16 OVdd15 OVdd14 OVdd13 OVdd12 OVdd11 OVdd10 OVdd9 OVdd8 OVdd7 OVdd6 OVdd5 OVdd4 OVdd3 OVdd2 OVdd1 U1I MPC8560 POWER 4 4 GND99 GND98 GND97 GND96 GND95 GND94 GND93 GND92 GND91 GND90 GND89 GND88 GND87 GND86 GND85 GND84 GND83 GND82 GND81 GND80 GND79 GND78 GND77 GND76 GND75 GND74 GND73 GND72 GND71 GND70 GND69 GND68 GND67 GND66 GND65 GND64 GND63 GND62 GND61 GND60 GND59 GND58 GND57 GND56 GND55 GND54 GND53 GND52 GND51 GND50 GND49 GND48 GND47 GND46 GND45 GND44 GND43 GND42 GND41 GND40 K28 B27 C27 H27 M27 AF27 B26 R26 V26 AG26 G25 L25 E24 J24 F23 K23 P23 W23 C22 H22 M22 U21 B20 H20 L20 R20 C19 J19 AB19 F18 K18 W18 A17 C17 H17 N17 R17 U17 AD17 M16 P16 T16 U16 Y16 N15 R15 U15 AF15 B14 H14 M14 P14 T14 N13 R13 U13 AA13 AF13 A12 E12

Decoupling +3.3V +3.3V +3.3V C764 C757 C750 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C765 C758 C751 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C766 C759 C752 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C767 C760 C753 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C768 C761 C754

3 0.1uF 0.1uF 0.1uF 3 +3.3V +3.3V +3.3V C769 C762 C755 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C770 C763 C756 0.1uF 0.1uF 0.1uF +3.3V C957 10uF, 6.3V

Bulk Decoupling Decoupling +3.3V +3.3V 2 1C1128 C1088 + 220uF, Tants 10uF,6.3V Tants +3.3V

2 1C1129 Vdd

220uF, Tants M17 M15 M13 N16 R16 N14 R14 U14 R12 U12 P17 P15 P13 T17 T15 T13 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 U1E MPC8560 Supply &PLL CORE SENSE_VDD SENSE_VSS AVdd3 AVdd2 AVdd1 AH17 AH18 AH19 K12 Decoupling L12 Vdd Vdd C1118 C742

2 0.1uF 0.1uF 2 Vdd Vdd C1119 C743 0.1uF 0.1uF Vdd Vdd C1120 C744 0.1uF 0.1uF TP183 TP182 Vdd Vdd C1121 C745 0.1uF 0.1uF Vdd Vdd C1122 C746 0.1uF 0.1uF Vdd Vdd C1123 C747 0.1uF 0.1uF

Vdd Vdd C1264 C1263 C1262 C1124 C748 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Vdd Vdd C314 C312 C310 C1125 C749 0.1uF 0.1uF 2.2uF 2.2uF 2.2uF Vdd C956 C315 C313 C311 ae Sheet Date: Size : System 10R 10R 10R C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 10uF, 6.3V 2.2uF 2.2uF 2.2uF R269 R268 R267

Bulk Decoupling Decoupling Page Title : Page Wednesday, October 01, 2003 Vdd Vdd Vdd Vdd Vdd Torridon - RapidIO Enabled Multi-Pr 2 1C1126 C1087 + 220uF, Tants 10uF,6.3V Tants Vdd Work Processor 1 - 2 1C1127

220uF, Tants 12V fan Header for 2 HS2 10-THMA-01 1 Power 1 Vdd +3.3V +12V Power 1 HD21 S4 S3 DO57 DO57 1 ocessing System Vdd +3.3V +12V DGND Ferrite Bead Ferrite L31 472 34 2 DGND Vdd +3.3V +12V +12V of ilbride Rev 0.6 C D A B

Figure A-32. Work Processor 1—Power

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B WP2_HRESET_REQ_N WP2_COP_SRESET_N WP2_COP_HRESET_N WP2_COP_T WP2_HRESET_N WP2_SRE WP2_SYS_CLK WP2_RTC_CLK WP2_T BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N 5 5 RST_N RST_N SET_N DGND +3.3V WP2_RTC_CLK WP2_HRESET_REQ_N WP2_COP_T WP2_T WP2_COP_SRESET_N WP2_COP_HRESET_N WP2_HRESET_N WP2_SRE WP2_SYS_CLK BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RST_N MSRCID0 SET_N RST_N +3.3V DGND WP2 - CPM Page 43 WP2 - AUX Page 39 WP2_SYS_CLK WP2_RTC_CLK MSRCID0 WP2_HRESET_REQ_N WP2_COP_TRST_N WP2_TRST_N WP2_COP_SRESET_N WP2_COP_HRESET_N WP2_HRESET_N WP2_SRESET_N DGND +3.3V BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RIO2_TXCLK_IN_N RIO2_TXCL K_IN G1_IRQ_N RIO2_TXCLK_IN_N RIO2_TXCL WP2_RXD WP2_TXD I2C_SDA I2C_SCL MDIO MDC 4 4 K_IN WP2 - RIO Page 38 WP2_RXD WP2_TXD RIO2_TXCLK_IN_N RIO2_TXCLK_IN G1GTXCLK MDC G1_IRQ_N I2C_SCL I2C_SDA MDIO G2TXD[7:2] G1TXD[7:4] WP2 - TSEC Top Page 35 WP2 - DDR SDRAM Page 32 RIO2_RFRAME_N RIO2_TFRAME_N WP2_RXD WP2_TXD G1GTXCLK G2TXD[7:2] G1TXD[7:4] MDIO MDC G1_IRQ_N I2C_SCL I2C_SDA RIO2_RD_N[0:7] RIO2_TD_N[0:7] RIO2_RFRAME RIO2_TFRAME RIO2_RCLK_N RIO2_TCLK_N RIO2_RD[0:7] RIO2_TD[0:7] RIO2_RCLK RIO2_TCLK RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME_N RIO2_RFRAME RIO2_TCLK RIO2_TFRAME_N RIO2_TFRAME WP2_G1_RESET_N RIO2_TCLK_N RIO2_R RIO2_R RIO2_TD_N[0:7] RIO2_TD[0:7] +1.5VGEther +2.5VGEther D_N[0:7] D[0:7] DGND DGND +3.3V +2.5V +3.3V 3 3 WP2_G1_ +1.5 +2.5 +3.3V +2.5V +3.3V DGND DGND RIO2_RD_N[0:7] RIO2_R RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME_N RIO2_RFRAME RIO2_TD_N[0:7] RIO2_TD[0:7] RIO2_TCLK_N RIO2_TCLK RIO2_TFRAME_N RIO2_TFRAME VGEther VGEther RESET_N D[0:7] +2.5V +3.3V DGND +1.5VGE +2.5VGE +3.3V DGND WP2_G1_ ther ther RESET_N WP2_RST_CONF_N DGND LGPL2 LGPL1 LGPL0 LALE BLA[27:31] LCS_N[0:2] LWE_N[2:3] +3.3V 2 2 WP2_RST_CONF_N +3.3V DGND WP2 - Page 45 WP2 - Local Bus Page 36 WP2 - PCI Page 37 - Power WP2 Page 46 WP2_RST_CONF_N DGND +3.3V LGPL2 LGPL1 LGPL0 LALE BLA[27:31] LCS_N[0:2] LWE_N[2:3] Config ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K LWE_N[2:3] G1GTXCLK G2TXD[7:2] G1TXD[7:4] LCS_N[0:2] BLA[27:31] MSRCID0 LGPL2 LGPL1 LGPL0 Page T DGND Monday, September 08, 2003 +3.3V LALE +12V Torridon - RapidIO Enabled Multi-Pr Vdd itle : okPoesr2-TpLvl0.6 Processor 2 - Top Level Work +12V Vdd +3.3V DGND G1GTXCLK LGPL2 LGPL1 LGPL0 LALE MSRCID0 G2TXD[7:2] G1TXD[7:4] LCS_N[0:2] LWE_N[2:3] BLA[27:31] 1 1 ocessing System DGND +12V Vdd +3.3V 572 35 of ilbride Rev C D A B

Figure A-33. Work Processor 2—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-34 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 4 4 LGPL4/LGTA/LUPWAIT/LPBSE LOCAL BUS LOCAL LCS7/DMA_DDONE2 LGPL2/LOE/LSDRAS LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LGPL3/LSDCAS LGPL0/LSDA10 LGPL1/LSDWE LSYNC_OUT LWE3/LBS3 LWE2/LBS2 LWE1/LBS1 LWE0/LBS0 U7F MPC8560 LSYNC_IN LGPL5 LBCTL LCLK2 LCLK1 LCLK0 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LCKE LCS4 LCS3 LCS2 LCS1 LCS0 LDP3 LDP2 LDP1 LDP0 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 LALE LA31 LA30 LA29 LA28 LA27 U19 V20 T27 T21 T20 T19 T18 U18 T28 V21 V18 U28 U27 N26 N25 N24 N23 N22 P18 P19 P20 P25 P26 R18 R21 R22 R23 R24 T22 V19 W26 W22 W20 Y26 Y22 V22 P21 T26 AA28 AA27 Y21 AA26 AA23 AA22 AC28 AC27 AC26 AD28 AD27 AD26 U23 P28 P27 R28 R27 W28 W27 Y28 Y27 P24 T23 AB27 AB28 V23 V27 V28 U22 3 3 LALE BLA31 BLA30 BLA29 BLA28 BLA27 LWE_N3 LWE_N2 LGPL2 LGPL1 LGPL0 LCS_N2 LCS_N1 LCS_N0 TP274 TP273 LALE LCS_N[0:2] BLA[27:31] LWE_N[2:3] LGPL2 LGPL1 LGPL0 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr okPoesr2-LclBs0.6 Work Processor 2 - Local Bus 1 1 ocessing System 672 36 of ilbride Rev C D A B

Figure A-34. Work Processor 2—Local Bus

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B TP60 TP59 TP58 TP57 TP56 TP55 VREF2

Decoupling +2.5V +2.5V +2.5V +2.5V 2 1 C694 C689 C672 C667 2MCK_N5 2MCK5 2MCK_N4 2MCK4 2MCK_N3 2MCK_3 2MCK_N2 2MCK2 2MCK_N1 2MCK1 2MCK_N0 2MCK0 2MCKE1 2MCKE0 2MCS3_N 2MCS2_N 2MCS1_N 2MCS0_N 2MCAS_N 2MRAS_N 2MWE_N 2MBA1 2MBA0 2MA14 2MA13 2MA12 2MA11 2MA10 2MA9 2MA8 2MA7 2MA6 2MA5 2MA4 2MA3 2MA2 2MA1 2MA0 2MDQS8 2MDQS7 2MDQS6 2MDQS5 2MDQS4 2MDQS3 2MDQS2 2MDQS1 2MDQS0 2MDM8 2MDM7 2MDM6 2MDM5 2MDM4 2MDM3 2MDM2 2MDM1 2MDM0 2MECC7 2MECC6 2MECC5 2MECC4 2MECC3 2MECC2 2MECC1 2MECC0 +

0.1uF C133 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V

VTT2_Sence C695 C690 C673 C668 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V C696 C691 C674 C669 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V C697 C692 C675 C670 4 3 2 1

0.1uF 0.1uF 0.1uF 0.1uF R1169 R1167 R1165 R1163 R1161 R1159 R1157 R1155 R1153 R1151 R1149 R1147 R1145 R1143 R1141 R1139 R1137 R1135 R1133 R1131 R1129 R1127 R1125 R1123 R1121 R1119 R1117 R1115 R1113 R1111 R1109 R1107 R1105 R1103 R1101 R1099 R1097 R1095 R1093 R1091 R1089 R1087 R1085 R1083 R1081 R1079 R1077 R1075 R1073 R1071 R1069 R1067 R1065 R1063 R1061 R1059 R1057 R1055 R1053 R1051 R1049 R1047 R1045 R1043 R1041 +2.5V +2.5V +2.5V +2.5V VREF VSENSE GND NC U26 LP2995

5 C698 C693 C676 C671 5

LP2995 0.1uF 0.1uF 0.1uF 0.1uF 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R

VDDQ Decoupling Decoupling Place Near Pin N27 VREF2 2MSYNC_IN 2MSYNC_OUT AVIN PVIN VTT VREF2 +2.5V C996 C1077 VREF2 0.1uF + Decoupling 2NCK5 2NCK4 2NCK3 2NCK2 2NCK1 2NCK0 2CKE1 2CKE0 2CAS_N 2RAS_N 2BA1 2BA0 2A14 2A13 2A12 2A11 2A10 2A9 2A8 2A7 2A6 2A5 2A4 2A3 2A2 2A1 2A0 2DQS8 2DQS7 2DQS6 2DQS5 2DQS4 2DQS3 2DQS2 2DQS1 2DQS0 2DM8 2DM7 2DM6 2DM5 2DM4 2DM3 2DM2 2DM1 2DM0 2ECC7 2ECC6 2ECC5 2ECC4 2ECC3 2ECC2 2ECC1 2ECC0 2CK5 2CK4 2CK3 2CK2 2CK1 2CK0 2CS3_N 2CS2_N 2CS1_N 2CS0_N 2WE_N 6 7 5 8

10uF,6.3V Tants VREF2

VREF2 C995 C997 0.1uF 0.01uF M28 M21 M19 M20 G27 G16 G24 G14 G19 N27 N28 D20 H25 H15 H16 D17 D27 H23 C23 N19 C20 C13 H18 D25 H28 C21 N20 K14 E20 B15 A15 E28 E26 B19 B18 B25 K19 B24 A23 K21 B21 A22 B13 E16 E18 A19 A21 E19 F27 F28 F20 F17 F21 F14 F16 F24 L14 L26 L21 L24 L19 J20 J15 J16 J13 J14 J25 2 1 47uF, Tants C131 MVREF(GVdd/2) MSYNC_IN MSYNC_OUT MCK5- MCK5 MCK4- MCK4 MCK3- MCK3 MCK2- MCK2 MCK1- MCK1 MCK0- MCK0 MCKE1 MCKE0 MCS3- MCS2- MCS1- MCS0- MCAS- MRAS- MWE- MBA1 MBA0 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MDQS8 MDQS7 MDQS6 MDQS5 MDQS4 MDQS3 MDQS2 MDQS1 MDQS0 MDM8 MDM7 MDM6 MDM5 MDM4 MDM3 MDM2 MDM1 MDM0 MECC7 MECC6 MECC5 MECC4 MECC3 MECC2 MECC1 MECC0 U7B MPC8560 +2.5V D SDRAM DDR 2 1 220uF, Tants C132 VTT2 1.25V @ GVdd41 GVdd40 GVdd39 GVdd38 GVdd37 GVdd36 GVdd35 GVdd34 GVdd33 GVdd32 GVdd31 GVdd30 GVdd29 GVdd28 GVdd27 GVdd26 GVdd25 GVdd24 GVdd23 GVdd22 GVdd21 GVdd20 GVdd19 GVdd18 GVdd17 GVdd16 GVdd15 GVdd14 GVdd13 GVdd12 GVdd11 GVdd10 MDQ63 MDQ62 MDQ61 MDQ60 MDQ59 MDQ58 MDQ57 MDQ56 MDQ55 MDQ54 MDQ53 MDQ52 MDQ51 MDQ50 MDQ49 MDQ48 MDQ47 MDQ46 MDQ45 MDQ44 MDQ43 MDQ42 MDQ41 MDQ40 MDQ39 MDQ38 MDQ37 MDQ36 MDQ35 MDQ34 MDQ33 MDQ32 MDQ31 MDQ30 MDQ29 MDQ28 MDQ27 MDQ26 MDQ25 MDQ24 MDQ23 MDQ22 MDQ21 MDQ20 MDQ19 MDQ18 MDQ17 MDQ16 MDQ15 MDQ14 MDQ13 MDQ12 MDQ11 MDQ10 GVdd9 GVdd8 GVdd7 GVdd6 GVdd5 GVdd4 GVdd3 GVdd2 GVdd1 MDQ9 MDQ8 MDQ7 MDQ6 MDQ5 MDQ4 MDQ3 MDQ2 MDQ1 MDQ0 1.5A J28 K22 K26 K27 M23 M24 K24 L22 L27 M26 A28 B28 C28 D28 G28 L28 A27 J27 A26 A25 F25 K25 M25 D24 H24 G23 L23 B22 E22 J22 D21 N21 A20 G20 K20 D19 F19 H19 G18 B17 E17 J17 D16 F15 K15 A14 G13 L13 C12 F12 J12 B12 A13 H13 F13 A11 D12 E13 D13 D14 E14 D15 C15 K13 C14 E15 G15 L15 A16 L16 G17 B16 C16 K16 K17 A18 C18 L18 M18 L17 D18 J18 N18 E21 H21 D22 G22 G21 J21 F22 B23 D23 A24 C25 D26 E23 C24 E25 C26 G26 H26 J23 J26 E27 F26 +2.5V 2DQ63 2DQ62 2DQ61 2DQ60 2DQ59 2DQ58 2DQ57 2DQ56 2DQ55 2DQ54 2DQ53 2DQ52 2DQ51 2DQ50 2DQ49 2DQ48 2DQ47 2DQ46 2DQ45 2DQ44 2DQ43 2DQ42 2DQ41 2DQ40 2DQ39 2DQ38 2DQ37 2DQ36 2DQ35 2DQ34 2DQ33 2DQ32 2DQ31 2DQ30 2DQ29 2DQ28 2DQ27 2DQ26 2DQ25 2DQ24 2DQ23 2DQ22 2DQ21 2DQ20 2DQ19 2DQ18 2DQ17 2DQ16 2DQ15 2DQ14 2DQ13 2DQ12 2DQ11 2DQ10 2DQ9 2DQ8 2DQ7 2DQ6 2DQ5 2DQ4 2DQ3 2DQ2 2DQ1 2DQ0 4 4

Bulk Decoupling Decoupling +2.5V +2.5V +2.5V +2.5V R1168 R1166 R1164 R1162 R1160 R1158 R1156 R1154 R1152 R1150 R1148 R1146 R1144 R1142 R1140 R1138 R1136 R1134 R1132 R1130 R1128 R1126 R1124 R1122 R1120 R1118 R1116 R1114 R1112 R1110 R1108 R1106 R1104 R1102 R1100 R1098 R1096 R1094 R1092 R1090 R1088 R1086 R1084 R1082 R1080 R1078 R1076 R1074 R1072 R1070 R1068 R1066 R1064 R1062 R1060 R1058 R1056 R1054 R1052 R1050 R1048 R1046 R1044 R1042 2 1C1171 C1249 C1242 C1235 0.1uF 0.1uF 0.1uF

220uF, Tants +2.5V +2.5V +2.5V

+2.5V C1250 C1243 C1236 2 1C1172 0.1uF 0.1uF 0.1uF 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R +2.5V +2.5V +2.5V 220uF, Tants C1251 C1244 C1237 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1252 C1245 C1238 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1253 C1246 C1239 0.1uF 0.1uF 0.1uF 2MDQ63 2MDQ62 2MDQ61 2MDQ60 2MDQ59 2MDQ58 2MDQ57 2MDQ56 2MDQ55 2MDQ54 2MDQ53 2MDQ52 2MDQ51 2MDQ50 2MDQ49 2MDQ48 2MDQ47 2MDQ46 2MDQ45 2MDQ44 2MDQ43 2MDQ42 2MDQ41 2MDQ40 2MDQ39 2MDQ38 2MDQ37 2MDQ36 2MDQ35 2MDQ34 2MDQ33 2MDQ32 2MDQ31 2MDQ30 2MDQ29 2MDQ28 2MDQ27 2MDQ26 2MDQ25 2MDQ24 2MDQ23 2MDQ22 2MDQ21 2MDQ20 2MDQ19 2MDQ18 2MDQ17 2MDQ16 2MDQ15 2MDQ14 2MDQ13 2MDQ12 2MDQ11 2MDQ10 2MDQ9 2MDQ8 2MDQ7 2MDQ6 2MDQ5 2MDQ4 2MDQ3 2MDQ2 2MDQ1 2MDQ0 +2.5V +2.5V +2.5V C1254 C1247 C1240 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1255 C1248 C1241 0.1uF 0.1uF 0.1uF I2C_SDA Place Near Pin 1 I2C_SCL Decoupling VREF2 C993

3 0.1uF 3 VREF2 C994 0.01uF +3.3V VddSPD I2C_SCL I2C_SDA 2MDQ59 2MDQ58 2MDQS7 2MDQ57 2MDQ56 2MDQ51 2MDQ50 2MDQS6 2MDQ49 2MDQ48 2MDQ43 2MDQ42 2MDQS5 2MDQ41 2MDQ40 2MDQ35 2MDQ34 2MDQS4 2MDQ33 2MDQ32 2MCS0_N 2MWE_N 2MBA0 2MA10 2MA1 2MA3 2MA5 2MA7 2MA9 2MA12 2MCKE1 2MCK_N1 2MCK1 2MECC3 2MECC2 2MDQS8 2MECC1 2MECC0 2MDQ27 2MDQ26 2MDQS3 2MDQ25 2MDQ24 2MDQ19 2MDQ18 2MDQS2 2MDQ17 2MDQ16 2MCK_N2 2MCK2 2MDQ11 2MDQ10 2MDQS1 2MDQ9 2MDQ8 2MDQ3 2MDQ2 2MDQS0 2MDQ1 2MDQ0 VREF2 +2.5V 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 P18 DDR SODIMM DDR Decoupling Decoupling VTT2 VTT2 C1051 C1043 0.1uF 0.1uF 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 VTT2 VTT2 C1052 C1044 0.1uF 0.1uF VTT2 VTT2

+2.5V C1053 C1045 0.1uF 0.1uF VTT2 VTT2 C1054 C1046 2MDQ63 2MDQ62 2MDM7 2MDQ61 2MDQ60 2MDQ55 2MDQ54 2MDM6 2MDQ53 2MDQ52 2MCK0 2MCK_N0 2MDQ47 2MDQ46 2MDM5 2MDQ45 2MDQ44 2MDQ39 2MDQ38 2MDM4 2MDQ37 2MDQ36 2MCS1_N 2MCAS_N 2MRAS_N 2MBA1 2MA0 2MA2 2MA4 2MA6 2MA8 2MA11 2MCKE0 2MECC7 2MECC6 2MDM8 2MECC5 2MECC4 2MDQ31 2MDQ30 2MDM3 2MDQ29 2MDQ28 2MDQ23 2MDQ22 2MDM2 2MDQ21 2MDQ20 2MDQ15 2MDQ14 2MDM1 2MDQ13 2MDQ12 2MDQ7 2MDQ6 2MDM0 2MDQ5 2MDQ4 VREF2 0.1uF 0.1uF VTT2 VTT2 C1055 C1047 0.1uF 0.1uF Do Not Fit VTT2 VTT2 C1056 C1048 R178 R175 0.1uF 0.1uF

2 4K7 10K +3.3V VTT2 VTT2 2 R179 R176 C1057 C1049 4K7 10K 0.1uF 0.1uF

R180 R177 VTT2 VTT2 4K7 10K C1058 C1050 +

MT18VDDT6472 SODIMM3 0.1uF

199(200) 41(42) 39(40) 1(2) 10uF,6.3V Tants 200-pin DDR SDRAM SODIMM 2MA1 2MA0 2MA3 2MA2 2MA5 2MA4 2MA7 2MA6 2MA9 2MA8 2MA12 2MA11 2MCKE1 2MCKE0 2MECC3 2MECC7 2MECC2 2MECC6 2MDQS8 2MDM8 2MECC1 2MECC5 2MECC0 2MECC4 2MDQ27 2MDQ31 2MDQ26 2MDQ30 2MDQS3 2MDM3 2MDQ25 2MDQ29 2MDQ24 2MDQ28 2MDQ19 2MDQ23 2MDQ18 2MDQ22 2MDQS2 2MDM2 2MDQ17 2MDQ21 2MDQ16 2MDQ20 2MDQ11 2MDQ15 2MDQ10 2MDQ14 2MDQS1 2MDM1 2MDQ9 2MDQ13 2MDQ8 2MDQ12 2MDQ3 2MDQ7 2MDQ2 2MDQ6 2MDQS0 2MDM0 2MDQ1 2MDQ5 2MDQ0 2MDQ4

Decoupling Decoupling VTT2

VTT2 C677 C998 0.1uF ae Sheet Date: Size : System VTT2 C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 0.1uF 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

VTT2 C678 C999 0.1uF 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN Page Title : Page 0.1uF VTT2 Wednesday, October 01, 2003 VTT2 RN231 RN229 RN97 RN95 RN89 RN85 RN81 RN75 Torridon - RapidIO Enabled Multi-Pr C679 C1000 0.1uF

0.1uF VTT2 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16

VTT2 C680 VTT2 Work Pr C1001 0.1uF + VTT2 10uF,6.3V Tants C681

0.1uF VTT2_Sence cso D DA 0.6 ocessor 2 - DDR SDRAM VTT2 Tap VTT Sence from middle C682 0.1uF 1 VTT2 1 C683 2MA14 2MA13 2MCS3_N 2MCS2_N 2MDQ59 2MDQ63 2MDQ58 2MDQ62 2MDQS7 2MDM7 2MDQ57 2MDQ61 2MDQ56 2MDQ60 2MDQ51 2MDQ55 2MDQ50 2MDQ54 2MDQS6 2MDM6 2MDQ49 2MDQ53 2MDQ48 2MDQ52 2MDQ43 2MDQ47 2MDQ42 2MDQ46 2MDQS5 2MDM5 2MDQ41 2MDQ45 2MDQ40 2MDQ44 2MDQ35 2MDQ39 2MDQ34 2MDQ38 2MDQS4 2MDM4 2MDQ33 2MDQ37 2MDQ32 2MDQ36 2MCS0_N 2MCS1_N 2MWE_N 2MCAS_N 2MBA0 2MRAS_N 2MA10 2MBA1 0.1uF +2.5V +3.3V Power VTT2 C684 ocessing System 0.1uF VTT2 +2.5V +3.3V DGND C685

0.1uF 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 VTT2 772 37 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN C686

0.1uF RN230 RN98 RN96 RN90 RN86 RN82 RN76 VTT2 of +2.5V +3.3V DGND C687 ilbride

0.1uF 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 VTT2 VTT2 C688

Rev 0.1uF C D A B

Figure A-35. Work Processor 2—DDR SDRAM

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-36 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 RIO2_TXCLK_IN_N RIO2_TXCL K_IN RIO2_TXCLK_ RIO2_TXCL 4 4 K_IN IN_N AF25 AF24 MPC8560 RIO_TXCLK_IN- RIO_TXCLK_IN U7C RIO_RFRAME- RIO_TFRAME- RIO_RFRAME RIO_TFRAME RIO_RCLK- RIO_TCLK- RIO_RCLK RIO_TCLK RIO_RD7- RIO_RD6- RIO_RD5- RIO_RD4- RIO_RD3- RIO_RD2- RIO_RD1- RIO_RD0- RIO_TD7- RIO_TD6- RIO_TD5- RIO_TD4- RIO_TD3- RIO_TD2- RIO_TD1- RIO_TD0- RIO_RD7 RIO_RD6 RIO_RD5 RIO_RD4 RIO_RD3 RIO_RD2 RIO_RD1 RIO_RD0 RIO_TD7 RIO_TD6 RIO_TD5 RIO_TD4 RIO_TD3 RIO_TD2 RIO_TD1 RIO_TD0 AE27 Y25 AD23 AC22 AE22 AD21 AE20 AD19 AC18 AE18 AE25 AD25 AC25 AB25 AA25 W25 V25 U25 T25 AE26 AC23 AE23 AD22 AC21 AD20 AC19 AE19 AD18 AE24 AE21 AD24 AC24 AB24 AA24 W24 V24 U24 T24 AC20 Y24 RIO2_RD_N7 RIO2_RD7 RIO2_RD_N6 RIO2_RD6 RIO2_RD_N5 RIO2_RD5 RIO2_RD_N4 RIO2_RD4 RIO2_RD_N3 RIO2_RD3 RIO2_RD_N2 RIO2_RD2 RIO2_RD_N1 RIO2_RD1 RIO2_RD_N0 RIO2_RD0 RIO2_RFRAME_N RIO2_RFRAME RIO2_RCLK_N RIO2_RCLK RIO2_TFRAME_N RIO2_TFRAME RIO2_TCLK RIO2_TD_N7 RIO2_TD7 RIO2_TD_N6 RIO2_TD6 RIO2_TD_N5 RIO2_TD5 RIO2_TD_N4 RIO2_TD4 RIO2_TD_N3 RIO2_TD3 RIO2_TD_N2 RIO2_TD2 RIO2_TD_N1 RIO2_TD1 RIO2_TD_N0 RIO2_TD0 RIO2_TCLK_N 3 3 RIO2_RFRAME_N RIO2_RFRAME RIO2_RCLK_N RIO2_RCLK RIO2_R RIO2_R D[0:7] D_N[0:7] RIO2_TFRAME_N RIO2_TFRAME RIO2_TCLK RIO2_TCLK_N RIO2_TD7 RIO2_TD6 RIO2_TD5 RIO2_TD4 RIO2_TD3 RIO2_TD2 RIO2_TD1 RIO2_TD0 RIO2_TD_N7 RIO2_TD_N6 RIO2_TD_N5 RIO2_TD_N4 RIO2_TD_N3 RIO2_TD_N2 RIO2_TD_N1 RIO2_TD_N0 RIO2_RFRAME_N RIO2_RFRAME RIO2_RCLK_N RIO2_RCLK RIO2_RD_N7 RIO2_RD_N6 RIO2_RD_N5 RIO2_RD_N4 RIO2_RD_N3 RIO2_RD_N2 RIO2_RD_N1 RIO2_RD_N0 RIO2_RD7 RIO2_RD6 RIO2_RD5 RIO2_RD4 RIO2_RD3 RIO2_RD2 RIO2_RD1 RIO2_RD0 RIO2_TFRAME_N RIO2_TFRAME RIO2_TCLK_N RIO2_TCLK RIO2_TD[0:7] RIO2_TD_N[0:7] 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Work rcso aiI nefc 0.6 Processor 2 - RapidIO Interface 1 1 ocessing System 872 38 of ilbride Rev C D A B

Figure A-36. Work Processor 2—RapidIO Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 4 4 AG10 AG13 AD13 AH10 AD10 AC10 AH13 AD11 AC12 AE13 AA11 AB10 W11 W14 AG6 AG5 AG4 AH5 AH8 AE6 AE5 AE4 AA9 AF6 AF3 AF5 Y11 V11 Y14 V14 PCI_GNT4 PCI_GNT3 PCI_GNT2 PCI_GNT1 PCI_GNT0 PCI_REQ4 PCI_REQ3 PCI_REQ2 PCI_REQ1 PCI_REQ0 PCI_SERR PCI_PERR PCI_ACK64 PCI_REQ64 PCI_IDSEL PCI_DEVSEL PCI_STOP PCI_IRDY PCI_TRDY PCI_FRAME PCI_PAR64 PCI_PAR PCI_C_BE7 PCI_C_BE6 PCI_C_BE5 PCI_C_BE4 PCI_C_BE3 PCI_C_BE2 PCI_C_BE1 PCI_C_BE0 U7A MPC8560 PCIX/PCI PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 AA14 AB14 AC14 AD14 AE14 AF14 AG14 AH14 V15 W15 Y15 AA15 AB15 AC15 AD15 AG15 AH15 V16 W16 AB16 AC16 AD16 AE16 AF16 V17 W17 Y17 AA17 AB17 AE17 AF17 AF18 AH6 AD7 AE7 AH7 AB8 AC8 AF8 AG8 AD9 AE9 AF9 AG9 AH9 W10 Y10 AA10 AE11 AF11 AG11 AH11 V12 W12 Y12 AB12 AD12 AE12 AG12 AH12 V13 Y13 AB13 AC13 3 3 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Pro esr2-PIItrae0.6 cessor 2 - PCI Interface 1 1 ocessing System 972 39 of ilbride Rev C D A B

Figure A-37. Work Processor 2—PCI Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-38 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 DGND +3.3V 4 4 DGND +3.3V WP2 - TSEC Page 41 DGND +3.3V G1RXD[7:0] G1GTXCLK G1TXD[7:0] G2TXD[7:2] G1RXCLK MGTX125 G1TXCLK G1RXER G1RXDV G1TXER G1TXEN G1CRS G1COL WP2_G1_ G2TXD[7:2] G1_IRQ_N G1TXD[7:4] RESET_N MDC MDIO 3 3 G1GTXCLK G1TXD[7:4] G2TXD[7:2] MGTX125 MDC WP2_G1_ G1_IRQ_N G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN MDIO G1COL G1RX G1TXD[7:0] D[7:0] RESET_N WP2 - Page 42 MDC MDIO WP2_G1_RESET_N G1_IRQ_N MGTX125 G1COL G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN G1RXD[7:0] G1TXD[7:0] TSEC - PHY +1.5VGEther +2.5VGEther DGND +3.3V +1.5VGEther +2.5VGEther +3.3V DGND 2 2 DGND +1.5VGEther +2.5VGEther +3.3V ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Monday, September 08, 2003 Torridon - RapidIO Enabled Multi-Pr okPoesr2-GgBt tentItrae-Tp0.6 Processor 2 - GigaByte Ethernet Interface Top Work 1 1 ocessing System 072 40 of ilbride Rev C D A B

Figure A-38. Work Processor 2—GigaByte Ethernet Interface—Top

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 +3.3V 5 H10 C5 E7 A4

Decoupling LVdd4 LVdd3 LVdd2 LVdd1 +3.3V

C734 Clocking GbE TSEC2 TSEC1

0.1uF U7G +3.3V C735 TSEC2_GTX_CLK TSEC1_GTX_CLK EC_GTX_CLK125

0.1uF MPC8560 TSEC2_RX_CLK TSEC1_RX_CLK TSEC2_TX_CLK TSEC1_TX_CLK TSEC2_RX_ER TSEC2_RX_DV TSEC1_RX_ER TSEC1_RX_DV TSEC2_TX_ER TSEC2_TX_EN TSEC1_TX_ER TSEC1_TX_EN +3.3V TSEC2_RXD7 TSEC2_RXD6 TSEC2_RXD5 TSEC2_RXD4 TSEC2_RXD3 TSEC2_RXD2 TSEC2_RXD1 TSEC2_RXD0 TSEC1_RXD7 TSEC1_RXD6 TSEC1_RXD5 TSEC1_RXD4 TSEC1_RXD3 TSEC1_RXD2 TSEC1_RXD1 TSEC1_RXD0 C736 TSEC2_TXD7 TSEC2_TXD6 TSEC2_TXD5 TSEC2_TXD4 TSEC2_TXD3 TSEC2_TXD2 TSEC2_TXD1 TSEC2_TXD0 TSEC1_TXD7 TSEC1_TXD6 TSEC1_TXD5 TSEC1_TXD4 TSEC1_TXD3 TSEC1_TXD2 TSEC1_TXD1 TSEC1_TXD0 TSEC2_CRS TSEC1_CRS TSEC2_COL TSEC1_COL 0.1uF +3.3V C737 0.1uF E2 D10 C6 C10 B6 F8 G7 E10 D6 A8 H8 E5 D2 B10 A10 J10 K11 J11 H11 G11 E11 A6 F7 D7 C7 B7 A7 G8 E8 D11 B11 B8 C8 F9 E9 C9 B9 A9 H9 G10 F10 D4 B4 D3 D5 B5 A5 F6 E6 D9 C3

Decoupling +3.3V R376 R375 R374

C1086 8 7 6 5 4 3 2 1 + RN158 22R, RN 10uF,6.3V Tants G1RXCLK G1RXER G1RXDV MGTX125 G2TXD7 G2TXD6 G2TXD5 G2TXD4 G2TXD3 G2TXD2 G1CRS G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 G1COL 22R 0.1W 22R 0.1W 22R 0.1W 22R 9 10 11 12 13 14 15 16 G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0 G1GTXCLK G1TXCLK G1TXER G1TXEN G1RX D[7:0] 4 4 G2TXD[7:2] G1COL G1CRS G1RXCLK G1RXER G1RXDV MGTX125 G1GTXCLK G1TXCLK G1TXER G1TXEN G1TXD[7:0] MGTX125 220R R377 +3.3V

330RR378

100pF C428 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G1RXD[7:0] 8 7 6 5 4 3 2 1 3R RN 330R, RN161 8 7 6 5 4 3 2 1 RN159 9 10 11 12 13 14 15 16 2R RN 220R, 9 10 11 12 13 14 15 16 100pF, CN 4 3 2 1 4 3 2 1 3 +3.3V 3 100pF, CN 100pF, CN15 5 6 7 8 5 6 7 8 CN13 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 8 7 6 5 4 3 2 1 3R RN 330R, RN162 8 7 6 5 4 3 2 1 RN160 G1TXD[7:0] 9 10 11 12 13 14 15 16 2R RN 220R, 9 10 11 12 13 14 15 16 100pF, CN 4 3 2 1 4 3 2 1 +3.3V 100pF, CN 100pF, CN16 G1RXCLK G1GTXCLK G1TXEN 5 6 7 8 5 6 7 8 CN14 2 2 220R R597 220R R591 220R R585 +3.3V +3.3V +3.3V

330R R598 330R R592 330R R586

100pF C884 100pF C881 100pF C878 G1CRS G1RXDV G1TXER 220R R599 220R R593 220R R587 +3.3V +3.3V +3.3V

330R R600 330R R594 330R R588

100pF C885 100pF C882 100pF C879 G1RXER G1TXCLK G1COL ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 220R R601 220R R595 220R R589 Page Title : Page Friday, September 26, 2003 +3.3V +3.3V +3.3V Torridon - RapidIO Enabled Multi-Pr

330R R602 330R R596 330R R590 Work 100pF C886 100pF C883 100pF C880 Power Processor 2 - GigaByte Ethernet Interface +3.3V 1 1 DGND +3.3V ocessing System 172 41 DGND +3.3V of ilbride Rev 0.6 C D A B

Figure A-39. Work Processor 2—GigaByte Ethernet Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-40 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B MDIO WP2_G1_RE MDC SET_N MDC MDIO 5 5 1K R1348 +3.3V +3.3V R1301

10K 1K R1349 G1RXD[7:0] G1TXD[7:0] G1GTXCLK MGTX125 G1RXCLK G1_IRQ_N G1TXCLK G1TXER G1TXEN G1CRS G1COL G1RXER G1RXDV WP2_G1_ C498 C497 +1.5VGE RESET_N 18pF 18pF G1TXCLK G1TXER G1TXEN G1RXCLK G1RXER G1RXDV ther 3 2 G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0 G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 0.01uF C484 MGTX125 G1CRS G1GTXCLK G1_IRQ_N G1COL

4 1 0.1uF C489

R422 R420 R419 R413 R412 R411 0.01uF C485 8 7 6 5 4 3 2 1 25MHz Y10 22R, RN 0.1uF C490

0.01uF C486 RN164 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R R417 0.1uF C491 GROUND Separate 9 10 11 12 13 14 15 16 0R 0.01uF C487 R423

22R 0.1W 22R 0.1uF C492 0.01uF C464 U61

mill trace must be 50 0.1uF C469 G2 G1 H2 H1 D8 C9 C8 D9 K2 E9 K3 A1 E1 B2 B4 A3 A2 A4 A5 B3 B9 A9 B8 A8 B7 A7 B6 B5 A6 E8 F7 F2 F1 J2 J1 +3.3V 0.01uF C465 VSSC XTAL1 XTAL2 SEL_2_5V RESET COMA TXD_7 TXD_6 TXD_5 TXD_4 TXD_3 TXD_2 TXD_1 TXD_0 TX_CLK TX_ER TX_EN CRS COL GTX_CLK CLK125 RXD_7 RXD_6 RXD_5 RXD_4 RXD_3 RXD_2 RXD_1 RXD_0 RX_CLK RX_ER RX_DV MDIO MDC INT 4 +3.3V 4 0.1uF C470

0.01uF C466 LED_YELLOW R1341 K7 0R R1342 CONFIG_6 0.1uF C471 2 1 J7 CONFIG_5

0R R1343 L9 3.3V 1.5V E3 LD28 0R R1344 CONFIG_4 DVDDL 0.01uF C467 K9 CONFIG_3 DVDDL H3

330R 0R R1345 K8 CONFIG_2 DVDDL D7

R429 0R R1346 J9 G7 0.1uF C472 0R R1347 CONFIG_1 DVDDL J8 CONFIG_0

0R 0.01uF C468 +2.5V

H9 LED_TX 2.5V AVDDL M3 F8 L2 0.1uF C473

LED_LINK10 AVDDL GEther G8 B1

LED_LINK1000 AVDDL 3PIN_FERRITE H8 LED_RX AVDDL M7 0.1uF C488 3 G9 LED_DPLX AVDDL M8

330R F9 88E1011S LED_LINK100 G1AVDDH L20 R432 AVDDH N5 M6 49R9 2 HDAC_N R406 49R9 HDAC_P M5 TP147 M4 R407 1 LED_YELLOW TP148 CTRL25 TP145 E2 CTRL_15 DVDDH G3 2 1 M2 F3 2K49 R425 RSET DVDDH TP146 0.01uF C474

LD30 330R M9 TDI VDDO H7

R430 0.1uF C479 M1 TRST VDDO J3 R426 4K7 L1 TMS VDDO C5

10K 0.01uF C475 L8 TDO VDDO C6 K1 E7 LED_RED TCK VDDO 0.1uF C480 2 1

R424 0.01uF C476 G6 DGND DGND G4

LD31 330R J6 DGND DGND D6 R428 +3.3V 0.1uF C481 H4 DGND DGND L7 F4 L6 DGND DGND 0.01uF C477 G5 DGND DGND K6 E4 L5 LED_YELLOW DGND DGND 0.1uF C482 D5 DGND DGND K5 2 1 D4 DGND DGND J5

3 C4 L4 0.01uF C478 3 LD26 DGND DGND C7 DGND DGND E6

0.1uF C483 +3.3V E5 DGND DGND L3 H6 DGND DGND J4 F6 DGND DGND K4 H5 DGND DGND F5 SOUT_M SOUT_P SCLK_M SCLK_P MDI3_M MDI2_M MDI1_M MDI0_M MDI3_P MDI2_P MDI1_P MDI0_P SIN_M SIN_P N9 N7 N4 N2 D2 C3 D1 C2 N8 N6 N3 N1 D3 C1

C4960.01uF C4950.01uF C4940.01uF C4930.01uF CONFIG6 SEL_BDT INT_POL 75/50 OHMCONFIG6 SEL_BDT INT_POL 75/50 CONFIG5 DIS_FC DIS_SLEEP HWCFG_ CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_ CONFIG3 ANEG[0] ENA_XC D CONFIG2 ANEG[3] ANEG[2] A CONFIG1 ENA_PAUSE PHYADR[4] PHY OFG 0 1 1 0 CONFIG6 0 0 CONFIG5 1 0 CONFIG4 1 0 CONFIG3 0 CONFIG2 1 CONFIG1 0 CONFIG0 0 Bit[2] Bit[1] Bit[0] Pin CONFIG0 PHYADR[2] PHYADR[1] PHY Bit[2] Bit[1] Bit[0] Pin R421 49R9 49R9 R416 49R9 49R9 R414 49R9 49R9 R409 49R9 49R9 R418 R415 R410 R408 WP2_PH1_M3 WP2_PH1_P3 WP2_PH1_M2 WP2_PH1_P2 WP2_PH1_M1 WP2_PH1_P1 WP2_PH1_M0 WP2_PH1_P0 2 2 CONFIG6 VSS CONFIG5 VDDO CONFIG4 VDDO CONFIG3 VSS CONFIG2 LED_LINK10 CONFIG1 VSS CONFIG0 VSS Pin IS_125 NEG[1] D4D D2D 10D ADR[3] ADR[0] 1D 2D 4D 3D 6D 5D 8D 7D 9D MODE[3] MODE[0] LED flashing => Transmitting or Rece LED off => Link Down LED on => Link Up LED_TX is used as a global activity indica NOTE: When PHY register 24.2:0='111', LED off => Link Down LED on => Link Up LED_LINK1000 is used as a global link indica NOTE: When PHY register 24.4:3='01', RJG5- Setting 7G05 P5D VSS 0 0 VSS 0 0 0 LED_TX 0 1 1 LED_RX 0 0 1LED_DUPLEX 0 1 0LED_LINK1000 1 0 0LED_LINK100 1 1 1LED_LINK10 1 0 1 VDD0 1 1 Bit[2:0] Pin 1:1 1:1 1:1 1:1 D3D D1D ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K iving Page Title : Page +3.3V tor. Tuesday, September 30, Torridon - RapidIO Enabled Multi-Pr tor. Work ProcessorWork 2 - +1.5VGEther +2.5VGEther +3.3V Power 2003 1 1 +1.5VGEther +2.5VGEther +3.3V DGND iayeEhre nefc H 0.6 GigaByte Ethernet Interface - PHY ocessing System 272 42 DGND +1.5VGEther +2.5VGEther +3.3V of ilbride Rev C D A B

Figure A-40. GigaByte Ethernet Interface—PHY

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 4 4 M10 N11 N10 P10 P11 L11 L10 M1 M2 M3 M6 M7 M8 M9 R7 R6 R5 R4 R3 R2 R1 N9 N8 N7 N6 N5 N4 N1 H2 H1 P1 P2 P3 P4 P5 P6 P7 P8 P9 K1 K2 K3 K6 K7 K8 L9 L8 L5 L4 L3 L2 L1 J8 J7 J6 J5 J4 J3 J2 J1 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17/FEC_RX_DV PB16/FEC_RX_ER PB15/FEC_TX_ER PB14/FEC_TX_EN PB13/FEC_COL PB12/FEC_CRS PB11/FEC_RXD3 PB10/FEC_RXD2 PB9/FEC_RXD1 PB8/FEC_RXD0 PB7/FEC_TXD0 PB6/FEC_TXD1 PB5/FEC_TXD2 PB4/FEC_TXD3 PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 U7H MPC8560

Alt. DUART CPM Alt. 10/100 Eth.Alt. DUART PD30/UART_SOUT0 PD27/UART_SOUT1 PC17/FEC_RX_CLK PC18/FEC_TX_CLK PD29/UART_RTS0 PD26/UART_RTS1 PC15/UART_CTS0 PC13/UART_CTS1

PD31/UART_SIN0 PD28/UART_SIN1 Alt. 10/100 Eth. 3 3 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PC31 PC30 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC16 PC14 PC12 PC11 PC10 PD9 PD8 PD7 PD6 PD5 PD4 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 AE2 AD5 V9 AE3 AD2 V6 AC1 AC2 AC3 AC4 AC7 AB6 AB5 AB3 AB2 AB1 AA1 AA2 AA3 AA4 AA7 AA8 Y9 W9 W8 W7 W6 W3 W2 W1 V1 V2 V3 V4 V5 U10 U8 U4 U3 U2 Y6 Y5 Y4 Y3 Y2 Y1 U1 T1 T4 T5 T6 T9 R11 R10 R9 R8 AD6 AD1 U9 U7 WP2_TXD WP2_RXD WP2_RXD WP2_TXD 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Processor 2 - Communications Processor Work Processor 2 - Communications 1 1 ocessing System 372 43 of ilbride Module Rev 0.6 C D A B

Figure A-41. Work Processor 2—Communications Processor Module

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-42 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 2 5 JP37 5 1 MSRCID0 MDC MDIO +3.3V +3.3V R638 R637 +3.3V TP98 TP172 TP171 TP170 TP169 TP168 +3.3V TP94 WP2_HRESET_N WP2_HRESET_REQ_N WP2_SRE CHKSTOP_OUT_N CHKSTOP_IN_N 244K7 4K7 R244 R243 4K7 R242 R241 R233 0R 0R MDC MDIO SET_N ASLEEP MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT THERM1 THERM0 CLK_OUT 4K7 4K7 AG18 AG22 AG28 AG20 AG19 AH16 AH20 AH28 AH27 AH26 AH25 AB22 AE28 AF20 AF22 AF28 AG2 AG1 M11 AH3 AH2 AH1 N12 G1 G2 G3 E1 A3 A2 B2 B1 F4 F2 F5 F3 F1 J9 HRESET HRESET_REQ SRESET CKSTP_OUT CKSTP_IN ASLEEP TEST_SEL(Draco/Dracom) LSSD_MODE MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT/READY/QUIESCE TRIG_IN L2_TSTCLK THERM1 THERM0 CLK_OUT L1_TSTCLK EC_MDIO EC_MDC NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 U7D MPC8560 AUXILIARY FUNCTION PIC CLOCKING SPARES Eth.MI IRQ11/DMA_DDONE3 IRQ10/DMA_DACK3 4 CNTRL SYS. JTAG 4 IRQ9/DMA_DREQ3 I2C ANALOG DMA DMA_DDONE1 DMA_DDONE0 DMA_DREQ1 DMA_DREQ0 DMA_DACK1 DMA_DACK0 PWR Mng. PWR DFT IRQ_OUT SYSCLK SPARE4 SPARE3 SPARE2 SPARE1 IIC_SDA IIC_SCL TRST IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 MCP TMS TDO UDE RTC TCK TDI DEBUG AB23 AH23 AF23 AF19 AH21 C1 AF1 U11 T11 AB20 AG25 AA19 Y19 AA21 AG24 AB18 Y18 AA18 AF21 AH22 AG23 G6 H7 G5 H6 G4 H5 AB21 AH24 AF26 Y20 AG16 AG17 AG21 IRQ11_N IRQ10_N IRQ9_N IRQ8_N IRQ7_N IRQ6_N IRQ5_N G1_IRQ_N IRQ0_N MCP_N WP2_INT_N BP_INT_N WP3_INT_N WP1_INT_N UDE_N I2C_SDA I2C_SCL WP2_RTC_CLK WP2_SYS_CLK 10K, RN 10K, RN147 TCK TMS WP2_T TDO TDI 1 TP93 TP92 TP91 TP90 2 3 RST_N

4 5 +3.3V

4K7 R629 +3.3V 6 10 7 8

10K R707 9 WP2_SYS_CLK WP2_RTC_CLK 4K7 R630 +3.3V I2C_SCL I2C_SDA +3.3V

3 1 3 2 BP_INT_N WP3_INT_N WP1_INT_N G1_IRQ_N 3 5 4 10 6 7 8 9 RN148 10K, RN CHKSTOP_OUT_N WP2_COP_HRESET_N WP2_COP_SR TMS TCK TDO TDI WP2_INT_N ESET_N +3.3V 10K R234 10K R235 10K R236 10K R237 15 13 11 9 7 5 3 1 2x8 Header HD12 2 2 WP2_HRESET_REQ_N WP2_COP_TRST_N WP2_T WP2_COP_SR WP2_COP_HRESET_N WP2_HRESET_N WP2_SRE 16 14 12 10 8 6 4 2 KEY KEY RST_N +3.3V SET_N 10K R238 ESET_N 2K R239 10K R240 CHKSTOP_IN_N WP2_COP_ TRST_N WP2_HRESET_R WP2_COP_ WP2_ WP2_COP_SR WP2_COP_HRES WP2_HRESET_N WP2_SR TRST_N ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K ESET_N TRST_N ESET_N Page Title : Page Friday, September 26, 2003 EQ_N ET_N Torridon - RapidIO Enabled Multi-Pr Work P oesr2-Axlr ucin 0.6 rocessor 2 - Auxilary Functions 1 1 +3.3V Power ocessing System +3.3V DGND 472 44 DGND +3.3V of ilbride Rev C D A B

Figure A-42. Work Processor 2—Auxiliary Functions

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5

"CONFIGURATION" TSEC Memory PCI/RIO Processor RIO Processor RIO "Device ID7" "Device ID6" "Device ID5" "Device ID3" "Device ID2" "Device ID1" "Device ID0" "RIO Clk 1" "RIO Clk 0" "Core "Core "Sys "Sys "Sys "Sys "TSEC1 Mode" "Debug Enable" "Host/Agent 1" "Host/Agent 0" "CPU Boot" Loc.2" "ROM Loc.0" "ROM "Device Loc.1" "ROM PLL3" PLL2" PLL1" PLL0" PLL1" PLL0" ID4" 4 4 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 SW DIP-8 SW SW11 DIP-8 SW SW10 DIP-8 SW SW9 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 10K, RN RN68 1 2

3 +3.3V 4 5 6 10

WP2_RST_CONF_N 7 8 9 10K, RN 10K, RN110 RN 10K, RN109 1 1 2 2

3 +3.3V 3 +3.3V 4 5 4 5 6 10 6 10 7 7 8 8 9 9 74LVC 19 24 25 48 17 15 13 11 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 1 1 8 6 4 2 3 3 U32 U31 2OE 2A4 2A3 2A2 2A1 1OE 1A4 1A3 1A2 1A1 OE4 4A4 4A3 4A2 4A1 OE3 3A4 3A3 3A2 3A1 OE2 2A4 2A3 2A2 2A1 OE1 1A4 1A3 1A2 1A1 H244 4 DGND 10 DGND 74ALVT16244 +3.3V +3.3V VCC 15 7

GND DGND 3V3 10 20 21 DGND 3V3 18 28 DGND 3V3 31 34 DGND 3V3 42 39 DGND 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 45 DGND 4Y4 4Y3 4Y2 4Y1 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 3 5 7 9 12 14 16 18 23 22 20 19 17 16 14 13 12 11 9 8 6 5 3 2 R755 R754 R753 R752 R751 R750 R749 Do Not Fit 0R 0R G1TXD4 G1TXD5 G1TXD6 G1TXD7 G2TXD4 G2TXD5 G2TXD6 G2TXD7 0R 0R 0R 0R 0R LGPL1 LGPL0 LGPL2 LALE BLA31 BLA30 BLA29 BLA28 BLA27 G1GTXCLK MSRCID0 LWE_N3 LWE_N2 BLA27 LCS_N2 LCS_N1 LCS_N0 G2TXD2 G2TXD3 G1GTXCLK MSRCID0 G2TXD[7:4] G1TXD[7:4] LGPL1 LGPL0 LGPL2 LALE BLA[27 LWE_N[2:3] LCS_N[0:2] :31] 2 2

Decoupling +3.3V C663 0.1uF +3.3V C664

0.1uF Add R749,R750 Remove R751,R752,R753,R754, For Rev 2 silicon; Note : Configuration shown is for Rev 1 Sili G2TXD2 G2TXD3 G2TXD4 G2TXD5 G2TXD6 G2TXD7 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Monday, September 08, 2003 G2TXD[7:2] Torridon - RapidIO Enabled Multi-Pr R755 okPoesr2-Cniuain0.6 Work Processor 2 - Configuration con. 1 1 +3.3V Power ocessing System +3.3V DGND 572 45 DGND +3.3V of ilbride Rev C D A B

Figure A-43. Work Processor 2—Power On Configuration

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-44 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 +3.3V AG27 AC17 AC11 AB11 AB26 AA20 AA16 AE15 AA12 AE10 AF10 AF12 W21 W19 W13 AG7 AG3 M12 AC9 AD8 AC6 AD3 AC5 AD4 AH4 G12 AA6 AB4 AB9 AE8 AB7 AA5 AE1 H12 C11 AF4 AF2 U26 R25 U20 R19 AF7 P12 V10 Y23 P22 K10 T12 F11 T10 W5 W4 M4 M5 G9 D8 U6 C4 H4 C2 N2 U5 H3 N3 D1 K9 Y8 V7 K5 B3 E3 V8 Y7 E4 K4 T8 T3 T7 T2 L6 L7 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 OVdd42 OVdd41 OVdd40 OVdd39 OVdd38 OVdd37 OVdd36 OVdd35 OVdd34 OVdd33 OVdd32 OVdd31 OVdd30 OVdd29 OVdd28 OVdd27 OVdd26 OVdd25 OVdd24 OVdd23 OVdd22 OVdd21 OVdd20 OVdd19 OVdd18 OVdd17 OVdd16 OVdd15 OVdd14 OVdd13 OVdd12 OVdd11 OVdd10 OVdd9 OVdd8 OVdd7 OVdd6 OVdd5 OVdd4 OVdd3 OVdd2 OVdd1 U7I MPC8560 POWER GND99 GND98 GND97 GND96 GND95 GND94 GND93 GND92 GND91 GND90 GND89 GND88 GND87 GND86 GND85 GND84 GND83 GND82 GND81 GND80 GND79 GND78 GND77 GND76 GND75 GND74 GND73 GND72 GND71 GND70 GND69 GND68 GND67 GND66 GND65 GND64 GND63 GND62 GND61 GND60 GND59 GND58 GND57 GND56 GND55 GND54 GND53 GND52 GND51 GND50 GND49 GND48 GND47 GND46 GND45 GND44 GND43 GND42 GND41 GND40 K28 B27 C27 H27 M27 AF27 B26 R26 V26 AG26 G25 L25 E24 J24 F23 K23 P23 W23 C22 H22 M22 U21 B20 H20 L20 R20 C19 J19 AB19 F18 K18 W18 A17 C17 H17 N17 R17 U17 AD17 M16 P16 T16 U16 Y16 N15 R15 U15 AF15 B14 H14 M14 P14 T14 N13 R13 U13 AA13 AF13 A12 E12 4 4

Decoupling +3.3V +3.3V +3.3V C725 C718 C711 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C726 C719 C712 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C727 C720 C713 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C728 C721 C714 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C729 C722 C715 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C730 C723 C716 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V Vdd C731 C724 C717 0.1uF 0.1uF 0.1uF M17 M15 M13 N16 R16 N14 R14 U14 R12 U12 P17 P15 P13 T17 T15 T13 3 +3.3V 3 C959 10uF, 6.3V VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 U7E MPC8560 Supply CORE &PLL Bulk Decoupling Decoupling +3.3V +3.3V SENSE_VDD 2 1C1140 C1082 SENSE_VSS + 220uF, Tants 10uF,6.3V Tants AVdd3 AVdd2 AVdd1 +3.3V 2 1C1141

220uF, Tants AH17 AH18 AH19 K12 L12 TP181 TP180

Decoupling Vdd Vdd C1130 C703 0.1uF 0.1uF C1258 C1257 C1256

Vdd Vdd 0.1uF 0.1uF 0.1uF C1131 C704 0.1uF 0.1uF C308 C306 C304 Vdd Vdd C1132 C705 2.2uF 2.2uF 2.2uF 0.1uF 0.1uF

2 Vdd Vdd C309 C307 C305 2 C1133 C706

0.1uF 0.1uF 2.2uF 10R 2.2uF 10R 2.2uF 10R R266 R265 R264 Vdd Vdd C1134 C707 0.1uF 0.1uF Vdd Vdd Vdd Vdd Vdd C1135 C708 0.1uF 0.1uF Vdd Vdd C1136 C709 0.1uF 0.1uF Vdd Vdd C1137 C710 0.1uF 0.1uF Vdd C958

10uF, 6.3V

Bulk Decoupling Decoupling Vdd Vdd 2 1C1138 C1081 + ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 220uF, Tants 10uF,6.3V Tants Vdd 2 1C1139 Page Title : Page Wednesday, October 01, 2003

Torridon - RapidIO Enabled Multi-Pr 220uF, Tants Work Processor 2 - 12V fan Header for 2 HS7 10-THMA-01 1 1 1 Power HD20 oe 0.6 Power Vdd +3.3V +12V S6 S5 DO57 DO57 1 Ferrite Bead L32 ocessing System Vdd +3.3V +12V DGND 2 672 46 +12V DGND Vdd +3.3V +12V of ilbride Rev C D A B

Figure A-44. Work Processor 2—Power

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B WP3_HRESET_REQ_N WP3_COP_SRESET_N WP3_COP_HRESET_N WP3_COP_T WP3_HRESET_N WP3_SRE WP3_SYS_CLK WP3_RTC_CLK WP3_T BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N 5 5 RST_N RST_N SET_N DGND MSRCID0 +3.3V WP3_RTC_CLK WP3_HRESET_REQ_N WP3_COP_T WP1_T WP3_COP_SRESET_N WP3_COP_HRESET_N WP3_HRESET_N WP3_SRE WP3_SYS_CLK BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RST_N SET_N RST_N +3.3V DGND WP3 - CPM Page 55 WP3 - AUX Page 51 WP3_SYS_CLK WP3_RTC_CLK MSRCID0 WP3_HRESET_REQ_N WP3_COP_TRST_N WP3_TRST_N WP3_COP_SRESET_N WP3_COP_HRESET_N WP3_HRESET_N WP3_SRESET_N DGND +3.3V BP_INT_N WP3_INT_N WP2_INT_N WP1_INT_N RIO3_TXCLK_IN_N RIO3_TXCL K_IN G1_IRQ_N RIO3_TXCLK_IN_N RIO3_TXCL WP3_RXD WP3_TXD I2C_SDA I2C_SCL MDIO MDC 4 4 K_IN WP3 - RIO Page 50 WP3_RXD WP3_TXD RIO3_TXCLK_IN_N RIO3_TXCLK_IN G1GTXCLK MDC G1_IRQ_N I2C_SCL I2C_SDA MDIO G2TXD[7:2] G1TXD[7:4] WP3 - TSEC Top Page 47 WP3 - DDR SDRAM Page 44 RIO3_RFRAME_N RIO3_TFRAME_N WP3_RXD WP3_TXD G1GTXCLK G2TXD[7:2] G1TXD[7:4] MDIO MDC G1_IRQ_N I2C_SDA I2C_SCL RIO3_RD_N[0:7] RIO3_TD_N[0:7] RIO3_RFRAME RIO3_TFRAME RIO3_RCLK_N RIO3_TCLK_N RIO3_RD[0:7] RIO3_TD[0:7] RIO3_RCLK RIO3_TCLK RIO3_RCLK_N RIO3_RCLK RIO3_RFRAME_N RIO3_RFRAME RIO3_TCLK RIO3_TFRAME_N RIO3_TFRAME WP3_G1_RESET_N RIO3_TCLK_N RIO3_R RIO3_R RIO3_TD_N[0:7] RIO3_TD[0:7] +1.5VGEther +2.5VGEther D_N[0:7] D[0:7] CGND DGND DGND +3.3V +2.5V +3.3V 3 3 WP3_G1_ +1.5 +2.5 +3.3V +2.5V +3.3V CGND DGND DGND RIO3_RD_N[0:7] RIO3_R RIO3_RCLK_N RIO3_RCLK RIO3_RFRAME_N RIO3_RFRAME RIO3_TD_N[0:7] RIO3_TD[0:7] RIO3_TCLK_N RIO3_TCLK RIO3_TFRAME_N RIO3_TFRAME VGEther VGEther RESET_N D[0:7] +2.5V +3.3V DGND +1.5VGE +2.5VGE +3.3V CGND DGND WP3_G1_ ther ther RESET_N WP3_RST_CONF_N DGND LGPL2 LGPL1 LGPL0 LALE BLA[27:31] LCS_N[0:2] LWE_N[2:3] +3.3V 2 2 WP3_RST_CONF_N +3.3V DGND WP3 - Page 57 WP3 - Local Bus Page 48 WP3 - PCI Page 49 - Power WP3 Page 58 WP3_RST_CONF_N DGND +3.3V LGPL2 LGPL1 LGPL0 LALE BLA[27:31] LCS_N[0:2] LWE_N[2:3] Config ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K LWE_N[2:3] G1GTXCLK G2TXD[7:2] G1TXD[7:4] LCS_N[0:2] BLA[27:31] MSRCID0 LGPL2 LGPL1 LGPL0 Page T DGND Monday, September 08, 2003 +3.3V LALE +12V Torridon - RapidIO Enabled Multi-Pr Vdd itle : okPoesr3-TpLvl0.6 Processor 3 - Top Level Work +12V Vdd +3.3V DGND G1GTXCLK LGPL2 LGPL1 LGPL0 LALE MSRCID0 G2TXD[7:2] G1TXD[7:4] LCS_N[0:2] LWE_N[2:3] BLA[27:31] 1 1 +12V Vdd +3.3V DGND ocessing System 772 47 of ilbride Rev C D A B

Figure A-45. Work Processor 3—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-46 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 4 4 LGPL4/LGTA/LUPWAIT/LPBSE LOCAL BUS LOCAL LCS7/DMA_DDONE2 LGPL2/LOE/LSDRAS LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LGPL3/LSDCAS LGPL0/LSDA10 LGPL1/LSDWE LSYNC_OUT LWE3/LBS3 LWE2/LBS2 LWE1/LBS1 LWE0/LBS0 U6F MPC8560 LSYNC_IN LGPL5 LBCTL LCLK2 LCLK1 LCLK0 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LCKE LCS4 LCS3 LCS2 LCS1 LCS0 LDP3 LDP2 LDP1 LDP0 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 LALE LA31 LA30 LA29 LA28 LA27 U19 V20 T28 V21 V18 U28 U27 N26 N25 N24 N23 N22 P18 P19 P20 P25 P26 R18 R21 R22 R23 R24 T22 V19 W26 W22 W20 Y26 Y22 T27 V22 P21 T26 AA28 AA27 Y21 AA26 AA23 AA22 AC28 AC27 AC26 AD28 AD27 AD26 P28 P27 R28 R27 W28 W27 Y28 Y27 P24 T23 AB27 AB28 V23 V27 V28 U22 U23 T21 T20 T19 T18 U18 LALE BLA31 BLA30 BLA29 BLA28 BLA27 LWE_N3 LWE_N2 LGPL2 LGPL1 LGPL0 LCS_N2 LCS_N1 LCS_N0 TP270 TP269 3 3 LALE LCS_N[0:2] BLA[27:31] LWE_N[2:3] LGPL2 LGPL1 LGPL0 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr okPoesr3-LclBs0.6 Work Processor 3 - Local Bus 1 1 ocessing System 872 48 of ilbride Rev C D A B

Figure A-46. Work Processor 3—Local Bus

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B TP71 TP70 TP69 TP68 TP67 TP66

Decoupling VREF3 +2.5V +2.5V +2.5V +2.5V C801 C796 C779 C774 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V 3MCK_N5 3MCK5 3MCK_N4 3MCK4 3MCK_N3 3MCK_3 3MCK_N2 3MCK2 3MCK_N1 3MCK1 3MCK_N0 3MCK0 3MCKE1 3MCKE0 3MCS3_N 3MCS2_N 3MCS1_N 3MCS0_N 3MCAS_N 3MRAS_N 3MWE_N 3MBA1 3MBA0 3MA14 3MA13 3MA12 3MA11 3MA10 3MA9 3MA8 3MA7 3MA6 3MA5 3MA4 3MA3 3MA2 3MA1 3MA0 3MDQS8 3MDQS7 3MDQS6 3MDQS5 3MDQS4 3MDQS3 3MDQS2 3MDQS1 3MDQS0 3MDM8 3MDM7 3MDM6 3MDM5 3MDM4 3MDM3 3MDM2 3MDM1 3MDM0 3MECC7 3MECC6 3MECC5 3MECC4 3MECC3 3MECC2 3MECC1 3MECC0 2 1 C802 C797 C780 C775 +

0.1uF C141 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V

VTT3_Sence C803 C798 C781 C776 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V C804 C799 C782 C777 0.1uF 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V +2.5V

C805 C800 C783 C778 R1298 R1296 R1294 R1292 R1290 R1288 R1286 R1284 R1282 R1280 R1278 R1276 R1274 R1272 R1270 R1268 R1266 R1264 R1262 R1260 R1258 R1256 R1254 R1252 R1250 R1248 R1246 R1244 R1242 R1240 R1238 R1236 R1234 R1232 R1230 R1228 R1226 R1224 R1222 R1220 R1218 R1216 R1214 R1212 R1210 R1208 R1206 R1204 R1202 R1200 R1198 R1196 R1194 R1192 R1190 R1188 R1186 R1184 R1182 R1180 R1178 R1176 R1174 R1172 R1170

4 3 2 1 0.1uF 0.1uF 0.1uF 0.1uF 5 5 VREF VSENSE GND NC U33 LP2995 LP2995 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R Place Near Pin N27 Decoupling Decoupling VREF3 +2.5V VREF3 3MSYNC_IN 3MSYNC_OUT

VDDQ C1005 C1078 Decoupling VREF3 + AVIN PVIN VTT

0.1uF VREF3 10uF,6.3V Tants C1004 3NCK5 3NCK4 3NCK3 3NCK2 3NCK1 3NCK0 3CKE1 3CKE0 3CAS_N 3RAS_N 3BA1 3BA0 3A14 3A13 3A12 3A11 3A10 3A9 3A8 3A7 3A6 3A5 3A4 3A3 3A2 3A1 3A0 3DQS8 3DQS7 3DQS6 3DQS5 3DQS4 3DQS3 3DQS2 3DQS1 3DQS0 3DM8 3DM7 3DM6 3DM5 3DM4 3DM3 3DM2 3DM1 3DM0 3ECC7 3ECC6 3ECC5 3ECC4 3ECC3 3ECC2 3ECC1 3ECC0 3CK5 3CK4 3CK3 3CK2 3CK1 3CK0 3CS3_N 3CS2_N 3CS1_N 3CS0_N 3WE_N

VREF3 0.1uF 5 8 6 7 C1006 0.01uF M28 M21 M19 M20 G27 G16 G24 G14 G19 N27 N28 D20 H25 H15 H16 D17 D27 H23 C23 N19 C20 C13 H18 D25 H28 C21 N20 K14 E20 B15 A15 E28 E26 B19 B18 B25 K19 B24 A23 K21 B21 A22 B13 E16 E18 A19 A21 E19 F27 F28 F20 F17 F21 F14 F16 F24 L14 L26 L21 L24 L19 J20 J15 J16 J13 J14 J25

2 1 MVREF(GVdd/2) MSYNC_IN MSYNC_OUT MCK5- MCK5 MCK4- MCK4 MCK3- MCK3 MCK2- MCK2 MCK1- MCK1 MCK0- MCK0 MCKE1 MCKE0 MCS3- MCS2- MCS1- MCS0- MCAS- MRAS- MWE- MBA1 MBA0 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MDQS8 MDQS7 MDQS6 MDQS5 MDQS4 MDQS3 MDQS2 MDQS1 MDQS0 MDM8 MDM7 MDM6 MDM5 MDM4 MDM3 MDM2 MDM1 MDM0 MECC7 MECC6 MECC5 MECC4 MECC3 MECC2 MECC1 MECC0 47uF, Tants U6B MPC8560 C139 +2.5V D SDRAM DDR

2 1 220uF, Tants C140 VTT3 1.25V @ GVdd41 GVdd40 GVdd39 GVdd38 GVdd37 GVdd36 GVdd35 GVdd34 GVdd33 GVdd32 GVdd31 GVdd30 GVdd29 GVdd28 GVdd27 GVdd26 GVdd25 GVdd24 GVdd23 GVdd22 GVdd21 GVdd20 GVdd19 GVdd18 GVdd17 GVdd16 GVdd15 GVdd14 GVdd13 GVdd12 GVdd11 GVdd10 MDQ63 MDQ62 MDQ61 MDQ60 MDQ59 MDQ58 MDQ57 MDQ56 MDQ55 MDQ54 MDQ53 MDQ52 MDQ51 MDQ50 MDQ49 MDQ48 MDQ47 MDQ46 MDQ45 MDQ44 MDQ43 MDQ42 MDQ41 MDQ40 MDQ39 MDQ38 MDQ37 MDQ36 MDQ35 MDQ34 MDQ33 MDQ32 MDQ31 MDQ30 MDQ29 MDQ28 MDQ27 MDQ26 MDQ25 MDQ24 MDQ23 MDQ22 MDQ21 MDQ20 MDQ19 MDQ18 MDQ17 MDQ16 MDQ15 MDQ14 MDQ13 MDQ12 MDQ11 MDQ10 GVdd9 GVdd8 GVdd7 GVdd6 GVdd5 GVdd4 GVdd3 GVdd2 GVdd1 MDQ9 MDQ8 MDQ7 MDQ6 MDQ5 MDQ4 MDQ3 MDQ2 MDQ1 MDQ0 J28 K22 K26 K27 M23 M24 K24 L22 L27 M26 A28 B28 C28 D28 G28 L28 A27 J27 A26 A25 F25 K25 M25 D24 H24 G23 L23 B22 E22 J22 D21 N21 A20 G20 K20 D19 F19 H19 G18 B17 E17 J17 D16 F15 K15 A14 G13 L13 C12 F12 J12 B12 A13 H13 F13 A11 D12 E13 D13 D14 E14 D15 C15 K13 C14 E15 G15 L15 A16 L16 G17 B16 C16 K16 K17 A18 C18 L18 M18 L17 D18 J18 N18 E21 H21 D22 G22 G21 J21 F22 B23 D23 A24 C25 D26 E23 C24 E25 C26 G26 H26 J23 J26 E27 F26 1.5A +2.5V 3DQ63 3DQ62 3DQ61 3DQ60 3DQ59 3DQ58 3DQ57 3DQ56 3DQ55 3DQ54 3DQ53 3DQ52 3DQ51 3DQ50 3DQ49 3DQ48 3DQ47 3DQ46 3DQ45 3DQ44 3DQ43 3DQ42 3DQ41 3DQ40 3DQ39 3DQ38 3DQ37 3DQ36 3DQ35 3DQ34 3DQ33 3DQ32 3DQ31 3DQ30 3DQ29 3DQ28 3DQ27 3DQ26 3DQ25 3DQ24 3DQ23 3DQ22 3DQ21 3DQ20 3DQ19 3DQ18 3DQ17 3DQ16 3DQ15 3DQ14 3DQ13 3DQ12 3DQ11 3DQ10 3DQ9 3DQ8 3DQ7 3DQ6 3DQ5 3DQ4 3DQ3 3DQ2 3DQ1 3DQ0 4 4 Bulk Decoupling +2.5V 2 1C1173 Decoupling +2.5V +2.5V +2.5V R1297 R1295 R1293 R1291 R1289 R1287 R1285 R1283 R1281 R1279 R1277 R1275 R1273 R1271 R1269 R1267 R1265 R1263 R1261 R1259 R1257 R1255 R1253 R1251 R1249 R1247 R1245 R1243 R1241 R1239 R1237 R1235 R1233 R1231 R1229 R1227 R1225 R1223 R1221 R1219 R1217 R1215 R1213 R1211 R1209 R1207 R1205 R1203 R1201 R1199 R1197 R1195 R1193 R1191 R1189 R1187 R1185 R1183 R1181 R1179 R1177 R1175 R1173 R1171 220uF, Tants C1279 C1272 C1265

+2.5V 0.1uF 0.1uF 0.1uF

2 1C1174 +2.5V +2.5V +2.5V C1280 C1273 C1266 220uF, Tants 0.1uF 0.1uF 0.1uF 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R +2.5V +2.5V +2.5V C1281 C1274 C1267 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1282 C1275 C1268 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1283 C1276 C1269 0.1uF 0.1uF 0.1uF 3MDQ63 3MDQ62 3MDQ61 3MDQ60 3MDQ59 3MDQ58 3MDQ57 3MDQ56 3MDQ55 3MDQ54 3MDQ53 3MDQ52 3MDQ51 3MDQ50 3MDQ49 3MDQ48 3MDQ47 3MDQ46 3MDQ45 3MDQ44 3MDQ43 3MDQ42 3MDQ41 3MDQ40 3MDQ39 3MDQ38 3MDQ37 3MDQ36 3MDQ35 3MDQ34 3MDQ33 3MDQ32 3MDQ31 3MDQ30 3MDQ29 3MDQ28 3MDQ27 3MDQ26 3MDQ25 3MDQ24 3MDQ23 3MDQ22 3MDQ21 3MDQ20 3MDQ19 3MDQ18 3MDQ17 3MDQ16 3MDQ15 3MDQ14 3MDQ13 3MDQ12 3MDQ11 3MDQ10 3MDQ9 3MDQ8 3MDQ7 3MDQ6 3MDQ5 3MDQ4 3MDQ3 3MDQ2 3MDQ1 3MDQ0 +2.5V +2.5V +2.5V C1284 C1277 C1270 0.1uF 0.1uF 0.1uF +2.5V +2.5V +2.5V C1285 C1278 C1271 0.1uF 0.1uF 0.1uF I2C_SDA I2C_SCL Place Near Pin Place Near Pin 1 Decoupling VREF3

3 C1002 3 0.1uF VREF3 C1003

+3.3V 0.01uF VddSPD I2C_SCL I2C_SDA 3MDQ59 3MDQ58 3MDQS7 3MDQ57 3MDQ56 3MDQ51 3MDQ50 3MDQS6 3MDQ49 3MDQ48 3MDQ43 3MDQ42 3MDQS5 3MDQ41 3MDQ40 3MDQ35 3MDQ34 3MDQS4 3MDQ33 3MDQ32 3MCS0_N 3MWE_N 3MBA0 3MA10 3MA1 3MA3 3MA5 3MA7 3MA9 3MA12 3MCKE1 3MCK_N0 3MCK0 3MECC3 3MECC2 3MDQS8 3MECC1 3MECC0 3MDQ27 3MDQ26 3MDQS3 3MDQ25 3MDQ24 3MDQ19 3MDQ18 3MDQS2 3MDQ17 3MDQ16 3MCK_N1 3MCK1 3MDQ11 3MDQ10 3MDQS1 3MDQ9 3MDQ8 3MDQ3 3MDQ2 3MDQS0 3MDQ1 3MDQ0 VREF3 +2.5V

Decoupling Decoupling VTT3 VTT3

199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 107 105 103 101 C1067 C1059 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11

9 7 5 3 1 0.1uF 0.1uF P19 VTT3 VTT3 DDR SODIMM DDR C1068 C1060 0.1uF 0.1uF VTT3 VTT3 C1069 C1061

200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0.1uF 0.1uF VTT3 VTT3 C1070 C1062 0.1uF 0.1uF +2.5V VTT3 VTT3 C1071 C1063 0.1uF 0.1uF VTT3 VTT3 3MDQ63 3MDQ62 3MDM7 3MDQ61 3MDQ60 3MDQ55 3MDQ54 3MDM6 3MDQ53 3MDQ52 3MCK2 3MCK_N2 3MDQ47 3MDQ46 3MDM5 3MDQ45 3MDQ44 3MDQ39 3MDQ38 3MDM4 3MDQ37 3MDQ36 3MCS1_N 3MCAS_N 3MRAS_N 3MBA1 3MA0 3MA2 3MA4 3MA6 3MA8 3MA11 3MCKE0 3MECC7 3MECC6 3MDM8 3MECC5 3MECC4 3MDQ31 3MDQ30 3MDM3 3MDQ29 3MDQ28 3MDQ23 3MDQ22 3MDM2 3MDQ21 3MDQ20 3MDQ15 3MDQ14 3MDM1 3MDQ13 3MDQ12 3MDQ7 3MDQ6 3MDM0 3MDQ5 3MDQ4 VREF3 C1072 C1064 0.1uF 0.1uF VTT3 VTT3 C1073 C1065 Do Not Fit 0.1uF 0.1uF VTT3 VTT3 R198 R195 C1074 C1066 +

2 4K7 10K +3.3V 0.1uF 2 R199 R196 10uF,6.3V Tants 4K7 10K R200 R197 4K7 10K MT18VDDT6472 SODIMM4 199(200) 41(42) 39(40) 1(2) 200-pin DDR SDRAM SODIMM 3MA1 3MA0 3MA3 3MA2 3MA5 3MA4 3MA7 3MA6 3MA9 3MA8 3MA12 3MA11 3MCKE1 3MCKE0 3MECC3 3MECC7 3MECC2 3MECC6 3MDQS8 3MDM8 3MECC1 3MECC5 3MECC0 3MECC4 3MDQ27 3MDQ31 3MDQ26 3MDQ30 3MDQS3 3MDM3 3MDQ25 3MDQ29 3MDQ24 3MDQ28 3MDQ19 3MDQ23 3MDQ18 3MDQ22 3MDQS2 3MDM2 3MDQ17 3MDQ21 3MDQ16 3MDQ20 3MDQ11 3MDQ15 3MDQ10 3MDQ14 3MDQS1 3MDM1 3MDQ9 3MDQ13 3MDQ8 3MDQ12 3MDQ3 3MDQ7 3MDQ2 3MDQ6 3MDQS0 3MDM0 3MDQ1 3MDQ5 3MDQ0 3MDQ4

Decoupling Decoupling VTT3 VTT3 C1007 C784 ae Sheet Date: Size : System

C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 0.1uF 0.1uF 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 VTT3 VTT3 C1008 C785 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN

Page Title : Page 0.1uF 0.1uF Wednesday, October 01, 2003 VTT3 VTT3 RN234 RN232 RN141 RN139 RN133 RN129 RN125 RN119 Torridon - RapidIO Enabled Multi-Pr C1009 C786 0.1uF 0.1uF 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 VTT3 VTT3 VTT3 Work Pr C1010 C787 + 0.1uF

10uF,6.3V Tants VTT3

C788 VTT3_Sence cso D DA 0.6 ocessor 3 - DDR SDRAM

0.1uF Tap VTT Sence from middle VTT3 C789

1 0.1uF 1 3MA14 3MA13 3MCS3_N 3MCS2_N 3MDQ59 3MDQ63 3MDQ58 3MDQ62 3MDQS7 3MDM7 3MDQ57 3MDQ61 3MDQ56 3MDQ60 3MDQ51 3MDQ55 3MDQ50 3MDQ54 3MDQS6 3MDM6 3MDQ49 3MDQ53 3MDQ48 3MDQ52 3MDQ43 3MDQ47 3MDQ42 3MDQ46 3MDQS5 3MDM5 3MDQ41 3MDQ45 3MDQ40 3MDQ44 3MDQ35 3MDQ39 3MDQ34 3MDQ38 3MDQS4 3MDM4 3MDQ33 3MDQ37 3MDQ32 3MDQ36 3MCS0_N 3MCS1_N 3MWE_N 3MCAS_N 3MBA0 3MRAS_N 3MA10 3MBA1 VTT3 C790 0.1uF +2.5V +3.3V Power VTT3 ocessing System C791 0.1uF +2.5V +3.3V VTT3 DGND

C792 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

972 49 0.1uF 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN 27R, RN VTT3

C793 RN233 RN142 RN140 RN134 RN130 RN126 RN120 0.1uF of +2.5V +3.3V VTT3 ilbride DGND

C794 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16

0.1uF VTT3 VTT3

Rev C795 0.1uF C D A B

Figure A-47. Work Processor 3—DDR SDRAM

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-48 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 RIO3_TXCLK_IN_N RIO3_TXCL K_IN RIO3_TXCLK_ RIO3_TXCL K_IN 4 4 IN_N AF25 AF24 MPC8560 RIO_TXCLK_IN- RIO_TXCLK_IN U6C RIO_RFRAME- RIO_TFRAME- RIO_RFRAME RIO_TFRAME RIO_RCLK- RIO_TCLK- RIO_RCLK RIO_TCLK RIO_RD7- RIO_RD6- RIO_RD5- RIO_RD4- RIO_RD3- RIO_RD2- RIO_RD1- RIO_RD0- RIO_TD7- RIO_TD6- RIO_TD5- RIO_TD4- RIO_TD3- RIO_TD2- RIO_TD1- RIO_TD0- RIO_RD7 RIO_RD6 RIO_RD5 RIO_RD4 RIO_RD3 RIO_RD2 RIO_RD1 RIO_RD0 RIO_TD7 RIO_TD6 RIO_TD5 RIO_TD4 RIO_TD3 RIO_TD2 RIO_TD1 RIO_TD0 AE27 Y25 AD23 AC22 AE22 AD21 AE20 AD19 AC18 AE18 AE25 AD25 AC25 AB25 AA25 W25 V25 U25 T25 AE26 AC23 AE23 AD22 AC21 AD20 AC19 AE19 AD18 AE24 AE21 AD24 AC24 AB24 AA24 W24 V24 U24 T24 AC20 Y24 RIO3_RD_N7 RIO3_RD7 RIO3_RD_N6 RIO3_RD6 RIO3_RD_N5 RIO3_RD5 RIO3_RD_N4 RIO3_RD4 RIO3_RD_N3 RIO3_RD3 RIO3_RD_N2 RIO3_RD2 RIO3_RD_N1 RIO3_RD1 RIO3_RD_N0 RIO3_RD0 RIO3_RFRAME_N RIO3_RFRAME RIO3_RCLK_N RIO3_RCLK RIO3_TFRAME_N RIO3_TFRAME RIO3_TCLK RIO3_TD_N7 RIO3_TD7 RIO3_TD_N6 RIO3_TD6 RIO3_TD_N5 RIO3_TD5 RIO3_TD_N4 RIO3_TD4 RIO3_TD_N3 RIO3_TD3 RIO3_TD_N2 RIO3_TD2 RIO3_TD_N1 RIO3_TD1 RIO3_TD_N0 RIO3_TD0 RIO3_TCLK_N 3 3 RIO3_RFRAME_N RIO3_RFRAME RIO3_RCLK_N RIO3_RCLK RIO3_ RIO3_R RD[0:7] D_N[0:7] RIO3_TFRAME_N RIO3_TFRAME RIO3_TCLK RIO3_TCLK_N RIO3_TD7 RIO3_TD6 RIO3_TD5 RIO3_TD4 RIO3_TD3 RIO3_TD2 RIO3_TD1 RIO3_TD0 RIO3_TD_N7 RIO3_TD_N6 RIO3_TD_N5 RIO3_TD_N4 RIO3_TD_N3 RIO3_TD_N2 RIO3_TD_N1 RIO3_TD_N0 RIO3_RFRAME_N RIO3_RFRAME RIO3_RCLK_N RIO3_RCLK RIO3_RD_N7 RIO3_RD_N6 RIO3_RD_N5 RIO3_RD_N4 RIO3_RD_N3 RIO3_RD_N2 RIO3_RD_N1 RIO3_RD_N0 RIO3_RD7 RIO3_RD6 RIO3_RD5 RIO3_RD4 RIO3_RD3 RIO3_RD2 RIO3_RD1 RIO3_RD0 RIO3_TFRAME_N RIO3_TFRAME RIO3_TCLK_N RIO3_TCLK RIO3_TD[0:7] RIO3_TD_N[0:7] 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Work Processor 3 - RapidIO Interface 1 1 ocessing System 072 50 of ilbride Rev 0.6 C D A B

Figure A-48. Work Processor 3—RapidIO Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 4 4 AG10 AG13 AD13 AH10 AD10 AC10 AH13 AD11 AC12 AE13 AA11 AB10 W11 W14 AG6 AG5 AG4 AH5 AH8 AE6 AE5 AE4 AA9 AF6 AF3 AF5 Y11 V11 Y14 V14 PCI_GNT4 PCI_GNT3 PCI_GNT2 PCI_GNT1 PCI_GNT0 PCI_REQ4 PCI_REQ3 PCI_REQ2 PCI_REQ1 PCI_REQ0 PCI_SERR PCI_PERR PCI_ACK64 PCI_REQ64 PCI_IDSEL PCI_DEVSEL PCI_STOP PCI_IRDY PCI_TRDY PCI_FRAME PCI_PAR64 PCI_PAR PCI_C_BE7 PCI_C_BE6 PCI_C_BE5 PCI_C_BE4 PCI_C_BE3 PCI_C_BE2 PCI_C_BE1 PCI_C_BE0 U6A MPC8560 PCIX/PCI PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 AA14 AB14 AC14 AD14 AE14 AF14 AG14 AH14 V15 W15 Y15 AA15 AB15 AC15 AD15 AG15 AH15 V16 W16 AB16 AC16 AD16 AE16 AF16 V17 W17 Y17 AA17 AB17 AE17 AF17 AF18 AH6 AD7 AE7 AH7 AB8 AC8 AF8 AG8 AD9 AE9 AF9 AG9 AH9 W10 Y10 AA10 AE11 AF11 AG11 AH11 V12 W12 Y12 AB12 AD12 AE12 AG12 AH12 V13 Y13 AB13 AC13 3 3 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Pro cessor 3 - PCI Interface 1 1 ocessing System 172 51 of ilbride Rev 0.6 C D A B

Figure A-49. Work Processor 3—PCI Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-50 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 DGND +3.3V 4 4 DGND +3.3V WP3 - TSEC Page 53 DGND +3.3V G1RXD[7:0] G1GTXCLK G1TXD[7:0] G2TXD[7:2] G1RXCLK MGTX125 G1TXCLK G1RXER G1RXDV G1TXER G1TXEN G1CRS G1COL WP3_G1_ G2TXD[7:2] G1_IRQ_N G1TXD[7:4] RESET_N MDC MDIO 3 3 G1GTXCLK G1TXD[7:4] G2TXD[7:2] MGTX125 MDC WP3_G1_ G1_IRQ_N G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN MDIO G1COL G1RX G1TXD[7:0] D[7:0] RESET_N WP3 - Page 54 MDC MDIO WP3_G1_RESET_N G1_IRQ_N MGTX125 G1COL G1CRS G1RXCLK G1RXER G1RXDV G1GTXCLK G1TXCLK G1TXER G1TXEN G1RXD[7:0] G1TXD[7:0] TSEC - PHY +1.5VGEther +2.5VGEther CGND DGND +3.3V +1.5VGEther +2.5VGEther +3.3V CGND DGND 2 2 CGND DGND +1.5VGEther +2.5VGEther +3.3V ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Monday, September 08, 2003 Torridon - RapidIO Enabled Multi-Pr Work Processor 3 - GigaByte Ethernet Interface Top Work 1 1 ocessing System 272 52 of ilbride Rev 0.6 C D A B

Figure A-50. Work Processor 3—GigaByte Ethernet Interface—Top

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 +3.3V H10 C5 E7 A4

Decoupling LVdd4 LVdd3 LVdd2 LVdd1 +3.3V

C838 Clocking GbE TSEC2 TSEC1

0.1uF U6G +3.3V C839 TSEC2_GTX_CLK TSEC1_GTX_CLK EC_GTX_CLK125

0.1uF MPC8560 TSEC2_RX_CLK TSEC1_RX_CLK TSEC2_TX_CLK TSEC1_TX_CLK TSEC2_RX_ER TSEC2_RX_DV TSEC1_RX_ER TSEC1_RX_DV +3.3V TSEC2_TX_ER TSEC2_TX_EN TSEC1_TX_ER TSEC1_TX_EN TSEC2_RXD7 TSEC2_RXD6 TSEC2_RXD5 TSEC2_RXD4 TSEC2_RXD3 TSEC2_RXD2 TSEC2_RXD1 TSEC2_RXD0 TSEC1_RXD7 TSEC1_RXD6 TSEC1_RXD5 TSEC1_RXD4 TSEC1_RXD3 TSEC1_RXD2 TSEC1_RXD1 TSEC1_RXD0 C840 TSEC2_TXD7 TSEC2_TXD6 TSEC2_TXD5 TSEC2_TXD4 TSEC2_TXD3 TSEC2_TXD2 TSEC2_TXD1 TSEC2_TXD0 TSEC1_TXD7 TSEC1_TXD6 TSEC1_TXD5 TSEC1_TXD4 TSEC1_TXD3 TSEC1_TXD2 TSEC1_TXD1 TSEC1_TXD0 TSEC2_CRS TSEC1_CRS TSEC2_COL TSEC1_COL 0.1uF +3.3V C841 0.1uF C10 B6 E2 D10 C6 F8 G7 E10 D6 B10 A10 J10 K11 J11 H11 G11 E11 A6 F7 D7 C7 B7 A7 G8 E8 D11 B11 B8 C8 F9 E9 C9 B9 A9 H9 G10 F10 D4 B4 D3 D5 B5 A5 F6 E6 A8 H8 E5 D2 D9 C3 R462 R461 R460 8 7 6 5 4 3 2 1 RN166 22R, RN G1RXCLK G1RXER G1RXDV MGTX125 G2TXD7 G2TXD6 G2TXD5 G2TXD4 G2TXD3 G2TXD2 G1CRS G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 G1COL 22R 0.1W 22R 0.1W 22R 0.1W 22R 9 10 11 12 13 14 15 16 G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0 G1GTXCLK G1TXCLK G1TXER G1TXEN G1RX 4 4 D[7:0] G2TXD[7:2] G1COL G1CRS G1RXCLK G1RXER G1RXDV MGTX125 G1GTXCLK G1TXCLK G1TXER G1TXEN G1TXD[7:0] MGTX125 220R R463 +3.3V

330RR464

100pF C534 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G1RXD0 G1RXD1 G1RXD2 G1RXD3 G1RXD4 G1RXD5 G1RXD6 G1RXD7 G1RXD[7:0] 8 7 6 5 4 3 2 1 3R RN 330R, RN169 8 7 6 5 4 3 2 1 RN167 9 10 11 12 13 14 15 16 2R RN 220R, 3 3 9 10 11 12 13 14 15 16 100pF, CN 100pF, 4 3 2 1 4 3 2 1 +3.3V 100pF, CN CN19 5 6 7 8 5 6 7 8 CN17 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 G1TXD0 G1TXD1 G1TXD2 G1TXD3 G1TXD4 G1TXD5 G1TXD6 G1TXD7 8 7 6 5 4 3 2 1 3R RN 330R, RN170 8 7 6 5 4 3 2 1 RN168 G1TXD[7:0] 9 10 11 12 13 14 15 16 2R RN 220R, G1RXCLK G1GTXCLK G1TXEN 9 10 11 12 13 14 15 16 100pF, CN 100pF, 4 3 2 1 4 3 2 1 +3.3V 100pF, CN 220R R615 220R R609 220R R603 +3.3V +3.3V +3.3V CN20

330R R616 330R R610 330R R604 5 6 7 8 5 6 7 8 2 2

100pF C893 100pF C890 100pF C887 CN18 G1CRS G1RXDV G1TXER 220R R617 220R R611 220R R605 +3.3V +3.3V +3.3V

330R R618 330R R612 330R R606

100pF C894 100pF C891 100pF C888 G1RXER G1TXCLK G1COL 220R R619 220R R613 220R R607 +3.3V +3.3V +3.3V ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K 330R R620 330R R614 330R R608

Page Title : Page 100pF C895 100pF C892 100pF C889 Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work rcso iayeEhre nefc 0.6 Processor 3 - GigaByte Ethernet Interface Power +3.3V 1 1 DGND +3.3V ocessing System 372 53 DGND +3.3V of ilbride Rev C D A B

Figure A-51. Work Processor 3—GigaByte Ethernet Interface

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-52 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B WP3_G1_ MDIO MDC RESET_N MDC MDIO 5 5 1K R1350 +3.3V +3.3V R1303 G1RXD[7:0]

10K 1K R1351 G1TXD[7:0] G1GTXCLK MGTX125 G1RXCLK G1_IRQ_N Wp3_G1_ G1TXCLK G1TXER G1TXEN G1CRS G1COL G1RXER G1RXDV C533 C532 RESET_N +1.5VGE 18pF 18pF G1TXCLK G1TXER G1TXEN G1RXCLK G1RXER G1RXDV ther 3 2 G1TXD7 G1TXD6 G1TXD5 G1TXD4 G1TXD3 G1TXD2 G1TXD1 G1TXD0 G1RXD7 G1RXD6 G1RXD5 G1RXD4 G1RXD3 G1RXD2 G1RXD1 G1RXD0 0.01uF C519 MGTX125 G1CRS G1GTXCLK G1_IRQ_N G1COL

4 1 0.1uF C524

R449 R447 R446 R440 R439 R438 0.01uF C520 8 7 6 5 4 3 2 1 25MHz Y11 22R, RN 0.1uF C525

0.01uF C521 RN165 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R 0.1W 22R R444 0.1uF C526 GROUND Separate 9 10 11 12 13 14 15 16 0R 0.01uF C522 R450

22R 0.1W 22R 0.1uF C527 0.01uF C499 U62

mill trace must be 50 0.1uF C504 G2 G1 H2 H1 D8 C9 C8 D9 K2 E9 K3 A1 E1 B2 B4 A3 A2 A4 A5 B3 B9 A9 B8 A8 B7 A7 B6 B5 A6 E8 F7 F2 F1 J2 J1 +3.3V 0.01uF C500 VSSC XTAL1 XTAL2 SEL_2_5V RESET COMA TXD_7 TXD_6 TXD_5 TXD_4 TXD_3 TXD_2 TXD_1 TXD_0 TX_CLK TX_ER TX_EN CRS COL GTX_CLK CLK125 RXD_7 RXD_6 RXD_5 RXD_4 RXD_3 RXD_2 RXD_1 RXD_0 RX_CLK RX_ER RX_DV MDIO MDC INT

+3.3V 0.1uF C505 4 4 0.01uF C501 R1352 K7 0R R1353 CONFIG_6 0.1uF C506 J7 CONFIG_5

LED_YELLOW 0R R1354 1.5V L9 CONFIG_4 DVDDL E3 2 1 0R R1355 K9 H3 0.01uF C502 0R R1356 CONFIG_3 DVDDL K8 CONFIG_2 DVDDL D7

LD34 330R 0R R1357 J9 G7 0.1uF C507 0R R1358 CONFIG_1 DVDDL J8 CONFIG_0 R456 0R 0.01uF C503 +2.5VGEther

H9 2.5V M3 LED_TX AVDDL 0.1uF C508 F8 LED_LINK10 AVDDL L2 G8 B1

LED_LINK1000 AVDDL 3PIN_FERRITE H8 LED_RX AVDDL M7 0.1uF C523 3 G9 LED_DPLX AVDDL M8

330R F9 88E1011S LED_LINK100 G1AVDDH L21 R459 AVDDH N5 M6 49R9 2 HDAC_N R433 49R9 HDAC_P M5 TP151 M4 R434 1 LED_YELLOW TP152 CTRL25 TP149 E2 CTRL_15 DVDDH G3 2 1 M2 F3 2K49 R452 RSET DVDDH TP150 0.01uF C509

LD36 330R 3.3V M9 TDI VDDO H7

R457 0.1uF C514 M1 TRST VDDO J3 R453 4K7 L1 TMS VDDO C5

10K 0.01uF C510 L8 TDO VDDO C6 K1 E7 LED_RED TCK VDDO 0.1uF C515 2 1

R451 0.01uF C511 G6 DGND DGND G4

LD37 330R J6 DGND DGND D6 R455 +3.3V 0.1uF C516 H4 DGND DGND L7 F4 L6 DGND DGND 0.01uF C512 G5 DGND DGND K6 E4 L5 LED_YELLOW DGND DGND 0.1uF C517 D5 DGND DGND K5 2 1 D4 DGND DGND J5 C4 L4 0.01uF C513 LD32 DGND DGND C7 DGND DGND E6

3 0.1uF C518 +3.3V 3 E5 DGND DGND L3 H6 DGND DGND J4 F6 DGND DGND K4 H5 DGND DGND F5 SOUT_M SOUT_P SCLK_M SCLK_P MDI3_M MDI2_M MDI1_M MDI0_M MDI3_P MDI2_P MDI1_P MDI0_P SIN_M SIN_P N9 N7 N4 N2 D2 C3 D1 C2 N8 N6 N3 N1 D3 C1

C5310.01uF C5300.01uF C5290.01uF C5280.01uF OFG 0 1 1 0 CONFIG6 0 0 CONFIG5 1 0 CONFIG4 1 0 CONFIG3 0 CONFIG2 1 CONFIG1 0 CONFIG0 0 Bit[2] Bit[1] Bit[0] Pin OHMCONFIG6 SEL_BDT INT_POL 75/50 CONFIG5 DIS_FC DIS_SLEEP HWCFG_ CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_ CONFIG3 ANEG[0] ENA_XC D CONFIG2 ANEG[3] ANEG[2] A CONFIG1 ENA_PAUSE PHYADR[4] PHY CONFIG0 PHYADR[2] PHYADR[1] PHY Bit[2] Bit[1] Bit[0] Pin R448 49R9 49R9 R443 49R9 49R9 R441 49R9 49R9 R436 49R9 49R9 R445 R442 R437 R435 WP3_PH1_M3 WP3_P WP3_PH1_M2 WP3_P WP3_PH1_M1 WP3_P WP3_PH1_M0 WP3_P H1_P3 H1_P2 H1_P1 H1_P0 CONFIG6 VSS CONFIG5 VDDO CONFIG4 VDDO CONFIG3 VSS CONFIG2 LED_LINK10 CONFIG1 VSS CONFIG0 VSS Pin Setting 2 2 IS_125 NEG[1] D4E D2E 10E ADR[3] ADR[0] 1E 2E 4E 3E 6E 5E 8E 7E 9E MODE[3] MODE[0] LED flashing => Transmitting or Rece LED off => Link Down LED on => Link Up LED_TX is used as a global activity indica NOTE: When PHY register 24.2:0='111', LED off => Link Down LED on => Link Up LED_LINK1000 is used as a global link indica NOTE: When PHY register 24.4:3='01', RJG5-7G05 P5E VSS 0 0 VSS 0 0 0 LED_TX 0 1 1 LED_RX 0 0 1LED_DUPLEX 0 1 0LED_LINK1000 1 0 0LED_LINK100 1 1 1LED_LINK10 1 0 1 VDD0 1 1 Bit[2:0] Pin 1:1 1:1 1:1 1:1 D3E D1E 11E iving ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K +3.3V tor. tor. Page Title : Page Tuesday, September 30, Torridon - RapidIO Enabled Multi-Pr Work ProcessorWork 3 - +1.5VGEther +2.5VGEther +3.3V Power 2003 1 1 +1.5VGEther +2.5VGEther +3.3V DGND iayeEhre nefc H 0.6 GigaByte Ethernet Interface - PHY CGND ocessing System 472 54 CGND DGND +1.5VGEther +2.5VGEther +3.3V of ilbride Rev C D A B

Figure A-52. Work Processor 3—GigaByte Ethernet Interface—PHY

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 4 4 M10 N11 N10 P10 P11 L11 L10 M1 M2 M3 M6 M7 M8 M9 R7 R6 R5 R4 R3 R2 R1 N9 N8 N7 N6 N5 N4 N1 H2 H1 P1 P2 P3 P4 P5 P6 P7 P8 P9 K1 K2 K3 K6 K7 K8 L9 L8 L5 L4 L3 L2 L1 J8 J7 J6 J5 J4 J3 J2 J1 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17/FEC_RX_DV PB16/FEC_RX_ER PB15/FEC_TX_ER PB14/FEC_TX_EN PB13/FEC_COL PB12/FEC_CRS PB11/FEC_RXD3 PB10/FEC_RXD2 PB9/FEC_RXD1 PB8/FEC_RXD0 PB7/FEC_TXD0 PB6/FEC_TXD1 PB5/FEC_TXD2 PB4/FEC_TXD3 PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 U6H MPC8560

Alt. DUART CPM Alt. 10/100 Eth.Alt. DUART PD30/UART_SOUT0 PD27/UART_SOUT1 PC17/FEC_RX_CLK PC18/FEC_TX_CLK PD29/UART_RTS0 PD26/UART_RTS1 PC15/UART_CTS0 PC13/UART_CTS1

PD31/UART_SIN0 PD28/UART_SIN1 Alt. 10/100 Eth. PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PC31 PC30 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC16 PC14 PC12 PC11 PC10 PD9 PD8 PD7 PD6 PD5 PD4 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 V6 AE2 AD5 V9 AE3 AD2 AC1 AC2 AC3 AC4 AC7 AB6 AB5 AB3 AB2 AB1 AA1 AA2 AA3 AA4 AA7 AA8 Y9 W9 W8 W7 W6 W3 W2 W1 V1 V2 V3 V4 V5 U10 U8 U4 U3 U2 Y6 Y5 Y4 Y3 Y2 Y1 U1 T1 T4 T5 T6 T9 R11 R10 R9 R8 AD6 AD1 U9 U7 3 3 WP3_RXD WP3_TXD WP3_RXD WP3_TXD 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr Work Processor 3 - Communications Processor Work Processor 3 - Communications 1 1 ocessing System 572 55 of ilbride Module Rev 0.6 C D A B

Figure A-53. Work Processor 3—Communications Processor Module

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-54 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 2 5 JP38 5 1 MSRCID0 MDC MDIO +3.3V +3.3V R636 R635 +3.3V TP89 TP167 TP166 TP165 TP164 TP163 +3.3V TP85 WP3_HRESET_N WP3_HRESET_REQ_N WP3_SRE CHKSTOP_OUT_N CHKSTOP_IN_N 224K7 4K7 R232 R231 4K7 R230 R229 R221 0R 0R MDC MDIO SET_N ASLEEP MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT THERM1 THERM0 CLK_OUT 4K7 4K7 AG18 AG22 AG28 AG20 AG19 AH16 AH20 AH28 AH27 AH26 AH25 AB22 AE28 AF20 AF22 AF28 AG2 AG1 M11 AH3 AH2 AH1 N12 G1 G2 G3 E1 A3 A2 B2 B1 F4 F2 F5 F3 F1 J9 HRESET HRESET_REQ SRESET CKSTP_OUT CKSTP_IN ASLEEP TEST_SEL(Draco/Dracom) LSSD_MODE MDVAL MSRCID4 MSRCID3 MSRCID2 MSRCID1 MSRCID0 TRIG_OUT/READY/QUIESCE TRIG_IN L2_TSTCLK THERM1 THERM0 CLK_OUT L1_TSTCLK EC_MDIO EC_MDC NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 U6D MPC8560 AUXILIARY FUNCTION PIC CLOCKING SPARES Eth.MI IRQ11/DMA_DDONE3 IRQ10/DMA_DACK3 4 CNTRL SYS. JTAG 4 IRQ9/DMA_DREQ3 I2C ANALOG DMA DMA_DDONE1 DMA_DDONE0 DMA_DREQ1 DMA_DREQ0 DMA_DACK1 DMA_DACK0 PWR Mng. PWR DFT IRQ_OUT SYSCLK SPARE4 SPARE3 SPARE2 SPARE1 IIC_SDA IIC_SCL TRST IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 MCP TMS TDO UDE RTC TCK TDI DEBUG AB23 AH23 AF23 AF19 AH21 C1 AF1 U11 T11 AB20 AG25 AA19 Y19 AA21 AG24 AB18 Y18 AA18 AF21 AH22 AG23 G6 H7 G5 H6 G4 H5 AB21 AH24 AF26 Y20 AG16 AG17 AG21 IRQ11_N IRQ10_N IRQ9_N IRQ8_N IRQ7_N IRQ6_N IRQ5_N IRQ1_N IRQ0_N MCP_N WP3_INT_N BP_INT_N WP2_INT_N WP1_INT_N UDE_N I2C_SDA I2C_SCL WP3_RTC_CLK WP3_SYS_CLK 10K, RN 10K, RN145 TCK TMS WP3_T TDO TDI 1 TP84 TP83 TP82 TP81 2 3 RST_N

4K7 R627 +3.3V 4 5 +3.3V 6 10 7 8

4K7 R628 10K R708 9 WP3_SYS_CLK WP3_RTC_CLK +3.3V +3.3V I2C_SCL I2C_SDA

1 2 3 5 4 10 6 7

3 8 3 9 BP_INT_N WP2_INT_N WP1_INT_N G1_IRQ_N RN146 10K, RN WP3_INT_N CHKSTOP_OUT_N WP3_COP_HRESET_N WP3_COP_SR TMS TCK TDO TDI ESET_N +3.3V 10K R222 10K R223 10K R224 10K R225 15 13 11 9 7 5 3 1 2x8 Header HD11 2 2 WP3_HRESET_REQ_N WP3_COP_TRST_N WP3_T WP3_COP_SR WP3_COP_HRESET_N WP3_HRESET_N WP3_SRE 16 14 12 10 8 6 4 2 KEY KEY RST_N +3.3V SET_N 10K R226 ESET_N 2K R227 10K R228 CHKSTOP_IN_N WP3_COP_ TRST_N WP3_HRESET_R WP3_COP_ WP3_ WP3_COP_SR WP3_COP_HRES WP3_HRESET_N WP3_SR TRST_N ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K ESET_N TRST_N ESET_N Page Title : Page Friday, September 26, 2003 EQ_N ET_N Torridon - RapidIO Enabled Multi-Pr Work P oesr3-Axlr ucin 0.6 rocessor 3 - Auxilary Functions 1 +3.3V Power 1 +3.3V DGND ocessing System 672 56 +3.3V DGND of ilbride Rev C D A B

Figure A-54. Work Processor 3—Auxiliary Functions

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5

"CONFIGURATION" Memory PCI/RIO Processor RIO Processor TSEC RIO "Device "Device "Device "Device "Device "Device "Device "RIO Clk 1" "RIO Clk 0" "Core "Core "Sys "Sys "Sys "Sys "Debug Enable" "Host/Agent 1" "Host/Agent 0" "CPU Boot" Loc.2" "ROM Loc.0" "ROM "Device "TSEC1 Mode" Loc.1" "ROM PLL3" PLL2" PLL1" PLL0" PLL1" PLL0" ID7" ID6" ID5" ID3" ID2" ID1" ID0" ID4" 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 SW DIP-8 SW SW18 DIP-8 SW SW13 DIP-8 SW SW12 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 4 4 10K, RN RN111 1 2

3 +3.3V 4 5 6 10

WP3_RST_CONF_N 7 8 9 10K, RN RN149 10K, RN RN112 1 1 2 2

3 +3.3V 3 +3.3V 4 5 4 5 6 10 6 10 7 7 8 8 9 9 74LVC 19 24 25 48 17 15 13 11 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 1 1 8 6 4 2 U40 U39 2OE 2A4 2A3 2A2 2A1 1OE 1A4 1A3 1A2 1A1 OE4 4A4 4A3 4A2 4A1 OE3 3A4 3A3 3A2 3A1 OE2 2A4 2A3 2A2 2A1 OE1 1A4 1A3 1A2 1A1 H244 4 DGND 10 DGND 74ALVT16244 +3.3V +3.3V VCC 15 7

GND DGND 3V3 10 20 21 DGND 3V3 18 28 DGND 3V3 31 34 DGND 3V3 42 39 DGND 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 45 DGND 4Y4 4Y3 4Y2 4Y1 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 3 3 3 5 7 9 12 14 16 18 23 22 20 19 17 16 14 13 12 11 9 8 6 5 3 2 R762 R761 R760 R759 R758 R757 R756 Do Not Fit 0R 0R G1TXD4 G1TXD5 G1TXD6 G1TXD7 G2TXD4 G2TXD5 G2TXD6 G2TXD7 0R 0R 0R 0R 0R LGPL1 LGPL0 LGPL2 LALE BLA31 BLA30 BLA29 BLA28 BLA27 G1GTXCLK MSRCID0 LWE_N3 LWE_N2 BLA27 LCS_N2 LCS_N1 LCS_N0 G2TXD2 G2TXD3 G1GTXCLK MSRCID0 G2TXD[ G1TXD[ LGPL1 LGPL0 LGPL2 LALE BLA[27:31] LWE_N[2:3] LCS_N[0:2] 7:4] 7:4] 2 2 Add R756,R757 Remove R758,R759,R760,R761, For Rev 2 silicon; Note : Configuration shown is for Rev 1 Sili G2TXD2 G2TXD3 G2TXD4 G2TXD5 G2TXD6 G2TXD7 G2TXD[7:2] R762 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K con. Page Title : Page Monday, September 08, 2003 Decoupling Torridon - RapidIO Enabled Multi-Pr +3.3V C732 0.1uF +3.3V okPoesr3-Cniuain0.6 Work Processor 3 - Configuration C733 0.1uF 1 1 +3.3V Power ocessing System +3.3V DGND 772 57 DGND +3.3V of ilbride Rev C D A B

Figure A-55. Work Processor 3—Power On Configuration

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-56 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 +3.3V AG27 AC17 AC11 AB11 AB26 AA20 AA16 AE15 AA12 AE10 AF10 AF12 W21 W19 W13 AG7 AG3 M12 AC9 AD8 AC6 AD3 AC5 AD4 AH4 G12 AA6 AB4 AB9 AE8 AB7 AA5 AE1 H12 C11 AF4 AF2 U26 R25 U20 R19 AF7 P12 V10 Y23 P22 K10 T12 F11 T10 W5 W4 M4 M5 G9 D8 U6 C4 H4 C2 N2 U5 H3 N3 D1 K9 Y8 V7 K5 B3 E3 V8 Y7 E4 K4 T8 T3 T7 T2 L6 L7 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 OVdd42 OVdd41 OVdd40 OVdd39 OVdd38 OVdd37 OVdd36 OVdd35 OVdd34 OVdd33 OVdd32 OVdd31 OVdd30 OVdd29 OVdd28 OVdd27 OVdd26 OVdd25 OVdd24 OVdd23 OVdd22 OVdd21 OVdd20 OVdd19 OVdd18 OVdd17 OVdd16 OVdd15 OVdd14 OVdd13 OVdd12 OVdd11 OVdd10 OVdd9 OVdd8 OVdd7 OVdd6 OVdd5 OVdd4 OVdd3 OVdd2 OVdd1 U6I MPC8560 POWER 4 4 GND99 GND98 GND97 GND96 GND95 GND94 GND93 GND92 GND91 GND90 GND89 GND88 GND87 GND86 GND85 GND84 GND83 GND82 GND81 GND80 GND79 GND78 GND77 GND76 GND75 GND74 GND73 GND72 GND71 GND70 GND69 GND68 GND67 GND66 GND65 GND64 GND63 GND62 GND61 GND60 GND59 GND58 GND57 GND56 GND55 GND54 GND53 GND52 GND51 GND50 GND49 GND48 GND47 GND46 GND45 GND44 GND43 GND42 GND41 GND40 K28 B27 C27 H27 M27 AF27 B26 R26 V26 AG26 G25 L25 E24 J24 F23 K23 P23 W23 C22 H22 M22 U21 B20 H20 L20 R20 C19 J19 AB19 F18 K18 W18 A17 C17 H17 N17 R17 U17 AD17 M16 P16 T16 U16 Y16 N15 R15 U15 AF15 B14 H14 M14 P14 T14 N13 R13 U13 AA13 AF13 A12 E12

Decoupling +3.3V +3.3V +3.3V C656 C649 C642 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C657 C650 C643 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C658 C651 C644 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C659 C652 C645 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C660 C653 C646 0.1uF 0.1uF 0.1uF 3 +3.3V +3.3V +3.3V 3 C661 C654 C647 0.1uF 0.1uF 0.1uF +3.3V +3.3V +3.3V C662 C655 C648 0.1uF 0.1uF 0.1uF +3.3V C961

10uF, 6.3V

Bulk Decoupling Decoupling +3.3V +3.3V 2 1C1142 C1080 + 220uF, Tants 10uF,6.3V Tants +3.3V 2 1C1143

220uF, Tants Vdd M17 M15 M13 N16 R16 N14 R14 U14 R12 U12 P17 P15 P13 T17 T15 T13 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 U6E MPC8560 Supply &PLL CORE SENSE_VDD SENSE_VSS AVdd3 AVdd2 AVdd1

Decoupling Vdd Vdd AH17 AH18 AH19 K12 C1096 C634 L12 0.1uF 0.1uF 2 Vdd Vdd 2 C1097 C635 0.1uF 0.1uF Vdd Vdd C1098 C636 0.1uF 0.1uF Vdd Vdd C1099 C637 0.1uF 0.1uF TP179 TP178 Vdd Vdd C1100 C638 0.1uF 0.1uF Vdd Vdd C1101 C639 0.1uF 0.1uF Vdd Vdd C1102 C640 0.1uF 0.1uF C1234 C1233 C1232

Vdd Vdd 0.1uF 0.1uF 0.1uF C1103 C641 0.1uF 0.1uF C302 C300 C298 Vdd C960 2.2uF 2.2uF 2.2uF

10uF, 6.3V C303 C301 C299 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K

2.2uF 10R 2.2uF 10R 2.2uF 10R Bulk Decoupling Decoupling R263 R262 R261 Page Title : Page Vdd Vdd Wednesday, October 01, 2003

Torridon - RapidIO Enabled Multi-Pr 2 1C1104 C1079 + Vdd Vdd Vdd 220uF, Tants 10uF,6.3V Tants Vdd

Work Processor 3 - 2 1C1105

220uF, Tants 12V fan Header for 2 1 Power 1 Vdd +3.3V +12V Power 1 HD19 HS4 10-THMA-01 ocessing System Vdd +3.3V +12V DGND 1 Ferrite L33 S8 S7 DO57 DO57 Bead 872 58 DGND Vdd +3.3V +12V 2 +12V of ilbride Rev 0.6 C D A B

Figure A-56. Work Processor 3—Power

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-57 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 TSI500_ TSI500_HW_RST_N TSI500_ TSI500_TXCLK_IN RIO0_TFRAME_N TSI500_ TSI500_ TSI500_LS1_CLK TSI500_LS0_CLK RIO0_RFRAME_N RIO0_TD_N[0:7] RIO0_R RIO0_TFRAME RIO0_TCLK_N RIO0_RFRAME RIO0_RCLK_N SW_RST_N TXCLK_IN_N RIO0_TD[0:7] RIO0_R RIO0_TCLK RIO0_RCLK INT0_N INT1_N D_N[0:7] D[0:7] TSI500_ TSI500_HW TSI500_ TSI500_ TSI500_ TSI500_TXCLK_IN TSI500_LS1_CLK TSI500_LS0_CLK RIO0_TCLK RIO0_TFRAME_N RIO0_TF RIO0_RCLK_N RIO0_RCLK RIO0_RFRAME_N RIO0_RFRAME RIO0_TCLK_N RIO0_TD_N[0:7] RIO0_TD[0:7] RIO0_R RIO0_R SW_RST_N INT0_N INT1_N TXCLK_IN_N _RST_N D_N[0:7] D[0:7] RAME RIO Switch - Misc Page 62 RIO Switch - Port 0 & 1 Page 60 TSI500_SW_RST_N TSI500_HW_RST_N TSI500_INT0_N TSI500_INT1_N TSI500_TXCLK_IN_N TSI500_TXCLK_IN TSI500_LS1_CLK TSI500_LS0_CLK RIO0_TD_N[0:7] RIO0_TD[0:7] RIO0_TCLK_N RIO0_TCLK RIO0_TFRAME_N RIO0_TFRAME RIO0_RD_N[0:7] RIO0_RD[0:7] RIO0_RCLK_N RIO0_RCLK RIO0_RFRAME_N RIO0_RFRAME 4 4 RIO1_RFRAME_N RIO1_TFRAME_N RIO1_RD_N[0:7] RIO1_TD_N[0:7] RIO1_RFRAME RIO1_TFRAME RIO1_RCLK_N RIO1_TCLK_N +1.2Vtsi500 +2.5Vtsi500 RIO1_RD[0:7] RIO1_TD[0:7] RIO1_RCLK RIO1_TCLK +1.2Vtsi500 DGND +3.3V DGND +3.3V +1.2Vtsi500 +2.5Vtsi500 +3.3V DGND +1.2Vt +3.3V DGND RIO1_TCLK RIO1_TFRAME_N RIO1_TF RIO1_RCLK_N RIO1_RCLK RIO1_RFRAME_N RIO1_RFRAME RIO1_TCLK_N RIO1_TD_N[0:7] RIO1_TD[0:7] RIO1_R RIO1_R si500 D_N[0:7] D[0:7] RAME DGND +1.2V +2.5V +3.3V DGND +1.2V +3.3V tsi500 tsi500 tsi500 RIO1_TD_N[0:7] RIO1_TD[0:7] RIO1_TCLK_N RIO1_TCLK RIO1_TFRAME_N RIO1_TFRAME RIO1_R RIO1_R RIO1_RCLK_N RIO1_RCLK RIO1_RFRAME_N RIO1_RFRAME D_N[0:7] D[0:7] 3 3 RIO2_TFRAME_N RIO2_RFRAME_N RIO2_TD_N[0:7] RIO2_RD_N[0:7] RIO2_TFRAME RIO2_TCLK_N RIO2_RFRAME RIO2_RCLK_N RIO2_TD[0:7] RIO2_R RIO2_TCLK RIO2_RCLK D[0:7] RIO2_TCLK RIO2_TFRAME_N RIO2_TF RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME_N RIO2_RFRAME RIO2_TCLK_N RIO2_TD_N[0:7] RIO2_TD[0:7] RIO2_R RIO2_R D_N[0:7] D[0:7] RAME RIO Switch - Page 63 RIO Switch - Port 2 & 3 Page 61 RIO2_TD_N[0:7] RIO2_TD[0:7] RIO2_TCLK_N RIO2_TCLK RIO2_TFRAME_N RIO2_TFRAME RIO2_RD_N[0:7] RIO2_RD[0:7] RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME_N RIO2_RFRAME Power 2 2 RIO3_RFRAME_N RIO3_TFRAME_N RIO3_RD_N[0:7] tsi500_VDD +2.5Vtsi500 RIO3_TD_N[0:7] RIO3_RFRAME RIO3_TFRAME RIO3_RCLK_N RIO3_TCLK_N RIO3_RD[0:7] RIO3_TD[0:7] RIO3_RCLK RIO3_TCLK +1.2Vtsi500 DGND +3.3V DGND +3.3V tsi500_VDD +2.5Vtsi500 +3.3V DGND +1.2Vtsi500 +3.3V DGND RIO3_TCLK RIO3_TFRAME_N RIO3_TFRAME RIO3_RCLK_N RIO3_RCLK RIO3_RFRAME_N RIO3_RFRAME RIO3_TCLK_N RIO3_TD_N[0:7] RIO3_TD[0:7] RIO3_R RIO3_R D_N[0:7] D[0:7] tsi500_VDD +2.5Vtsi500 +3.3V DGND +1.2Vtsi500 +3.3V DGND ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 05, 2003 RIO3_TD_N[0:7] RIO3_TD[0:7] RIO3_TCLK_N RIO3_TCLK RIO3_TFRAME_N RIO3_TF RIO3_RD RIO3_R RIO3_RCLK_N RIO3_RCLK RIO3_RFRAME_N RIO3_RFRAME Torridon - RapidIO Enabled Multi-Pr D[0:7] RAME _N[0:7] RapidIO Switch - Top 1 1 ee 0.6 Level ocessing System 972 59 of ilbride Rev C D A B

Figure A-57. RapidIO Switch—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-58 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5

Bulk Decoupling +1.2Vtsi500

2 1C1189 RIO0_TD[0:7] RIO0_TD_N[0:7]

220uF, Tants RIO1_TD[0:7] RIO1_TD_N[0:7] RIO0_TD_N7 RIO0_TD_N6 RIO0_TD_N5 RIO0_TD_N4 RIO0_TD_N3 RIO0_TD_N2 RIO0_TD_N1 RIO0_TD_N0 RIO1_TD7 RIO1_TD6 RIO1_TD5 RIO1_TD4 RIO1_TD3 RIO1_TD2 RIO1_TD1 RIO1_TD0 RIO1_TD_N7 RIO1_TD_N6 RIO1_TD_N5 RIO1_TD_N4 RIO1_TD_N3 RIO1_TD_N2 RIO1_TD_N1 RIO1_TD_N0 RIO0_TD7 RIO0_TD6 RIO0_TD5 RIO0_TD4 RIO0_TD3 RIO0_TD2 RIO0_TD1 RIO0_TD0 4 4 RIO1_TCLK_N RIO1_TCLK RIO1_TFRAME_N RIO1_TF RIO0_TCLK_N RIO0_TCLK RIO0_TFRAME_N RIO0_TFRAME RAME RIO1_TCLK RIO1_TFRAME_N RIO1_TFRAME RIO1_TD_N7 RIO1_TD7 RIO1_TD_N6 RIO1_TD6 RIO1_TD_N5 RIO1_TD5 RIO1_TD_N4 RIO1_TD4 RIO1_TD_N3 RIO1_TD3 RIO1_TD_N2 RIO1_TD2 RIO1_TD_N1 RIO1_TD1 RIO1_TD_N0 RIO1_TD0 RIO1_TCLK_N RIO0_TCLK RIO0_TFRAME_N RIO0_TFRAME RIO0_TD_N7 RIO0_TD7 RIO0_TD_N6 RIO0_TD6 RIO0_TD_N5 RIO0_TD5 RIO0_TD_N4 RIO0_TD4 RIO0_TD_N3 RIO0_TD3 RIO0_TD_N2 RIO0_TD2 RIO0_TD_N1 RIO0_TD1 RIO0_TD_N0 RIO0_TD0 RIO0_TCLK_N +1.2Vt +1.2Vtsi500 AM19 AM20 AM21 AM22 AM24 AM25 AM26 AM27 AM23 AM18 AN19 AN20 AN21 AN22 AN24 AN25 AN26 AN27 AN23 AN18 si500 0.1uF C245 AG3 AG2 AD3 AD2 AC3 AC2 AA3 AA2 AB3 AB2 AE3 AE2 AF3 AF2 W3 W2 0.1uF C242 Y3 Y2 V3 V2 P1_RD_n(7) P1_RD_p(7) P1_RD_n(6) P1_RD_p(6) P1_RD_n(5) P1_RD_p(5) P1_RD_n(4) P1_RD_p(4) P1_RD_n(3) P1_RD_p(3) P1_RD_n(2) P1_RD_p(2) P1_RD_n(1) P1_RD_p(1) P1_RD_n(0) P1_RD_p(0) P1_RCLK_n P1_RCLK_p P1_RFRAME_n P1_RFRAME_p U4B TSi500 P0_RD_n(7) P0_RD_p(7) P0_RD_n(6) P0_RD_p(6) P0_RD_n(5) P0_RD_p(5) P0_RD_n(4) P0_RD_p(4) P0_RD_n(3) P0_RD_p(3) P0_RD_n(2) P0_RD_p(2) P0_RD_n(1) P0_RD_p(1) P0_RD_n(0) P0_RD_p(0) P0_RCLK_n P0_RCLK_p P0_RFRAME_n P0_RFRAME_p U4A TSi500 2 2 JP10 JP8 1 1 +3.3V

P1_CLK_SEL(1) F2 +3.3V AP29 P1_DVDD PORT 1 TSi500 10K R205 P0_CLK_SEL(1) F1 AJ1 P0_DVDD PORT 0 TSi500 10K R201 3 AP30 P1_DVSS +3.3V 3 P1_CLK_SEL(0) E1 AL1 P0_DVSS +3.3V AN29 P1_AVDD 10K R206 P0_CLK_SEL(0) F3 2 AK1 P0_AVDD 10K R202 2 AM29 P1_AVSS JP11 P1_TFRAME_n P1_TFRAME_p AK2 P0_AVSS JP9 P0_TFRAME_n P0_TFRAME_p P1_TD_n(7) P1_TD_p(7) P1_TD_n(6) P1_TD_p(6) P1_TD_n(5) P1_TD_p(5) P1_TD_n(4) P1_TD_p(4) P1_TD_n(3) P1_TD_p(3) P1_TD_n(2) P1_TD_p(2) P1_TD_n(1) P1_TD_p(1) P1_TD_n(0) P1_TD_p(0) P1_TCLK_n P1_TCLK_p 1 P0_TD_n(7) P0_TD_p(7) P0_TD_n(6) P0_TD_p(6) P0_TD_n(5) P0_TD_p(5) P0_TD_n(4) P0_TD_p(4) P0_TD_n(3) P0_TD_p(3) P0_TD_n(2) P0_TD_p(2) P0_TD_n(1) P0_TD_p(1) P0_TD_n(0) P0_TD_p(0) P0_TCLK_n P0_TCLK_p 1 AN16 AM16 AN15 AM15 AN14 AM14 AN13 AM13 AN11 AM11 AN10 AM10 AN9 AM9 AN8 AM8 AN17 AM17 AN12 AM12 U2 U3 T2 T3 R2 R3 P2 P3 N2 N3 L2 L3 K2 K3 J2 J3 H2 H3 M2 M3 0.1uF C247 0.1uF C244 RIO1_RD_N7 RIO1_RD7 RIO1_RD_N6 RIO1_RD6 RIO1_RD_N5 RIO1_RD5 RIO1_RD_N4 RIO1_RD4 RIO1_RD_N3 RIO1_RD3 RIO1_RD_N2 RIO1_RD2 RIO1_RD_N1 RIO1_RD1 RIO1_RD_N0 RIO1_RD0 RIO1_RCLK_N RIO1_RCLK RIO1_RFRAME_N RIO1_RFRAME + 10uF,6.3V Tants C246 RIO0_RD_N7 RIO0_RD7 RIO0_RD_N6 RIO0_RD6 RIO0_RD_N5 RIO0_RD5 RIO0_RD_N4 RIO0_RD4 RIO0_RD_N3 RIO0_RD3 RIO0_RD_N2 RIO0_RD2 RIO0_RD_N1 RIO0_RD1 RIO0_RD_N0 RIO0_RD0 RIO0_RCLK_N RIO0_RCLK RIO0_RFRAME_N RIO0_RFRAME + 10uF,6.3V Tants C243 R208 R207 R204 R203 2R2 0R 2R2 0R RIO1_RCLK_N RIO1_RCLK RIO1_RFRAME_N RIO1_RFRAME 470nH L8 RIO0_RCLK_N RIO0_RCLK RIO0_RFRAME_N RIO0_RFRAME 470nH L7 +1.2Vtsi500 +1.2V RIO1_RD7 RIO1_RD6 RIO1_RD5 RIO1_RD4 RIO1_RD3 RIO1_RD2 RIO1_RD1 RIO1_RD0 RIO1_RD_N7 RIO1_RD_N6 RIO1_RD_N5 RIO1_RD_N4 RIO1_RD_N3 RIO1_RD_N2 RIO1_RD_N1 RIO1_RD_N0 tsi500 2 2 RIO0_RD7 RIO0_RD6 RIO0_RD5 RIO0_RD4 RIO0_RD3 RIO0_RD2 RIO0_RD1 RIO0_RD0 RIO0_RD_N7 RIO0_RD_N6 RIO0_RD_N5 RIO0_RD_N4 RIO0_RD_N3 RIO0_RD_N2 RIO0_RD_N1 RIO0_RD_N0 RIO1_R RIO1_RD RIO0_R RIO0_R D[0:7] _N[0:7] D[0:7] D_N[0:7] ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Tuesday, September 30, Torridon - RapidIO Enabled Multi-Pr +1.2Vtsi500 aiI wth-Pr 0.6 RapidIO Switch - Port 0 & 1 +3.3V Power 2003 1 1 +1.2Vtsi500 +3.3V DGND ocessing System 072 60 +1.2Vtsi500 +3.3V DGND of ilbride Rev C D A B

Figure A-58. RapidIO Switch—Ports 0 and 1

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5 RIO3_TD[0:7] RIO3_TD_N[0:7] RIO2_TD[0:7] RIO2_TD_N[0:7]

Bulk Decoupling +1.2Vtsi500

2 1C1188

220uF, Tants RIO3_TD7 RIO3_TD6 RIO3_TD5 RIO3_TD4 RIO3_TD3 RIO3_TD2 RIO3_TD1 RIO3_TD0 RIO3_TD_N7 RIO3_TD_N6 RIO3_TD_N5 RIO3_TD_N4 RIO3_TD_N3 RIO3_TD_N2 RIO3_TD_N1 RIO3_TD_N0 RIO2_TD7 RIO2_TD6 RIO2_TD5 RIO2_TD4 RIO2_TD3 RIO2_TD2 RIO2_TD1 RIO2_TD0 RIO2_TD_N7 RIO2_TD_N6 RIO2_TD_N5 RIO2_TD_N4 RIO2_TD_N3 RIO2_TD_N2 RIO2_TD_N1 RIO2_TD_N0 RIO3_TCLK_N RIO3_TCLK RIO3_TFRAME_N RIO3_TFRAME RIO2_TCLK_N RIO2_TCLK RIO2_TFRAME_N RIO2_TFRAME 4 4 RIO3_TCLK RIO3_TFRAME_N RIO3_TFRAME RIO2_TCLK RIO2_TFRAME_N RIO2_TFRAME RIO3_TD_N7 RIO3_TD7 RIO3_TD_N6 RIO3_TD6 RIO3_TD_N5 RIO3_TD5 RIO3_TD_N4 RIO3_TD4 RIO3_TD_N3 RIO3_TD3 RIO3_TD_N2 RIO3_TD2 RIO3_TD_N1 RIO3_TD1 RIO3_TD_N0 RIO3_TD0 RIO3_TCLK_N RIO2_TD_N7 RIO2_TD7 RIO2_TD_N6 RIO2_TD6 RIO2_TD_N5 RIO2_TD5 RIO2_TD_N4 RIO2_TD4 RIO2_TD_N3 RIO2_TD3 RIO2_TD_N2 RIO2_TD2 RIO2_TD_N1 RIO2_TD1 RIO2_TD_N0 RIO2_TD0 RIO2_TCLK_N +1.2Vt +1.2Vt M32 M33 C16 C15 C14 C13 C11 C10 C12 C17 R32 R33 N32 N33 H32 H33 U32 U33 B16 B15 B14 B13 B11 B10 B12 B17 P32 P33 K32 K33 T32 T33 L32 L33 si500 si500 J32 J33 0.1uF C10 0.1uF C7 C9 C8 B9 B8 P3_RD_n(7) P3_RD_p(7) P3_RD_n(6) P3_RD_p(6) P3_RD_n(5) P3_RD_p(5) P3_RD_n(4) P3_RD_p(4) P3_RD_n(3) P3_RD_p(3) P3_RD_n(2) P3_RD_p(2) P3_RD_n(1) P3_RD_p(1) P3_RD_n(0) P3_RD_p(0) P3_RCLK_n P3_RCLK_p P3_RFRAME_n P3_RFRAME_p P2_RD_n(7) P2_RD_p(7) P2_RD_n(6) P2_RD_p(6) P2_RD_n(5) P2_RD_p(5) P2_RD_n(4) P2_RD_p(4) P2_RD_n(3) P2_RD_p(3) P2_RD_n(2) P2_RD_p(2) P2_RD_n(1) P2_RD_p(1) P2_RD_n(0) P2_RD_p(0) P2_RCLK_n P2_RCLK_p P2_RFRAME_n P2_RFRAME_p U4D U4C TSi500 TSi500 2 2 JP3 JP1 1 1 +3.3V +3.3V P3_CLK_SEL(1) A4 P2_CLK_SEL(1) B4 A6 P3_DVDD PORT 3 TSi500 10K R21 F34 P2_DVDD PORT 2 TSi500 10K R17

A5 P3_DVSS +3.3V E34 P2_DVSS +3.3V P3_CLK_SEL(0) B5 P2_CLK_SEL(0) D3 B6 P3_AVDD 10K R22 F33 P2_AVDD 10K R18 2 2 3 3

C6 P3_AVSS JP4 F32 P2_AVSS JP2 P3_TFRAME_n P3_TFRAME_p P2_TFRAME_n P2_TFRAME_p P3_TD_n(7) P3_TD_p(7) P3_TD_n(6) P3_TD_p(6) P3_TD_n(5) P3_TD_p(5) P3_TD_n(4) P3_TD_p(4) P3_TD_n(3) P3_TD_p(3) P3_TD_n(2) P3_TD_p(2) P3_TD_n(1) P3_TD_p(1) P3_TD_n(0) P3_TD_p(0) P2_TD_n(7) P2_TD_p(7) P2_TD_n(6) P2_TD_p(6) P2_TD_n(5) P2_TD_p(5) P2_TD_n(4) P2_TD_p(4) P2_TD_n(3) P2_TD_p(3) P2_TD_n(2) P2_TD_p(2) P2_TD_n(1) P2_TD_p(1) P2_TD_n(0) P2_TD_p(0) P3_TCLK_n P3_TCLK_p P2_TCLK_n P2_TCLK_p 1 1 B19 C19 B20 C20 B21 C21 B22 C22 B24 C24 B25 C25 B26 C26 B27 C27 W33 W32 Y33 Y32 AA33 AA32 AB33 AB32 AD33 AD32 AE33 AE32 AF33 AF32 AG33 AG32 B18 C18 V33 V32 B23 C23 AC33 AC32 0.1uF C12 0.1uF C9 RIO3_RD_N7 RIO3_RD7 RIO3_RD_N6 RIO3_RD6 RIO3_RD_N5 RIO3_RD5 RIO3_RD_N4 RIO3_RD4 RIO3_RD_N3 RIO3_RD3 RIO3_RD_N2 RIO3_RD2 RIO3_RD_N1 RIO3_RD1 RIO3_RD_N0 RIO3_RD0 RIO3_RCLK_N RIO3_RCLK RIO3_RFRAME_N RIO3_RFRAME RIO2_RD_N7 RIO2_RD7 RIO2_RD_N6 RIO2_RD6 RIO2_RD_N5 RIO2_RD5 RIO2_RD_N4 RIO2_RD4 RIO2_RD_N3 RIO2_RD3 RIO2_RD_N2 RIO2_RD2 RIO2_RD_N1 RIO2_RD1 RIO2_RD_N0 RIO2_RD0 RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME_N RIO2_RFRAME + + 10uF,6.3V Tants C11 10uF,6.3V Tants C8 R24 R23 R20 R19 2R2 2R2 0R 0R RIO3_RCLK_N RIO3_RCLK RIO3_RFRAME_N RIO3_RFRAME RIO2_RCLK_N RIO2_RCLK RIO2_RFRAME_N RIO2_RFRAME 470nH L2 470nH L1 +1.2V +1.2V RIO3_RD7 RIO3_RD6 RIO3_RD5 RIO3_RD4 RIO3_RD3 RIO3_RD2 RIO3_RD1 RIO3_RD0 RIO3_RD_N7 RIO3_RD_N6 RIO3_RD_N5 RIO3_RD_N4 RIO3_RD_N3 RIO3_RD_N2 RIO3_RD_N1 RIO3_RD_N0 RIO2_RD7 RIO2_RD6 RIO2_RD5 RIO2_RD4 RIO2_RD3 RIO2_RD2 RIO2_RD1 RIO2_RD0 RIO2_RD_N7 RIO2_RD_N6 RIO2_RD_N5 RIO2_RD_N4 RIO2_RD_N3 RIO2_RD_N2 RIO2_RD_N1 RIO2_RD_N0 tsi500 tsi500 2 2 RIO3_R RIO3_R RIO2_R RIO2_R D[0:7] D_N[0:7] D[0:7] D_N[0:7] ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Tuesday, September 30, Torridon - RapidIO Enabled Multi-Pr aiI wth-Pr 0.6 RapidIO Switch - Port 2 & 3 +1.2Vtsi500 +3.3V Power 2003 1 1 +1.2Vtsi500 +3.3V DGND ocessing System 172 61 DGND +1.2V +3.3V of tsi500 ilbride Rev C D A B

Figure A-59. RapidIO Switch—Ports 2 and 3

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-60 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 10 8 6 4 2 2 2x5 Header HD1 JP5 9 7 5 3 1 1 R25 10K R26 10K +3.3V R27 10K 2 R28 10K JP6 TSI500_HW_ TSI500_ 1 TSI500_I TSI500_I X3 8-Pin DIP Socket SW_RST_N RST_N Interrupt pull ups on processor p NT1_N NT0_N +3.3V 4 4 10K R35 TSI500_HW TSI500_ TSI500_IN TSI500_IN SW_RST_N _RST_N T1_N T0_N age. AM31 AN30 AK34 AK33 AP31 AJ33 AJ32 AJ34 D34 C29 A29 A30 B29 B30 C4 E2 TSi500 HARD_RST_B SW_RST BOOTUP_DISABLE_B RESERVE6 RESERVE5 RESERVE4 RESERVE3 RESERVE2 RESERVE1 JT_TDO JT_TRST_B JT_TMS JT_TCK JT_TDI INT(1) INT(0) U4G +3.3V 0.1uF C16 Misc TSi500 4 8 EEPROM U5 GND VCC HSPLL_BYPASS_CLK_n HSPLL_BYPASS_CLK_p HSPLL_RANGE_SEL(1) HSPLL_RANGE_SEL(0) SDA SCL WP CORE_CLK_SEL(0) CORE_CLK_SEL(1) A0 A1 A2 3 3 HSPLL_DGND HSPLL_AGND HSPLL_DVDD HSPLL_AVDD 5 1 2 3 6 7 I2C_SCLK LS0_CLK LS1_CLK I2C_SDA TM_DO TM_DI 10K R36 +3.3V AP6 AM6 AL32 AN31 AJ3 AJ2 AL3 AL2 AN6 AP5 AN4 D33 E33 AM4 D32 C31 10K R37 TSI500_ TSI5 +1.2Vtsi500 TSI5 TSI5 00_TXCLK_IN 00_LS0_CLK 00_LS1_CLK TP12 TP11 TXCLK_IN_N 0.1uF C13

Do Not Fit

R366 R38 TSI5 TSI5

4K7 10K +3.3V R367 R39 00_LS0_CLK 00_LS1_CLK 4K7 10K TSI500 TSI500_TXCLK_IN R368 R40 4K7 10K _TXCLK_IN_N 2 2 0.1uF C15 + 10uF,6.3V Tants C14 R30 R29 2R2 0R 470nH L3 +2.5Vtsi500 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 05, 2003 Torridon - RapidIO Enabled Multi-Pr R31 10K +1.2Vtsi500 +2.5Vtsi500 RapidIO Switch - +3.3V Power R32 10K +3.3V R33 10K 1 1 +1.2Vtsi500 +2.5Vtsi500 +3.3V DGND ic0.6 Misc R34 10K ocessing System 4 3 2 1 SW DIP-4 SW SW1 272 62 +1.2Vtsi500 +2.5Vtsi500 +3.3V DGND 5 6 7 8 of ilbride Rev C D A B

Figure A-60. RapidIO Switch—Misc

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-61 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5

Decoupling +2.5Vtsi500 +2.5Vtsi500 2200pF C171 2200pF C160 +2.5Vtsi500 +2.5Vtsi500 2200pF C192 2200pF C172 2200pF C161 AC34 AP10 AP12 AP14 AP16 AP18 AP20 AP22 AP24 AE34 AA34 W34 AD1 AB1 N34 R34 U34 A11 A13 A15 A17 A19 A21 A23 A25 L34 M1 K1 P1 Y1 V1 T1 2200pF C193 2200pF C173 2200pF C162 P0_IO_VDD P0_IO_VDD P0_IO_VDD P0_IO_VDD P0_IO_VDD P0_IO_VDD P0_IO_VDD P0_IO_VDD P1_IO_VDD P1_IO_VDD P1_IO_VDD P1_IO_VDD P1_IO_VDD P1_IO_VDD P1_IO_VDD P1_IO_VDD P2_IO_VDD P2_IO_VDD P2_IO_VDD P2_IO_VDD P2_IO_VDD P2_IO_VDD P2_IO_VDD P2_IO_VDD P3_IO_VDD P3_IO_VDD P3_IO_VDD P3_IO_VDD P3_IO_VDD P3_IO_VDD P3_IO_VDD P3_IO_VDD U4F TSi500 2200pF C194 2200pF C174 2200pF C163 2200pF C195 2200pF C175 2200pF C164 IO Power TSi500 2200pF C196 2200pF C176 2200pF C165 2200pF C197 2200pF C177 2200pF C166 P0_IO_VSS P0_IO_VSS P0_IO_VSS P0_IO_VSS P0_IO_VSS P0_IO_VSS P0_IO_VSS P1_IO_VSS P1_IO_VSS P1_IO_VSS P1_IO_VSS P1_IO_VSS P1_IO_VSS P1_IO_VSS P2_IO_VSS P2_IO_VSS P2_IO_VSS P2_IO_VSS P2_IO_VSS P2_IO_VSS P2_IO_VSS P3_IO_VSS P3_IO_VSS P3_IO_VSS P3_IO_VSS P3_IO_VSS P3_IO_VSS P3_IO_VSS P3_VREF P2_VREF P1_VREF P0_VREF 2200pF C198 2200pF C178 2200pF C167 M4 K4 P4 T4 Y4 AD4 AB4 AL10 AL12 AL14 AL16 AL20 AL22 AL24 W31 AA31 AE31 AC31 R31 L31 N31 D11 D13 D15 D19 D21 D23 D25 D17 U31 AL18 V4 2200pF C199 2200pF C179 2200pF C168 4 4 2200pF C200 2200pF C180 2200pF C169 2200pF C201 2200pF C181 2200pF C170 0.1uF 0.1uF 0.1uF 0.1uF C151 C149 C147 C145 2 2 2 2 MAX6520 U37 MAX6520 U36 MAX6520 U35 MAX6520 U34 VOUT VOUT VOUT VOUT END END END END VIN VIN VIN VIN 1 1 1 1 3 3 3 3 +2.5Vt +2.5Vt +2.5Vt +2.5Vt 0.1uF C150 0.1uF C148 0.1uF C146 0.1uF C144 si500 si500 si500 si500 3 3

Decoupling tsi500_VDD tsi500_VDD tsi500_VDD tsi500_VDD tsi500_VDD +3.3V 0.1uF C232 0.1uF C222 0.1uF C212 0.1uF C202 0.1uF C182 0.1uF C152 0.1uF C233 0.1uF C223 0.1uF C213 0.1uF C203 0.1uF C183 0.1uF C153 0.1uF C234 0.1uF C224 0.1uF C214 0.1uF C204 0.1uF C184 0.1uF C154 0.1uF C235 0.1uF C225 0.1uF C215 0.1uF C205 0.1uF C185 0.1uF C155 0.1uF C236 0.1uF C226 0.1uF C216 0.1uF C206 0.1uF C186 0.047uF C156 0.1uF C237 0.1uF C227 0.1uF C217 0.1uF C207 0.1uF C187 0.047uF C157 AM32 AM34 AG34 AG31 AN33 AN34 AP26 AP28 AP32 AP33 AP34 AL26 AL28 AL31 AL34 AM1 AM3 AH1 AH4 AN1 AN2 AN5 AP1 AP2 AP3 AP8 AL4 AL8 B31 D1 0.1uF C238 0.1uF C228 0.1uF C218 0.1uF C208 0.1uF C188 0.047uF C158 U4E TSi500 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSSO VSSO VSSO VSSO tsi500_VDD 0.1uF C239 0.1uF C229 0.1uF C219 0.1uF C209 0.1uF C189 0.047uF C159 AF4 GND VDD A28 AF1 GND VDD B3 J34 GND VDD B7 0.1uF C240 0.1uF C230 0.1uF C220 0.1uF C210 0.1uF C190 J31 GND VDD B28 H4 GND VDD B32 H1 GND VDD C2 2 G34 GND VDD C5 2 0.1uF C241 0.1uF C231 0.1uF C221 0.1uF C211 0.1uF C191 G31 GND VDD C7 D31 GND VDD C33 D27 GND VDD D5 D4 GND Power and Ground VDD D6 D9 GND VDD C28 D7 GND TSi500 VDD C30 C34 GND VDD D28 C1 GND VDD D29 C3 GND VDD D30 C32 GND VDD E3 B34 E4 Bulk Decoupling Bulk Decoupling Bulk Decoupling GND VDD +2.5V tsi500_VDD B33 GND VDD E31 +3.3V B2 GND VDD E32 2 1C1185 2 1C1183 2 1C1181 B1 F4

tsi500 GND VDD A34 F31 220uF, Tants 220uF, Tants 220uF, Tants GND VDD A33 GND VDD G1 +3.3V A32 GND VDD G2

+2.5Vtsi500 tsi500_VDD C1182 2 1 A27 GND VDD G3 A9 G4 C1186 C1184 220uF, Tants GND VDD 2 1 2 1 A7 GND VDD G32 A3 G33 220uF, Tants 220uF, Tants GND VDD A2 GND VDD AH2 A1 GND VDD AH3 VDDO VDDO VDDO VDDO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K A31 D2 AL33 AP4 AK4 AN3 AP7 AN32 AN28 AN7 AM33 AM30 AM28 AM7 AM5 AM2 AL30 AL29 AL7 AL6 AL5 AK32 AK31 AK3 AJ31 AJ4 AH34 AH33 AH32 AH31 Page Title : Page Monday, September 29, 2003 Torridon - RapidIO Enabled Multi-Pr tsi500_VDD +2.5Vtsi500 RapidIO Swi +3.3V +3.3V Power c oe 0.6 tch - Power 1 1 tsi500_VDD +2.5Vtsi500 +3.3V DGND ocessing System 372 63 tsi500_VDD +2.5Vtsi500 +3.3V DGND of ilbride Rev C D A B

Figure A-61. RapidIO Switch—Power

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-62 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5 4 4 DGND DGND +3.3V +3.3V +3.3V +3.3V DGND DGND Clocking - RapidIO Page 66 Clocking - Processor Page 65 DGND +3.3V DGND +3.3V 3 3 TSI500_TXCLK_IN_N RIO3_TXCLK_IN_N RIO2_TXCLK_IN_N RIO1_TXCLK_IN_N RIO0_TXCLK_IN_N TSI500_TXCLK_IN TSI500_LS1_CLK TSI500_LS0_CLK RIO3_TXCLK_IN RIO2_TXCLK_IN RIO1_TXCLK_IN RIO0_TXCLK_IN WP3_RTC_CLK WP2_RTC_CLK WP1_RTC_CLK WP3_SYS_CLK WP2_SYS_CLK WP1_SYS_CLK BP_RTC_CLK BP_SYS_CLK PCI_CLK VIA_CLK LA_CLK TSI5 TSI5 TSI500_ TSI5 RIO3_TXCLK_ RIO3_TXCL RIO2_TXCLK_ RIO2_TXCL RIO1_TXCLK_ RIO1_TXCL RIO0_TXCLK_ RIO0_TXCL WP3_RTC_CLK WP2_RTC_CLK WP1_RTC_CLK BP_RTC_CLK 00_LS1_CLK 00_LS0_CLK 00_TXCLK_IN VIA_CLK PCI_CLK LA_CLK WP3_SYS_CLK WP2_SYS_CLK WP1_SYS_CLK BP_SYS_CLK TXCLK_IN_N K_IN K_IN K_IN K_IN IN_N IN_N IN_N IN_N VIA_CLK PCI_CLK LA_CLK WP3_SYS_CLK WP2_SYS_CLK WP1_SYS_CLK BP_SYS_CLK WP3_RTC_CLK WP2_RTC_CLK WP1_RTC_CLK BP_RTC_CLK TSI500_LS1_CLK TSI500_LS0_CLK TSI500_ TSI500_TXCLK_IN RIO3_TXCLK_IN_N RIO3_TXCL RIO2_TXCLK_IN_N RIO2_TXCL RIO1_TXCLK_IN_N RIO1_TXCL RIO0_TXCLK_IN_N RIO0_TXCL TXCLK_IN_N K_IN K_IN K_IN K_IN 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Monday, September 29, 2003 Torridon - RapidIO Enabled Multi-Pr lcig-TpLvl0.6 Clocking - Top Level 1 1 ocessing System 472 64 of ilbride Rev C D A B

Figure A-62. Clocking—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-63 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 5 5

Decoupling +3.3V C627 0.1uF +3.3V C628 0.1uF +3.3V C629 0.1uF 4 4 X4 8-Pin DIP Socket 8-Pin C416 16pF C413

Decoupling 10pF 3 2 1 +3.3V C625 Socket X4 in Socketted is Oscillator gnd Vdd 0.1uF +3.3V

+3.3V 1 2 4 8 R364 C626 16MHz 7

0.1uF Y8 OUT CLK 6 Y15 33.3MHz, Osc

R361 +3.3V

10K 5

100R R362 10K +3.3V 16 15 1 2 MPC905 U58 XTAL_IN XTAL_OUT EN2 EN1 4K7 R1359 R1381 CLK_S ELECT 27R 3 GND VDD 13 +3.3V 11 GND VDD 9 7 GND VDD 5 CLKOUT5 CLKOUT4 CLKOUT3 CLKOUT2 CLKOUT1 CLKOUT0 5 4 2 6 1 3 CCLK OE CLK_SEL CLK_STOP PCLK PCLK U59 MPC9448FA 3 3 12 14 10 8 6 4 FANOUT BU 0...350MHz

R513 R512 R511 R510 32 GND7 VCC7 30 28 GND6 VCC6 26 24 GND5 VCC5 22 +3.3V 20 GND4 VCC4 18 16 14 GND3 FFER VCC3 12 GND2 VCC2 10 27R 27R 27R 27R 8 GND1 VCC1 7 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 WP3_RTC_CLK WP2_RTC_CLK WP1_RTC_CLK BP_RTC_CLK 9 11 13 15 17 19 21 23 25 27 29 31 TP131 TP130 Processors' RTC Clocks R710 R661 R518 R517 R516 R515 R514 WP3_RTC_CLK WP2_RTC_CLK WP1_RTC_CLK BP_RTC_CLK 27R 27R 27R 27R 27R 27R 27R VIA_CLK PCI_CLK LA_CLK WP3_SYS_CLK WP2_SYS_CLK WP1_SYS_CLK BP_SYS_CLK TP174 TP173 TP140 TP139 TP138 2 2 System Clocks VIA_CLK PCI_CLK LA_CLK WP3_SYS_CLK WP2_SYS_CLK WP1_SYS_CLK BP_SYS_CLK ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Tuesday, September 30, Torridon - RapidIO Enabled Multi-Pr lcig-Poesr0.6 Clocking - Processor +3.3V Power 2003 1 1 +3.3V DGND ocessing System 572 65 DGND +3.3V of ilbride Rev C D A B

Figure A-63. Clocking—Processor

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-64 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B +3.3V +3.3V +3.3V +3.3V 3 1 3 1 3 1 3 1 JP35 JP31 JP27 JP23 2 2 2 2 2 pF 220 C933 pF 220 C929 pF 220 C925 pF 220 C921 FBDS1 1DS0 3DS1 +3.3V FS 3 2 +3.3V +3.3V +3.3V +3.3V DS1818R-10/T&R 5 5 3 1 3 1 3 1 3 1 U9 DGND VCC 6 5 4 3 2 1 6 5 4 3 2 1 2 1 JP36 JP32 JP28 JP24 2 2 2 2 SW DIP-6 SW DIP-6 SW Push SW28 SW4 Decoupling SW3 -to-Make RST 2 pF 220 C934 pF 220 C930 pF 220 C926 pF 220 C922 +3.3V

C621 4 3 INV3 3F0 MODE 1DS1

0.1uF 7 8 9 10 11 12 7 8 9 10 11 12 1 +3.3V TP24

C622 Trst~150mS

+3.3V +3.3V +3.3V 0.1uF 3 1 3 1 3 1 JP33 JP29 JP25 2 2 2 2 pF 220 C931 pF 220 C927 pF 220 C923 3 2 1F0 3F1 FBF0 +3.3V 4 1 25MHz Y1 +3.3V +3.3V +3.3V R720 R717 RIO_N0 RIO_M8 RIO_M7 RIO_M5 RIO_M4 RIO_M3 RIO_M2 RIO_M1 RIO_M0 RIO_P_LOAD 3 1 3 1 3 1 RIO_M6 RIO_N1 JP34 JP30 JP26 2 2 2 4K7 4K7 18pF C973 22pF C972 2 pF 220 C932 pF 220 C928 pF 220 C924 1F1 FBDS0 3DS0 18 20 19 23 17 27 22 32 31 30 29 28 26 25 24 6 5 4 3 2 1 ICS8442 U10 S_CLOCK S_LOAD S_DATA T_CLK MR VCO_SEL nXTAL_SEL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 nP_LOAD XTAL2 XTAL1 1 gnd Vdd 4 +3.3V 4 2 4 nFOUT1 nFOUT0 25MHz, Osc FOUT1 FOUT0 VDDA OUT CLK TEST GND GND VDD VDD Y2 nc 3 12 15 21 11 14 8 16 13 10 9 7 1F1 1F0 INV3 3F1 3F0 FBDS1 FBDS0 FBF0 MODE 1DS1 1DS0 3DS1 3DS0 FS R666 RIO_TXCLK_IN_N RIO_TXCLK

0.01uF C23 27R +3.3V _IN_P C252 1 + 10R R715 10uF,6.3V Tants 33 19 24 32 56 34 18 23 31 69 46 51 22 52 21 53 99 98 57 48 68 72 71 70 73 74 79 80 81 78 77 7 2 4 6 3 5 R718 R716 CY7B994V U77 DIS1 1DS1 1DS0 1F1 1F0 DIS2 2DS1 2DS0 2F1 2F0 INV3 DIS3 3DS1 3DS0 3F1 3F0 DIS4 4DS1 4DS0 4F1 4F0 FBDIS FBDS1 FBDS0 FBF0 OUTPUT_MODE FS REFSEL REFB- REFB+ REFA- REFA+ FBSEL FBKB- FBKB+ FBKA- FBKA+ 51R 51R 1 GND +3.3V

8 10 R713 +3.3V GND VCCN 4K7 12 GND VCCN 15 13 37 R714 GND VCCN 4K7 17 GND VCCN 42 25 60 GND VCCN 19 18 42 43 26 GND VCCN 65

27 85 ICS8516 U11

GND VCCN CLK nCLK OE2 OE1 28 GND VCCN 90 35 GND VCCN 95 39 GND 3 40 GND 7 GND VDD 1 3 44 GND 17 GND VDD 6 +3.3V 47 GND VCCQ 20 20 GND VDD 12 50 GND VCCQ 29 30 GND VDD 25 55 GND VCCQ 30 41 GND VDD 31 58 GND VCCQ 45 44 GND VDD 36 62 GND VCCQ 49 63 54 GND VCCQ nQ15 nQ14 nQ13 nQ12 nQ11 nQ10 67 75 Q15 Q14 Q13 Q12 Q11 Q10 nQ9 nQ8 nQ7 nQ6 nQ5 nQ4 nQ3 nQ2 nQ1 nQ0 GND VCCQ Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 82 GND VCCQ 76 83 GND 21 23 26 28 32 34 38 40 45 47 2 4 8 10 13 15 37 39 46 48 3 5 9 11 14 16 22 24 27 29 33 35 87 GND 88 GND LOCK 100 92 GND QFA1 QFA0 93 GND 1QB1 1QB0 1QA1 1QA0 2QB1 2QB0 2QA1 2QA0 3QB1 3QB0 3QA1 3QA0 4QB1 4QB0 4QA1 4QA0 97 GND R727 R726 R725 R724 R723 R722 R721 R719 R712 R711 TP248 84 86 96 94 91 89 59 61 64 66 43 41 38 36 9 11 14 16 TP266 TP265 TP260 TP259 TP257 TP256 TP112 TP111 TP110 TP109 TP108 TP107 51R 51R 51R 51R 51R 51R 51R 51R 51R 51R R667 R668 R1360 RIO3_TXCLK_ RIO3_TXCL RIO2_TXCLK_ RIO2_TXCL RIO1_TXCLK_ RIO1_TXCL RIO0_TXCLK_ RIO0_TXCL TSI500_ TSI500_TXCLK_IN TXCLK_IN_N K_IN K_IN K_IN K_IN TP255 TP254 TP250 TP253 TP252 TP251 27R 27R 0R IN_N IN_N IN_N IN_N TSI5 TSI5 00_LS0_CLK 00_LS1_CLK RIO3_TXCLK_ RIO3_TXCLK_IN RIO2_TXCLK_ RIO2_TXCLK_IN RIO1_TXCLK_ RIO1_TXCLK_IN RIO0_TXCLK_ RIO0_TXCLK_IN TSI500_ TSI5 Decoupling 00_TXCLK_IN +3.3V +3.3V

C935 C624 TXCLK_IN_N

2 0.1uF 0.1uF 2 +3.3V +3.3V C915 C909 IN_N IN_N IN_N IN_N 0.1uF 0.1uF TSI5 TSI5 +3.3V +3.3V C916 C910 00_LS0_CLK 00_LS1_CLK 0.1uF 0.1uF +3.3V +3.3V C917 C911 0.1uF 0.1uF +3.3V +3.3V

RapidIO Switch Clocks C918 C912 0.1uF 0.1uF +3.3V +3.3V C919 C913 Decoupling

0.1uF 0.1uF +3.3V

+3.3V +3.3V C966 C920 C914 0.1uF

0.1uF 0.1uF +3.3V C967 0.1uF +3.3V C968 0.1uF +3.3V ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K C969

RapidIO Clocks 0.1uF +3.3V

Page Title : Page C970 Wednesday, October 01, 2003

Torridon - RapidIO Enabled Multi-Pr 0.1uF +3.3V C971 0.1uF lcig-RpdO0.6 Clocking - RapidIO +3.3V Power 1 1 +3.3V DGND ocessing System 672 66 DGND +3.3V of ilbride Rev C D A B

Figure A-64. Clocking—RapidIO

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-65 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B

Decoupling +3.3VCPLD "System RESET" 8 7 6 5 4 3 2 1

C738 "PWR_ 2 1

0.1uF "CPLD SW DIP-8 SW SW25 Push-to-Make 2 1 ON/OFF" SW23 +3.3VCPLD RESET" 2 1 +3.3VCPLD Push 4 3 9 10 11 12 13 14 15 16 Push-to-Make

C739 SW19 -to-Make

0.1uF SW27 +3.3VCPLD 4 3 +3.3VCPLD 4 3 3 4

R274 10K, RN RN207

+3.3VCPLD R192 4K7 1 MR VCC U45 MAX811

4K7 2 +3.3VCPLD

5 C740 3 5 0.1uF 4 5 RESET 6 10 GND 7 1 PB_RESET_N

+3.3VCPLD 8 +3.3VCPLD ON_OFF

9 gnd Vdd 1 C741 2 2 4 0.1uF 66MHz USR7 USR6 USR5 USR3 USR2 USR1 USR0 USR4 +3.3VCPLD OUT CLK Y6 3 10K R365 VIA_INT USR4 PORST USR7 R USR6 R USR5 R USR4 Switch USR3 WP3 USR2 WP2 USR1 WP1 USR0 BP Switch C Note :- Key for R778 R765 +3.3VCPLD

R703 10K VIA_INT 27R 27R PS_ON ontrols eserved eserved eserved Reset Reset Reset Reset Switches +3.3VCPLD Flash Bank R1361 PLD_LA 4K7 PLD_CLK _CLK WP2_COP_HRESET_N WP2_COP_SRESET_N WP3_COP_SRESET_N WP3_COP_HRESET_N WP3_HRESET_REQ_N SYSTEM_RESET_N BP_HRESET_REQ_N WP2_COP_T TSI500_SW_RST_N WP2_RST_CONF_N WP3_RST_CONF_N 3.3V_Power_Good 5V_Power_Good VIA_RESET_REQ_N DDR_P WP2_RES WP3_RES SPEAKER WP2_HRESET_N WP2_SRE WP3_HRESET_N WP3_SRE DDR_Powe Core_Power_On WP2_T WP3_T 5V_Power_On PCI_INTA_N ower_Good 4 4 PWR_OK RST_N DLALE PS_ON ET_N ET_N SET_N SET_N RST_N RST_N FLA8 LALE LA8 ID3 ID2 ID1 ID0 r_On +3.3VCPLD

R1382 1K 3.3V_Power_Good TSI500_ BP_HRESET_REQ_N DDR_Po ID3 WP2_RE ON_OFF WP2_COP_ WP2_RST_CONF_N WP2_HRESET_N WP2_SRE WP2_T WP2_COP_HRESET_N WP2_COP_SR SYSTEM_RESET_N 5V_Power_Good WP3_HRESET_REQ_N FLA8 LA8 ID2 WP3_RE PORST 5V_Power_On PCI_INTA_N WP3_RST_CONF_N PB_RE WP3_COP_SR VIA_RESET_R WP3_HRESET_N WP3_SRE WP3_T WP3_COP_HRESET_N Core_Power_On DLALE LALE ID1 DDR_Po PWR_OK LED_N0 LED_N6 LED_N3 PS_ON LED_N5 LED_N2 USR7 USR0 USR4 USR2 USR1 4 3 2 1 HEAD +5VSB HD32 SET_N RST_N RST_N SW_RST_N wer_On wer_Good C410 SET_N SET_N SET_N SET_N ER4x1 TDO TMS TCK ID[3:0] PLD_CLK TDI TRST_N 10R R340 EQ_N ESET_N ESET_N 2.2uF Speaker header TP329 TP330 TP328 TP282 TP327 TP326 TP321 TP318 TP283 TP320 TP313 TP307 TP306 TP303 TP289 TP288 TP276 470pF C411 22uF,6.3V C409 154 156 129 165 164 163 162 161 160 159 158 175 174 173 172 171 170 169 168 84K5, 1% R341 68 66 91 41 10 11 12 14 15 16 17 18 19 20 21 30 29 28 27 26 25 24 23 39 38 37 36 35 34 33 32 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 11 12 5 3 5 6 7 8 9 7 6 4 2 CLK_3_I CLK_2_I CLK_1_I CLK_0_I TDO TDI TMS TCK A14 A12 A10 A8 A6 A4 A2_GOE0 A0 B14 B12 B10 B8 B6 B4 B2 B0 C14 C12 C10 C8 C6 C4 C2 C0 D14 D12 D10 D8 D6 D4 D2 D0 E14 E12 E10 E8 E6 E4 E2 E0 F14 F12 F10 F8 F6 F4 F2 F0 G14 G12 G10 G8 G6 G4 G2 G0 H14 H12 H10 H8 H6 H4 H2 H0 TOFF SHDN COMP FBSEL VCC IN2 IN1 U29 U55 MAX1831

167 GND_BANK0 VCCO_BANK0 4 155 40 PGND PGND

GND_BANK0 VCCO_BANK0 GND REF 55 56 LX4 LX3 LX2 LX1 GND_BANK0 VCCO_BANK0 FB 13 GND_BANK0 VCCO_BANK0 166 3 31 GND_BANK0 VCCO_BANK0 22 3 15 13 16 14 3 1 10 9 8 ispMA

143 GND_BANK1 VCCO_BANK1 110 +3.3VCPLD CH4256 119 GND_BANK1 VCCO_BANK1 144 101 GND_BANK1 VCC0_BANK1 78 2 1 CDRH6

79 128 MBRS130L

GND_BANK1 VCCO_BANK1 D11 67 GND_BANK1 VCCO_BANK1 92 1 2uH, 3A L17 D28-3R0

153 GND VCC 42 1uF,10V C412 134 GND VCC 69 65 GND VCC 130 46 GND VCC 157 2 2 176 GND P2_GOE1 VCC 90 GND VCC 88 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 M10 M12 M14 O10 O12 O14 N10 N12 N14 P10 P12 P14 K10 K12 K14 L10 L12 L14 J10 J12 J14 M0 M2 M4 M6 M8 I10 I12 I14 FP_POWER_ON FP_RESET ATX_BP 5V_Power_Good Core_Power_Good 3.3V_Power_Good DDR_Po TEST O0 O2 O4 O6 O8 N0 N2 N4 N6 N8 P0 P4 P6 P8 K0 K2 K4 K6 K8 L0 L2 L4 L6 L8 J0 J2 J4 J6 J8 I0 I2 I4 I6 I8 104 103 102 137 136 135 80 81 82 83 84 1 45 44 43 89 133 132 131 109 108 107 106 105 151 142 141 140 139 138 147 146 145 95 94 93 152 150 149 148 100 99 98 97 96 116 117 118 85 86 87 125 126 127 111 112 113 114 115 75 76 77 70 71 72 73 74 120 121 122 123 124 wer_Good 10K, RN RN214 +3.3VCPLD 1

2 +3.3VCPLD +

3 120uF,4V Tants C408

TP325 TP324 TP323 TP317 TP316 TP315 TP312 TP311 TP293 TP291 TP285 TP284 TP281 TP277 TP275 4 5 6 10 7 8

9 @ 1A 3.3V TSI500_HW VIA_RESET_N PCI_RST_N FP_LED_N 3.3V_Power_On IO_LV_Power_On WP1_HRESET_REQ_N FP_RESET WP3_COP_ WP1_RE WP1_COP_ SHUTDOWN WP3_G1_ WP2_G1_ WP1_G1_ BP_G2_ BP_G1_ VIA_ON ATX_BP BP_COP_SR BP_COP_HRESET_N BP_TRST_N BP_SRE BP_HRESET_N BP_RST_CONF_N WP1_COP_SR WP1_COP_HRESET_N WP1_T WP1_SRE WP1_HRESET_N WP1_RST_CONF_N SYS_RESET_N BP_COP_TRST_N WP2_HRESET_REQ_N Core_Power_Good FP_POWER_ON LED_N7 LED_N4 ADS_HRESET_N LED_N1 USR5 USR3 USR6 FP_LED_N SPEAKER RST_N RESET_N RESET_N SET_N SET_N DEBUG2 DEBUG1 DEBUG0 RESET_N RESET_N RESET_N SET_N TRST_N TRST_N _RST_N ESET_N TEST ID0 ESET_N 2 2 +3.3VCPLD TSI500_HW VIA_RESET_N PCI_RST_N 3.3V_Power_On IO_LV_Power_On WP1_HRESET_REQ_N WP3_COP_TRST_N WP1_RE WP1_COP_TRST_N SHUTDOWN WP3_G1_ WP2_G1_ WP1_G1_ BP_G2_ BP_G1_ VIA_ON ATX_BP ADS_HRESET_N BP_COP_SR BP_COP_HRESET_N BP_TRST_N BP_SRESET_N BP_HRESET_N BP_RST_CONF_N WP1_COP_SR WP1_COP_HRESET_N WP1_T WP1_SRE WP1_HRESET_N WP1_RST_CONF_N SYS_RESET_N BP_COP_ WP2_HRESET_REQ_N Core_Power_Good

3 1 RST_N HD30 330R R1370 RESET_N RESET_N 2 SET_N TRST_N RESET_N RESET_N RESET_N SET_N _RST_N ESET_N Front Panel Connection Power Indicator - ESET_N IO_LV_Power_On 3.3V_Power_On DDR_Po 5V_Power_On Core_Power_On PCI_RST_N TSI500_ ID3 ID2 ID1 ID0 BP_HRESET_REQ_N BP_COP_HRESET_N BP_COP_ BP_COP_SR PLD_LA PS_ON LED_N7 LED_N6 LED_N5 LED_N4 LED_N3 LED_N2 LED_N1 LED_N0 _CLK SW_RST_N wer_On TRST_N LD20 "Heart LD19 Low Voltage IO LD18 DDR Power is LD17 Core Power is LD16 +3.3V Po LD15 +5V Power is LD14 ATX Power LD13 +5VSB_ LED I Note :- Key for TDO TMS TCK WP3_RESET_N WP2_RESET_N WP1_RESET_N ADS_HRESET_N TDI ESET_N ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K R1369 R1368 R1367 R1366 R1365 R1364 R1363 R1362 Page Title : Page Wednesday, October 01, 2003 Torridon - RapidIO Enabled Multi-Pr FP_POWER_ON FP_RESET 10K, RN RN212 Panel Connection Power On - Front ndicates 330R 330R 330R 330R 330R 330R 330R 330R ee oto 0.6 Control Reset 1 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

2 +3.3VCPLD LEDs

3 ATX is on D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A D14A D15A CLKA GND 5V Beat"

4 5 LD39 LD19 LD18 LD17 LD16 LD15 LD14 LD13 wer is Good

+5VSB 6 10 P20 GND Supply is on Power 7 43 42 41 40 39 1 1 1 1 1 1 1 1

8 2 1 CLKB D10B D11B D12B D13B D14B D15B SDA D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B SCL Good Good 1 9 1 HD24 Good DGND Power is On +5VSB R194 4 18 16 14 12 10 8 6 38 36 34 32 30 28 26 24 22 20 2 1K 9 7 5 3 1 MICTOR 38 SO 2x5 Header HD9

ocessing System 2 1 2 2 2 2 2 2 2 2 HD25 LED_GREEN LED_YELLOW LED_YELLOW LED_YELLOW LED_YELLOW LED_YELLOW LED_YELLOW LED_YELLOW 10 8 6 4 2 Connection Panel Reset - Front 772 67 +3.3VCPLD CKET DGND +5VSB 3.3V_Power_Good 5V_Power_Good DDR_Po Core_Power_Good ON_OFF PB_RE BP_RST_CONF_N SYS_RESET_N TSI500_HW DEBUG2 BP_HRESET_N DEBUG1 DEBUG0 BP_SRESET_N BP_T PWR_OK +3.3VCPLD of ilbride RST_N SET_N wer_Good _RST_N Rev C D A B

Figure A-65. Reset Control

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-66 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B SENSE_VSS SENSE_VDD Core_Power_On 5 5 SENSE_VSS SENSE_VDD Core_Power_On PS - Core Page 69 SENSE_VSS SENSE_VDD Core_Power_On Core_Power_Good DGND +3.3V +12V Vdd 3.3V_Power_Good 3.3V_Power_On 5V_Power_Good 5V_Power_On Vdd +3.3V +12V DGND PWR_OK PS_ON 4 4 Core_Power_Good 3.3V_Power_Good 5V_Power_Good PWR_OK PS_ON 3.3V_Power_On 5V_Power_On Core_Power_Good Vdd +3.3V +12V DGND PS - Power Supply Page 71 3.3V_Power_Good 3.3V_Power_On 5V_Power_Good 5V_Power_On PWR_OK PS_ON IO_LV_Power_On DDR_Pow +5VSB_BP +3.3V_BP +5V_BP +5VSB CGND DGND +3.3V er_On +12V -12V +5V 3 3 CGND DGND +3.3V_BP +5V_BP +3.3V +5V +5VSB +5VSB_BP +12V -12V DDR_Po IO_LV_Power_On wer_On CGND DGND +3.3V_BP +5V_BP +3.3V +5V +5VSB +5VSB_BP +12V -12V PS - IO PS Page 70 DDR_Power_On IO_LV_Power_On DDR_Power_Good +1.5VGEther +2.5VGEther tsi500_VDD +1.2Vtsi500 +2.5Vtsi500 DGND +2.5V +12V +5V +2.5V +5V +12V DDR_Po +1.5VGEther +2.5VGEther tsi500_VDD +1.2Vt +2.5Vt DGND 2 2 si500 si500 wer_Good DDR_P DGND +1.5VG +2.5VG tsi500_VDD +1.2V +2.5V +2.5V +5V +12V tsi500 tsi500 ower_Good Ether Ether ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Thursday, September 25, Torridon - RapidIO Enabled Multi-Pr Power Supply - Top L 2003 1 1 vl0.6 evel ocessing System 872 68 of ilbride Rev C D A B

Figure A-66. Power Supply—Top Level

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B 1 1 0 1 0 1 0 VID4 VID3 VID2 Note :- Default settings 6 5 4 3 2 1 SW DIP-6 SW SW20 This sets

C1187 +12V

2 1 7 8 9 10 11 12 + 680uF, 16V, Aluminium Electrolytic 1.2V 5 5 Core_Power_Good 10K R318 for Switches 10K R319 TP121 VID1 VID0 10K R288 Vo_Sence- Core_Power_Good VID1 VID3 10K R289 +3.3V 10K R290 10K R291 +12V VID4 VID3 VID2 VID1 VID0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 5 4 3 2 1 VRM 9.0 Conne P36 Vo-_10 Vo+_9 Vo-_9 Vo+_8 Vo-_8 Vo+_7 Vo-_7 Vo+_6 Vo-_6 Vo+_5 Vo-_5 Vo+_4 Vo-_4 Vo+_3 Vo-_3 Vo+_2 Vo-_2 Vo+_1 Vo-_1 Reserved_3 Vo Sen- PWRGD Reserved_2 VID1 VID3 Reserved_1 Vin+_4 Vin+_3 Vin+_2 Vin+_1 ctor Reserved_4 4 4 VRM-pres Vo Sen+ Vo+_10 Vo+_11 Vo+_12 Vo+_13 Vo+_14 Vo+_15 Vo+_16 Vo+_17 Vo+_18 OUTEN Vo-_11 Vo-_12 Vo-_13 Vo-_14 Vo-_15 Vo-_16 Vo-_17 Vo-_18 Vo-_19 Vin-_1 Vin-_2 Vin-_3 Vin-_4 Ishare VID0 VID2 VID4 Vo+ 51 52 58 55 56 57 33 35 37 41 43 45 47 49 50 32 34 36 38 40 42 44 46 48 53 59 60 61 62 54 39 Vdd

C1144 Vdd Vo_Sence+ Core_Power_On 2 1 + 560uF, 6.3V, OSCON C1145 2 1 VID0 VID2 VID4 + 560uF, 6.3V, OSCON C1146 2 1 + 560uF, 6.3V, OSCON C1147 Core_Power_On 2 1 + 560uF, 6.3V, OSCON C1148 2 1 + 560uF, 6.3V, OSCON C1149 2 1 + 560uF, 6.3V, OSCON A2 NXI100 31(32) 12(51) 11(52) 1(62) C1150 2 1

NXI100 Module +

3 560uF, 6.3V, OSCON 3 C1151 2 1 + 560uF, 6.3V, OSCON

C1152 4.7uF, 6.3

C1153 4.7uF, 6.3

C1154 4.7uF, 6.3

C1155 4.7uF, 6.3

C1156 4.7uF, 6.3

C1157 4.7uF, 6.3

C1158 4.7uF, 6.3

C1159 4.7uF, 6.3

C1160 Vo_Sence- Vo_Sence+ 4.7uF, 6.3

C1161 4.7uF, 6.3 2 2

Do Not Fit R641 0R R640 R642 0R R639 0R 0R SENSE_VDD ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K SENSE_VSS Page Title : Page Wednesday, October 29, 2003 Torridon - RapidIO Enabled Multi-Pr Power Supply - Core Vol Power Processor Core +3.3V +12V Vdd 25mV step Size @ 81A with 1.1V to 1.85V +3.3V +12V SENS SENSE_VDD Vdd 1 1 DGND E_VSS ae0.6 tage ocessing System Vdd +3.3V +12V DGND 972 69 of ilbride Rev C D A B

Figure A-67. Power Supply—Core Voltage

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-68 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B

Decoupling +5V C845 0.1uF +5V C846 0.1uF IO_LV_Power_On IO_LV_Power_On IO_LV_Power_On IO_LV_Power_On 5 5

C345 +5V C335 +5V

C340 +5V C327 +5V 10R R283 10R R279

2.2uF 10R R281 2.2uF 10R R276 2.2uF 2.2uF IO_LV_Power_On IO_LV_Power_On 470pF C346 470pF C336 IO_LV_Power_On IO_LV_Power_On 470pF C341 470pF C328 22uF,6.3V C344 22uF,6.3V C334 22uF,6.3V C339 22uF,6.3V C326 182K, 1% R286 182K, 1% R280 0K 0.5% 100K. R282 0.5% 100K. R278 11 12 11 12 5 5 7 6 4 2 7 6 4 2 11 12 11 12 7 6 4 2 7 6 4 2 5 5 TOFF SHDN COMP FBSEL VCC IN2 IN1 TOFF SHDN COMP FBSEL VCC IN2 IN1 TOFF SHDN COMP FBSEL VCC IN2 IN1 TOFF SHDN COMP FBSEL VCC IN2 IN1 U50 U48 MAX1831 MAX1831 U49 U46 MAX1831 MAX1831 PGND PGND PGND PGND GND GND REF REF LX4 LX3 LX2 LX1 PGND PGND LX4 LX3 LX2 LX1 PGND PGND Check resistor vlaues for 1.2V Check resistor vlaues for 1.2V o/p FB FB GND GND REF REF LX4 LX3 LX2 LX1 LX4 LX3 LX2 LX1 FB FB 15 13 15 13 8 8 16 14 3 1 16 14 3 1 10 10 9 9 15 13 15 13 16 14 3 1 16 14 3 1 10 10 9 9 8 8

2 1 DO5010P-1 2 1 DO5010P-1 MBRS130L MBRS130L 2 1 DO5010P-1 2 1 DO5010P-1 D5 D3 1 1 MBRS130L MBRS130L D4 D2 1 1 10uH, 6A L13 10uH, 6A L11 L12 10uH, 6A L9 10uH, 6A 03HC 03HC 1uF,10V C347 1uF,10V C337 03HC 03HC 1uF,10V C342 1uF,10V C330 4 4 2 2 2 2 10K, 1/8W R285 3K3 R1372 tsi500_VDD +2.5Vtsi500 +1.5V +2.5V GEther GEther + + + + 47uF, Tants C343 47uF, Tants C338 47uF, Tants C333 47uF, Tants C325 (typi 1.518A. (typi 979mA. = 896mA + .V@ 2A 1.3V 1.5A 2.5V @ 2.5A 1.5V @ (typi = 1.7A. 340mA x 5 @ 2A 2.5V (typi 1.175A. = 235mA x 5 Ethernet Gigabyte cal) cal) cal) cal) 83mA IO_LV_Power_On

C939 +5V 10R R681 2.2uF 3 3 IO_LV_Power_On 470pF C938 22uF,6.3V C937

182K, 1% R684 C1165 +12V 2 1 11 12 + 7 6 4 2 5 270uF, 16V TOFF SHDN COMP FBSEL VCC IN2 IN1 C1166 U78

MAX1831 2 1 + 270uF, 16V PGND PGND GND REF LX4 LX3 LX2 LX1 Vdd_Sense- FB Vdd_Sense+ 10 9 15 13 16 14 3 1 8

2 1 DO5010P- R1373 R1374 MBRS130L D14 1 L26 10uH, 6A 103HC 1uF,10V C940 DDR_P DDR_P 0R 0R 2 +2.5V ower_Good ower_On 82R R1376 10R R1375 10K, 1/8W R683 900R R682 2 2 Decoupling +5V Vdd_Sense+ Vdd_Sense-

+1.2Vtsi500 C847 0.1uF DDR_Po +5V C848 DDR_Po + wer_Good

47uF, Tants C936 0.1uF +2.5V Switch RapidIO +5V +12V C941 0.1uF wer_On (typi 1.518A. .V@ 2A 1.2V cal) J2-15 J2-14 J2-13 J2-12 J2-11 J2-10 J2-9 J2-8 J2-7 J2-6 J2-5 J2-4 J2-3 J2-2 J2-1 J1-7 J1-6 J1-5 J1-4 J1-3 J1-2 J1-1 A1 DDR12 Vdd_5 Vdd_4 Vdd_3 Vdd_2 Vdd_1 Vdd Sense + Vdd Sense - Ground_7 Ground_6 Ground_5 Ground_4 Ground_3 Vtt_2 Vtt_1 Vtt Ref +12V_3 +12V_2 +12V_1 Ground_2 Ground_1 Output Enable Power Good ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Wednesday, OctoberWednesday, 29, 2003 Torridon - RapidIO Enabled Multi-Pr +1.5VGEther +2.5VGEther tsi500_VDD +1.2V +2.5V Power C1162 +2.5V +5V +12V oe upy-I 0.6 Power Supply - IO 2 1 + tsi500 tsi500 680uF, 6.3V C1163 2 1 + +1.5VGEther +2.5VGEther tsi500_VDD +1.2Vtsi500 +2.5Vtsi500 +2.5V +5V +12V DGND 680uF, 6.3V

1 C1164 1 2 1 + 680uF, 6.3V

C369 2.5V @ 25A ocessing System +

DDR SDRAM 220uF, Tants +1.5V +2.5V tsi500_VDD +1.2Vtsi500 +2.5Vtsi500 +2.5V +5V +12V DGND 072 70

GEther GEther C896 + +2.5V of 220uF, Tants ilbride Rev C D A B

Figure A-68. Power Supply—IO Voltages

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-69 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics C D A B

Decoupling +3.3V C665 PS_ON 0.1uF +3.3V 330uF, Tants C666

0.1uF +5V

+3.3V 3 1 C292 C962 HD26 330R R1371 10uF, 6.3V 2 +3.3V PS_ON

C963 Front Panel Connection Power Indicator - -12V

5 10uF, 6.3V + 5 _ATX +5V +5VSB -12V C964 _ATX

10uF, 6.3V supply or the backplane either the ATX power +5V Stand By comes from _ATX +5V + C296

C965 330uF, Tants

10uF, 6.3V -12V +5VSB_BP +3.3V_ATX TP334 + 330uF, Tants C293 +5VSB +5V_ATX 20 19 18 17 16 15 14 13 12 11 3.3V_Power_Good 3.3V_Power_On 5V_Power_Good 5V_Power_On ATX_PWR_ 5V 5V -5V GND GND GND PS-ON GND -12V 3.3V P9 CONN PW-OK 5VSB GND GND GND 3.3V 3.3V 12V Bulk Decoupling 5V 5V 3.3V_Power_Good 5V_Power_Good 3.3V_Power_On 5V_Power_On 9 7 5 3 8 10 6 4 C1175 2 1 +3.3V 2 1 + +3.3V_ATX 10uF,6.3V Tants

4 C1176 4 +3.3V +3.3V_BP 2 1 + MAX5918

10uF,6.3V Tants +5V_BP +5V_ATX C1177 16 15 11 6 1 +3.3V +

2 1 +3.3V_ATX 0.1uF C407 0.1uF C404 330uF, Tants C294 + GND PGOOD2 PGOOD1 ON2 ON1 U53

10uF,6.3V Tants +5VS

C1178 +5V_ATX +3.3V B_ATX 2 1 14 3 + IN2 IN1 10uF,6.3V Tants

C1179 Short pins 53 & 54 close to U53 +3.3V +12V 2 1 13 4 + SENSE2 SENSE1 + 2 330uF, Tants C295 2 FDB7045L Q8

10uF,6.3V Tants U53Short pins 3 & 4 close to FDB7045L Q7 C1180 1 12 GATE2 3 +3.3V GATE1 5 1 2 1 3 + 20K. 1% 10 LIM2 +

10uF,6.3V Tants R336 330uF, Tants C297 PWR_OK 20K. 1% 7 R337 LIM1

20K. 1% 2 MON2 MON1 R338 TIM Do Not Fit 9 8 3 3 2 1 ATX_12V_P P37 GND GND R335 1K R334 0.5% 442K. R333 0.5% 100K. R332 0.5% 100K. R331 0.5% 715K. R509 8K06. 1% WR_CONN 12V 12V 3 4 + C406 + 1000uF,16V Electolytic 1000uF,16V Electolytic C405 +3.3V +5V + 330uF, Tants C1286 + 330uF, Tants C1287 + 330uF, Tants C1288 +12V + 330uF, Tants C1289 2 2 MH1 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K MH2 Mounting H Page Title : Page Friday, October 24, 2003 Friday, Torridon - RapidIO Enabled Multi-Pr MH3 oles Power Supply - MH4 +3.3V_BP +5V_BP +5VSB_BP +5VSB Power +3.3V +5V +12V -12V MH5 upidPwr0.6 Supplied Power 1 1 +3.3V +5V +3.3V_BP +5V_BP +5VSB_BP +5VSB +12V -12V CGND DGND MH6 ocessing System 172 71 CGND DGND +3.3V +5V +3.3V_BP +5V_BP +5VSB_BP +5VSB +12V -12V of ilbride Rev C D A B

Figure A-69. Power Supply—Supplied Power

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-70 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE C D A B 5 5

Decoupling +3.3V C806 0.1uF WP3_TXD WP2_TXD WP1_TXD WP3_RXD WP2_RXD WP1_RXD 4 4 WP3_RXD WP2_RXD WP1_RXD WP3_TXD WP2_TXD WP1_TXD 0.1uF C539 0.1uF C537 +3.3V 24 12 13 14 10 11 8 7 5 4 3 1 MAX3387 R3out R2out R1out T3in T2in T1in FORCEON FORCEOFF C2- C2+ C1- C1+ U63 +3.3V 22 GND Vcc 23 INVALID 0.1uF C535 T3out T2out T1out R3in R2in R1in V+ V- Vl 19 20 21 6 15 16 17 18 9 2 +3.3V 0.1uF C538 3 3 0.1uF C540 C536 0.1uF WP3 Debug Port HD34 2

3 1 WP2 Debug Port HD35 2

3 1 HD36 WP1 Debug Port 2

3 1 2 2 ae Sheet Date: Size : System C Engineer : Rod Watt, NCSG Platforms Group, Motorola Ltd.,East K Page Title : Page Friday, September 26, 2003 Torridon - RapidIO Enabled Multi-Pr P-DbgPrs0.6 - Debug Ports WP 1 1 +3.3V Power ocessing System +3.3V DGND 272 72 DGND +3.3V of ilbride Rev C D A B

Figure A-70. WP—Debug Ports

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor A-71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Schematics

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 A-72 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Appendix B Revision History

Table B-1. Revision History

Revision Release Date Changes

0.1 12/2004 Modified footer on front cover 0 11/2004 Initial release

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor B-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Revision History

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 B-2 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE