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MPC8560UG Rev. 0.1 10/2004 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number Chapter 1 References 1.1 Glossary ...............................................................................................................................1 1.2 References............................................................................................................................3 Chapter 2 Introduction 2.1 Background..........................................................................................................................1 2.2 Scope....................................................................................................................................1 2.3 System Overview.................................................................................................................1 Chapter 3 Motherboard 3.1 Motherboard Overview........................................................................................................1 3.2 Motherboard Features ..........................................................................................................2 Chapter 4 Processor 4.1 Overview..............................................................................................................................1 4.2 MPC8560 Processor Configuration .....................................................................................2 4.3 COP Interface ......................................................................................................................4 Chapter 5 Flash 5.1 Overview..............................................................................................................................1 5.2 Flash.....................................................................................................................................1 Chapter 6 DDR 6.1 Overview..............................................................................................................................1 6.1.1 DDR Memory ..................................................................................................................1 6.1.2 The MPC8560’s DDR Memory Controller .....................................................................1 6.1.2.1 Available Signals .........................................................................................................1 6.2 Design Considerations .........................................................................................................2 6.2.1 Signal Termination...........................................................................................................2 6.2.2 Signal Connections ..........................................................................................................3 6.2.2.1 Address and Control Signals .......................................................................................3 6.2.2.2 Data..............................................................................................................................3 6.2.2.3 Clock............................................................................................................................4 MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1 Freescale Semiconductor -iii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Contents Paragraph Page Number Title Number 6.2.2.4 Serial Presence Detect .................................................................................................4 6.2.2.5 DDR SDRAM Power ..................................................................................................4 6.2.2.6 Voltage Generation ......................................................................................................5 6.3 Physical Implementation......................................................................................................5 6.3.1 Schematics .......................................................................................................................7 6.4 Layout ................................................................................................................................12 6.4.1 Address and Control ......................................................................................................12 6.4.2 Data................................................................................................................................14 6.4.3 Clocks ............................................................................................................................17 6.4.4 DDR Power....................................................................................................................19 Chapter 7 RapidIO 7.1 Overview..............................................................................................................................1 7.1.1 RapidIO Interconnect.......................................................................................................1 7.1.2 The MPC8560’s RapidIO Controller...............................................................................1 7.1.3 Signals Descriptions ........................................................................................................1 7.2 Design Considerations .........................................................................................................2 7.2.1 Signal Termination...........................................................................................................2 7.2.2 Signal Connections ..........................................................................................................3 7.3 Logic Analyser Connection .................................................................................................5 7.4 Physical Connections...........................................................................................................7 7.5 Layout Considerations .......................................................................................................11