DOCSLIB.ORG

A Roofline Model of Energy

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Roofline Model of Energy Preprint – To appear in the IEEE Int’l. Parallel & Distributed Processing Symp. (IPDPS), May 2013 A roofline model of energy Jee Whan Choi Daniel Bedard, Robert Fowler Richard Vuduc Georgia Institute of Technology Renaissance Computing Institute Georgia Institute of Technology Atlanta, Georgia, USA Chapel Hill, North Carolina, USA Atlanta, Georgia, USA [email protected] fdanb,[email protected] [email protected] Abstract—We describe an energy-based analogue of the time- or alternative explanations about time, energy, and power based roofline model. We create this model from the perspective relationships. of algorithm designers and performance tuners, with the intent not of making exact predictions, but rather, developing high- First, when analyzing time, the usual first-order analytic level analytic insights into the possible relationships among tool is to assess the balance of the processing system [7]– the time, energy, and power costs of an algorithm. The model [12]. Recall that balance is the ratio of work the system expresses algorithms in terms of operations, concurrency, and can perform per unit of data transfer. To this notion of memory traffic; and characterizes the machine based on a time-balance, we define an energy-balance analogue, which small number of simple cost parameters, namely, the time and energy costs per operation or per word of communication. We measures the ratio of flops and bytes per unit-energy (e.g., confirm the basic form of the model experimentally. From this Joules). We compare balancing computations in time against model, we suggest under what conditions we ought to expect balancing in energy. [xII] an algorithmic time-energy trade-off, and show how algorithm Secondly, we use energy-balance to develop an energy- properties may help inform power management. based analogue of the time-based roofline model [12]. Keywords-performance analysis; power and energy model- Because time can be overlapped while energy cannot, the ing; computational intensity; machine balance; roofline model energy-based “roofline” is actually a smooth “arch line” (see fig. 2a). Interestingly, if time-balance differs from energy- balance, then there are distinct notions of being “compute- I. INTRODUCTION bound” versus “memory-bound,” depending on whether the optimization goal is to minimize time or to minimize energy. The overarching goal of this paper is to develop a simple We can measure this difference as a time-energy balance explanation, aimed at algorithm designers and performance gap. We also posit an analogous “powerline” model for tuners, about the relationships among time, energy, and power. [xII, xIII] power. For that audience, a useful model would directly connect properties of an algorithm—such as concurrency Thirdly, when a balance gap exists and energy-balance ex- and locality—with architectural time and energy costs. It ceeds time-balance, the arch line predicts that optimizing for would explain whether there is any difference in optimizing energy may be fundamentally more difficult than optimizing an algorithm for time versus optimizing for energy, why for time. It further suggests that high algorithmic energy- such differences exist, and what properties of the architec- efficiency may imply time-efficiency, while the converse— ture might lead to non-trivial time-energy trade-offs. We that time-efficiency implies energy-efficiency—is not true. have studied similar kinds of models in some of our prior [xII, xIV] work [1]–[3], but thus far have not considered energy in a Fourthly, we test the basic form of the model using formal way. experiments on real CPU and GPU platforms. Using our Our analysis is inspired by a similar set of thought model and these data, we show that the hypothetical balance experiments based on “Amdahl” analysis, written by and gap above does not yet really exist, which consequently for architects [4]–[6]. (We review this work and numerous explains why on today’s platforms race-to-halt is likely other related studies in xVI.) Such analyses offer archi- to work well. This raises the question for architects and tectural insights, but abstract away essential properties of hardware designers about what the fundamental trends in an algorithm. By contrast, our analysis more explicitly the balance gap will be: if energy-balance will exceed time- connects algorithmic and architectural parameters. However, balance in the future, race-to-halt will break. We further for clarity we pose and study an intentionally simple—but use the experiments to highlight both the strengths and the not overly so—model, with some initial experimental tests limitations of our model and analysis. [xIV, xV, xVII] to confirm its basic form. Taken together, we believe these analyses can improve our Below, we summarize what our model implies. These collective understanding of the relationship among algorithm claims both reflect familiar intuition and also yield new properties and their costs in time, energy, and power. 1 Preprint – To appear in the IEEE Int’l. Parallel & Distributed Processing Symp. (IPDPS), May 2013 size n;1 in addition, Q will depend on the size of the fast memory. We discuss these dependences momentarily. Slow memory For performance analysis and tuning, we may measure the algorithm’s computational intensity, which is defined as I ≡ W=Q. Intensity has units of operations per unit storage, such as flops per word or flops per byte. Generally speaking, a higher value of I implies a more “scalable” algorithm. That Q transfers is, it will have more work than mops; therefore, it is more likely to improve as the architecture’s compute throughput increases, which happens as cores increase or SIMD lanes Fast memory widen. (total size = ) Z Variable Description W # of arithmetic operations, e.g., # of flops xPU Q # of main memory operations (“mops”) I Intensity, or W=Q (e.g., flops per byte) τflop Time per work (arithmetic) operation, e.g., time per flop operations τmem Time per mop W Bτ Balance in time, τmem/τflop (e.g., flops per byte) flop Energy per arithmetic operation Figure 1: A simple von Neumann architecture with a two- mem Energy per mop level memory hierarchy. In our first analysis, suppose that an B Balance in energy, mem/flop (e.g., flops per Joule) Constant energy per flop algorithm performs W arithmetic operations and Q memory 0 flop + 0 Minimum energy to execute one flop flop operations, or “mops,” between slow and fast memories. ηflop Constant-flop energy efficiency, flop+0 π0 Constant power, e.g., Joule per second = Watts flop πflop Baseline power per flop excluding constant power, τflop ^ II. A BASIC MODEL AND ITS INTERPRETATION B (I) Effective energy-balance (π0 ≥ 0) Tflops Total time to perform arithmetic Assume the simple architecture shown in fig. 1. This ar- Tmem Total time to perform mops chitecture has a processing element, labeled “xPU”, as well T Total time as two levels of memory, namely, an infinite slow memory Eflops Total energy of arithmetic Emem Total energy of mops and a fast memory of finite capacity. This system roughly E0 Total “constant” energy captures everything from a single functional unit (xPU) E Total energy attached to registers (fast memory), to a manycore processor P Average power (xPU) attached to a large shared cache (fast memory). Z Fast memory size (e.g., words, bytes) Further assume that the xPU may only perform operations Table I: Summary of model parameters on data present in the fast memory. As such, an algorithm for this architecture must explicitly move data between slow and fast memories. What should we expect about the value of I? Recall that Q depends on fast memory capacity, which we denote by A. Algorithm characterization Z units of storage (words or bytes), as shown in fig. 1. Therefore, intensity will also depend on Z . A well-known W Let be the total number of “useful” operations that the result among algorithm designers is that no algorithm for Q algorithm performs and let be the total number of words it n × n matrix multiply can have an intensity exceeding I = transfers. (Table I summarizes all of the parameters of our p O Z [13]. Consequently, if we improve an architecture model.) By useful, we mean in an algorithmic sense; for example, we might only count flops when analyzing matrix by doubling Z , we will improve the inherent algorithmic multiply, or comparisons for sorting, or edges traversed for pintensity of a matrix multiply algorithm by no more than a graph traversal algorithm. For simplicity, we will assume 2. Contrast this scenario to that of just summing all of the W is measured in units of flops. We will also refer to W as elements of an array. Intuitively, we expect this computation the total work of the algorithm. Regarding Q, we will for to be memory bandwidth-bound if the array is very large. simplicity not distinguish between loads and stores, though Indeed, it has an intensity of I = O(1), that is, a constant one could do so in principle. We will refer to Q as “mops” independent of problem size or Z . Thus, increasing Z has measured in some convenient storage unit, such as a word no effect on the intensity of this kind of reduction. In short, or a byte. 1That is, imagine a W (n) = O(n) style of analysis. However, unlike In a typical algorithm analysis, both W and Q will of the traditional forms of such analysis, we will also want to characterize course depend on characteristics of the input, such as its constants and costs much more precisely whenever possible. 2 Preprint – To appear in the IEEE Int’l. Parallel & Distributed Processing Symp. (IPDPS), May 2013 Table II: Sample values for model parameters, values. (See table II for sample parameters.) This assumption based on best case (peak) capabilities of currently will tend to give a best-case analysis,2 which is only valid available systems.
Load more

Recommended publications
  • Cache-Aware Roofline Model: Upgrading the Loft
    1 Cache-aware Roofline model: Upgrading the loft Aleksandar Ilic, Frederico Pratas, and Leonel Sousa INESC-ID/IST, Technical University of Lisbon, Portugal ilic,fcpp,las @inesc-id.pt f g Abstract—The Roofline model graphically represents the attainable upper bound performance of a computer architecture. This paper analyzes the original Roofline model and proposes a novel approach to provide a more insightful performance modeling of modern architectures by introducing cache-awareness, thus significantly improving the guidelines for application optimization. The proposed model was experimentally verified for different architectures by taking advantage of built-in hardware counters with a curve fitness above 90%. Index Terms—Multicore computer architectures, Performance modeling, Application optimization F 1 INTRODUCTION in Tab. 1. The horizontal part of the Roofline model cor- Driven by the increasing complexity of modern applica- responds to the compute bound region where the Fp can tions, microprocessors provide a huge diversity of compu- be achieved. The slanted part of the model represents the tational characteristics and capabilities. While this diversity memory bound region where the performance is limited is important to fulfill the existing computational needs, it by BD. The ridge point, where the two lines meet, marks imposes challenges to fully exploit architectures’ potential. the minimum I required to achieve Fp. In general, the A model that provides insights into the system performance original Roofline modeling concept [10] ties the Fp and the capabilities is a valuable tool to assist in the development theoretical bandwidth of a single memory level, with the I and optimization of applications and future architectures.
    [Show full text]
  • CS 575: the Roofline Model
    CS 575: The Roofline Model Wim Bohm Colorado State University Spring 2013 Roofline: An Insightful Visual Performance Model.. David Patterson.. U.C. Berkeley submitted to CAM April 2008 Analyzing Program Performance n In empirical Computer Science, we plot functions describing the run time (or the memory use) of a program: ¨ This can be as a function of the input size. We have seen this in e.g. cs320 or cs420, where we studied polynomial and exponential (monotonically growing) complexity. ¨ In this class we also study program performance as a function of the number of processors. n In this case the functions are positive and, hopefully decreasing. n Also we plot speedup curves, which are usually asymptotic ¨ The roofline model plots GFlops/second as a function of Operational Intensity (GFlops/byte) Straight Lines CS475: When plotting data we get the most information from straight lines! ¨ We can easily recognize a straight line (y = ax+b) n The slope (a) and y intercept (b) tells us all. ¨ So we need to turn our data sets into straight lines. ¨ This is easiest done using log-s, because they turn a multiplicative factor into a shift up (y intercept) , and an exponential into a multiplicative factor (slope) Exponential functions log(2n) = n log2 linear in n log(3n) = n log 3 slope is base of log log(4.3n) = n log3 + log4 * shifts it up log((3n)/4) = n log3 – log4 / shifts it down Exponentials: semi-log plot n 2n 3n 20*3n 10000000" 0 1 1 20 1000000" 1 2 3 60 2 4 9 180 100000" 3 8 27 540 10000" 4 16 81 1620 2^n" 3^n" 5 32 243 4860 1000" 20"3^n" 7 128 2087 41740 10 1024 56349 1126980 100" 10" semi-log plot: y–axis on log scale 1" x-axis linear 0" 2" 4" 6" 8" 10" 12" angle: base shift: multiplicative factor Polynomials n What if we take the log of a polynomial? e.g.
    [Show full text]
  • Beyond the Roofline: Cache-Aware Power and Energy-Efficiency
    This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/TC.2016.2582151 TRANSACTIONS ON COMPUTERS, VOL. X, NO. X, MAY 2016 1 Beyond the Roofline: Cache-aware Power and Energy-Efficiency Modeling for Multi-cores Aleksandar Ilic, Member, IEEE, Frederico Pratas, Member, IEEE, and Leonel Sousa, Senior Member, IEEE Abstract—To foster the energy-efficiency in current and future multi-core processors, the benefits and trade-offs of a large set of optimization solutions must be evaluated. For this purpose, it is often crucial to consider how key micro-architecture aspects, such as accessing different memory levels and functional units, affect the attainable power and energy consumption. To ease this process, we propose a set of insightful cache-aware models to characterize the upper-bounds for power, energy and energy-efficiency of modern multi-cores in three different domains of the processor chip: cores, uncore and package. The practical importance of the proposed models is illustrated when optimizing matrix multiplication and deriving a set of power envelopes and energy-efficiency ranges of the micro-architecture for different operating frequencies. The proposed models are experimentally validated on a computing platform with a quad-core Intel 3770K processor by using hardware counters, on-chip power monitoring facilities and assembly micro-benchmarks. Index Terms—Multicore architectures, Modeling and simulation, Performance evaluation and measurement. F 1 INTRODUCTION N the road to pursuing highly energy-efficient execu- The key contribution of this paper is a set of insight- O tion, current and future trends in computer architec- ful cache-aware models to characterize the upper-bounds ture move towards complex and heterogeneous designs by for power, energy and energy-efficiency of modern multi- incorporating specialized functional units and cores [1].
    [Show full text]
  • How to Write Fast Numerical Code Fall 2016 Lecture: Roofline Model
    How to Write Fast Numerical Code Fall 2016 Lecture: Roofline model Instructor: Torsten Hoefler & Markus Püschel TA: Salvatore Di Girolamo Roofline model (Williams et al. 2008) Roofline model Resources in a processor that bound performance: Example: one core with π = 2 and β = 1 and no SSE • peak performance [flops/cycle] ops are double precision flops • memory bandwidth [bytes/cycle] • <others> performance [ops/cycle] Platform model bound based on β mem 4 bound based on π Bandwidth β carefully measured π = 2 [bytes/cycle] • raw bandwidth from manual is β: 1 unattainable (maybe 60% is) cache x • Stream benchmark may be 1/2 mem. compute bound conservative 1/4 bound P1 Pp 1/4 1/2 1 2 4 8 operational Peak performance π [ops/cycle] intensity some function [ops/bytes] run on some input Algorithm model (n is the input size) Operational intensity I(n) = W(n)/Q(n) = Bound based on β? - assume program as operational intensity of x ops/byte number of flops (cost) [ops/bytes] - it can get only β bytes/cycle number of bytes transferred - hence: performance = y ≤ βx between memory and cache - in log scale: log2(y) ≤ log2(β) + log2(x) - line with slope 1; y = β for x = 1 Q(n): assumes empty cache; Variations best measured with performance counters - vector instructions: peak bound goes up (e.g., 4 times for AVX) - multiple cores: peak bound goes up (p times for p cores) Notes - program has uneven mix adds/mults: peak bound comes down In general, Q and hence W/Q depend on the cache size m [bytes].
    [Show full text]
  • Roofline-Based Data Migration Methodology for Hybrid Memories 849
    Roofline-based Data Migration Methodology for Hybrid Memories 849 Roofline-based Data Migration Methodology for Hybrid Memories Jongmin Lee1, Kwangho Lee1, Mucheol Kim2, Geunchul Park3, Chan Yeol Park3 1 Department of Computer Engineering, Won-Kwang University, Korea 2 School of Software, Chung-Ang University, Korea 3 National Institute of Supercomputing and Networking, Korea Institute of Science and Technology Information, Korea [email protected], [email protected], [email protected], [email protected], [email protected]* Abstract be the future memory systems in high-performance computing (HPC) systems [4-7]. High-performance computing (HPC) systems provide Knights Landing (KNL) is the code name for the huge computational resources and large memories. The second-generation Intel Xeon Phi product family [1, 8]. hybrid memory is a promising memory technology that The KNL processor contains tens of cores and it contains different types of memory devices, which have provides the HBM 3D-stacked memory as a Multi- different characteristics regarding access time, retention Channel DRAM (MCDRAM). DRAM and MCDRAM time, and capacity. However, the increasing performance differ significantly in terms of access time, bandwidth and employing hybrid memories induce more complexity and capacity. Because of those differences between as well. In this paper, we propose a roofline-based data DRAM and MCDRAM, performance will vary migration methodology called HyDM to effectively use depending on the application characteristics and the hybrid memories targeting at Intel Knight Landing (KNL) usage of memory resources. The efficient use of these processor. HyDM monitors status of applications running systems requires prior application knowledge to on a system and migrates pages of selected applications determine which data of applications to place in which to the High Bandwidth Memory (HBM).
    [Show full text]
  • Roofline Model Toolkit: a Practical Tool for Architectural and Program
    Roofline Model Toolkit: A Practical Tool for Architectural and Program Analysis Yu Jung Lo, Samuel Williams, Brian Van Straalen, Terry J. Ligocki, Matthew J. Cordery, Nicholas J. Wright, Mary W. Hall, and Leonid Oliker University of Utah, Lawerence Berkeley National Laboratory {yujunglo,mhall}@cs.utah.edu {swwilliams,bvstraalen,tjligocki,mjcordery,njwright,loliker}@lbl.gov Abstract. We present preliminary results of the Roofline Toolkit for multicore, manycore, and accelerated architectures. This paper focuses on the processor architecture characterization engine, a collection of portable instrumented micro benchmarks implemented with Message Passing Interface (MPI), and OpenMP used to express thread-level paral- lelism. These benchmarks are specialized to quantify the behavior of dif- ferent architectural features. Compared to previous work on performance characterization, these microbenchmarks focus on capturing the perfor- mance of each level of the memory hierarchy, along with thread-level parallelism, instruction-level parallelism and explicit SIMD parallelism, measured in the context of the compilers and run-time environments. We also measure sustained PCIe throughput with four GPU memory managed mechanisms. By combining results from the architecture char- acterization with the Roofline model based solely on architectural spec- ifications, this work offers insights for performance prediction of current and future architectures and their software systems. To that end, we in- strument three applications and plot their resultant performance on the corresponding Roofline model when run on a Blue Gene/Q architecture. Keywords: Roofline, Memory Bandwidth, CUDA Unified Memory 1 Introduction The growing complexity of high-performance computing architectures makes it difficult for users to achieve sustained application performance across different architectures.
    [Show full text]
  • FPGA-Roofline: an Insightful Model for FPGA-Based Hardware
    FPGA-Roofline: An Insightful Model for FPGA-based Hardware Accelerators in Modern Embedded Systems Moein Pahlavan Yali Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Computer Engineering Patrick R. Schaumont, Chair Thomas L. Martin Chao Wang December 10, 2014 Blacksburg, Virginia Keywords: Embedded Systems, FPGA, Hardware Accelerator, Performance Model FPGA-Roofline: An Insightful Model for FPGA-based Hardware Accelerators in Modern Embedded Systems Moein Pahlavan Yali (ABSTRACT) The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance of modern em- bedded processors, they are outpaced by computational demands of the growing number of modern applications. This trend has led to emergence of hardware accelerators in embed- ded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and estimate the integration overhead and consequently the hardware acceleration benefit before committing to implementation. In this work, we present FPGA-Roofline, a visual model that offers insights to designers and developers to have realistic expectations of their system and that enables them to do their design and analysis in a faster and more efficient fashion. FPGA-Roofline allows simultaneous analysis of communication and computation resources in FPGA-based hardware accelerators. To demonstrate the effectiveness of our model, we have implemented hardware accelerators in FPGA and used our model to analyze and optimize the overall system performance.
    [Show full text]
  • Gables: a Roofline Model for Mobile Socs
    2019 IEEE International Symposium on High Performance Computer Architecture (HPCA) Gables: A Roofline Model for Mobile SoCs Mark D. Hill∗ Vijay Janapa Reddi∗ Computer Sciences Department School Of Engineering And Applied Sciences University of Wisconsin—Madison Harvard University [email protected] [email protected] Abstract—Over a billion mobile consumer system-on-chip systems with multiple cores, GPUs, and many accelerators— (SoC) chipsets ship each year. Of these, the mobile consumer often called intellectual property (IP) blocks, driven by the market undoubtedly involving smartphones has a significant need for performance. These cores and IPs interact via rich market share. Most modern smartphones comprise of advanced interconnection networks, caches, coherence, 64-bit address SoC architectures that are made up of multiple cores, GPS, and many different programmable and fixed-function accelerators spaces, virtual memory, and virtualization. Therefore, con- connected via a complex hierarchy of interconnects with the goal sumer SoCs deserve the architecture community’s attention. of running a dozen or more critical software usecases under strict Consumer SoCs have long thrived on tight integration and power, thermal and energy constraints. The steadily growing extreme heterogeneity, driven by the need for high perfor- complexity of a modern SoC challenges hardware computer mance in severely constrained battery and thermal power architects on how best to do early stage ideation. Late SoC design typically relies on detailed full-system simulation once envelopes, and all-day battery life. A typical mobile SoC in- the hardware is specified and accelerator software is written cludes a camera image signal processor (ISP) for high-frame- or ported.
    [Show full text]
  • Page 1 the Roofline Model Electrical Engineering and Computer
    Auto-tuning and the Roofline Model EECS Sam Williams, David Patterson, Kathy Yelick, Jim Demmel, Electrical Engineering and Andrew Waterman, Rich Vuduc, Lenny Oliker, John Shalf, Jonathan Carter, … BERKELEY PAR LAB Computer Sciences [email protected] P A R A L L E L C O M P U T I N G L A B O R A T O R Y Where does this fit in the ParLab ? The Roofline Model Auto-tuning the Structured Grid Motif Auto-tuning the Sparse Linear Algebra Motif ParLab Reference Reference Reference •Multi- and manycore is the only foreseeable solution to improve Samuel Williams, Andrew Waterman, David Patterson, “Roofline: An Insightful Multicore Performance Model”, Samuel Williams, Jonathan Carter, Leonid Oliker, John Shalf, Katherine Yelick, "Lattice Boltzmann Simulation Samuel Williams, Leonid Oliker, Richard Vuduc, John Shalf, Katherine Yelick, James Demmel, (submitted to) Communications of the ACM, 2008 Optimization on Leading Multicore Platforms", International Parallel & Distributed Processing Symposium "Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms", performance or reduce power. (IPDPS) (to appear), 2008. Supercomputing (SC), 2007. •Vertically and horizontally integrated lab focused on manycore. Best Paper, Application Track •Within each layer are multiple research groups. Introduction •Within each group are multiple projects. •Use bound and bottleneck analysis to distill the key components of Lattice-Boltzmann Magneto-hydrodynamics (LBMHD) What’s a Sparse Matrix? •Two groups (analysis and verification) dive
    [Show full text]
  • The Roofline Model
    FUTURE TECHNOLOGIES GROUP The Roofline Model Samuel Williams Lawrence Berkeley National Laboratory [email protected] 1 Outline FUTURE TECHNOLOGIES GROUP Introduction The Roofline Model Example: high-order finite difference stencils New issues at exascale 2 Challenges / Goals FUTURE TECHNOLOGIES GROUP At petascale, there are a wide variety of architectures (superscalar CPUs, embedded CPUs, GPUs/accelerators, etc…). The comput ati onal ch aract eri sti cs of numeri cal meth o ds can vary dramatically. The result is that performance and the benefit of optimization can vary significantly from one architecture x kernel combination to the next. We wish to qqyqypuickly quantify performance bounds for a variet y of architectural x implementation x algorithm combinations. Moreover, we wish to identify performance bottlenecks and enumerate potential remediation strategies. 3 Arithmetic Intensity FUTURE TECHNOLOGIES GROUP O( log(N) ) O( 1 ) O( N ) SpMV, BLAS1,2 FFTs Dense Linear Algebra Stencils (PDEs) (BLAS3) PIC codes Naïve Particle Methods Lattice Methods True Arithmetic Intensity (AI) ~ Total Flops / Total DRAM Bytes Some HPC kernels have an arithmetic intensity that scales with problem size (temporal locality increases with problem size) while others have constant arithmetic intensity. Arithmetic intensity is ultimately limited by compulsory traffic Arithmetic intensity is diminished by conflict or capacity misses 4 Arithmetic Intensity FUTURE TECHNOLOGIES GROUP O( log(N) ) O( 1 ) O( N ) SpMV, BLAS1,2 FFTs Dense Linear Algebra Stencils (PDEs) (BLAS3) PIC codes Naïve Particle Methods Lattice Methods Note, we are free to define arithmetic intensity in different terms: e.g. DRAM bytes -> cache, PCIe, or network bytes. flop’ s -> stencil’ s Thus, we might consider performance (MStencil/s) as a function of arithmetic intensity (stencils per byte of ____) 5 FUTURE TECHNOLOGIES GROUP Roofline Model 6 Overlap of Communication FUTURE TECHNOLOGIES GROUP Consider a simple example in which a FP kernel maintains a working set in DRAM.
    [Show full text]
  • The Roofline Model
    “Simple” performance modeling: The Roofline Model Loop-based performance modeling: Execution vs. data transfer A simple performance model for loops Simplistic view of the hardware: Simplistic view of the software: Execution units max. performance ! may be multiple levels do i = 1,<sufficient> 푷풑풆풂풌 <complicated stuff doing N flops causing Data path, V bytes of data transfer> bandwidth 풃푺 enddo → Unit: byte/s 푵 Computational intensity 푰 = 푽 Data source/sink → Unit: flop/byte Roofline Model (c) NHR@FAU 2021 2 Naïve Roofline Model How fast can tasks be processed? 푷 [flop/s] The bottleneck is either ▪ The execution of work: 푃peak [flop/s] ▪ The data path: 퐼 ∙ 푏푆 [flop/byte x byte/s] 푃 = min(푃peak, 퐼 ∙ 푏푆) This is the “Naïve Roofline Model” P ▪ High intensity: P limited by execution peak Performance ▪ Low intensity: P limited by data transfer ▪ “Knee” at 푃푚푎푥 = 퐼 ∙ 푏푆: Best use of resources ▪ Roofline is an “optimistic” model (“light speed”) Intensity Roofline Model (c) NHR@FAU 2021 3 The Roofline Model in computing – Basics Apply the naive Roofline model in practice 퐹 ▪ Machine parameter #1: Peak performance: 푃 푝푒푎푘 푠 퐵 ▪ Machine parameter #2: Memory bandwidth: 푏 푆 푠 퐹 ▪ Code characteristic: Computational intensity: 퐼 퐵 Machine properties: GF 푃 = 2.5 GF/s 푷 = 4 double s=0, a[]; 풑풆풂풌 s for(i=0; i<N; ++i) { s = s + a[i] * a[i];} GB 풃 = 10 푺 s 2 퐹 퐼 = = 0.25 퐹Τ 8 퐵 퐵 Application property: I Roofline Model (c) NHR@FAU 2021 4 Prerequisites for the Roofline Model ▪ The roofline formalism is based on some (crucial) prerequisites: ▪ There is a clear concept of “work” vs.
    [Show full text]
  • The Boat Hull Model: Enabling Performance Prediction for Parallel Computing Prior to Code Development
    The Boat Hull Model: Enabling Performance Prediction for Parallel Computing Prior to Code Development Cedric Nugteren Henk Corporaal Eindhoven University of Technology, The Netherlands http://parse.ele.tue.nl/ {c.nugteren, h.corporaal}@tue.nl ABSTRACT 1. INTRODUCTION Multi-core and many-core were already major trends for the For the past five decades, single-processor performance past six years and are expected to continue for the next has shown an exponential growth, enabling technology to decade. With these trends of parallel computing, it becomes become pervasive and ubiquitous in our society. This ex- increasingly difficult to decide on which processor to run a ponential growth ended in 2004, limited by two aspects: 1) given application, mainly because the programming of these it became unfeasible to increase clock frequencies because processors has become increasingly challenging. of power dissipation problems, and 2), processor architec- In this work, we present a model to predict the perfor- ture improvements have seen a diminishing impact [9]. To mance of a given application on a multi-core or many-core re-enable performance growth, parallelism is exploited. En- processor. Since programming these processors can be chal- abled by Moore’s law, more processors per chip (i.e. multi- lenging and time consuming, our model does not require core) was already a major trend for the past six years and is source code to be available for the target processor. This expected to continue for the next decades [7]. While multi- is in contrast to existing performance prediction techniques core is expected to enable 100-core processors by 2020 [7], such as mathematical models and simulators, which require another trend (many-core) already yields more than 2000 code to be available and optimized for the target architec- cores per chip, enabled by using much simpler processing ture.
    [Show full text]