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Fsms and Turing Machines Designing Sequential Logic Sequential logic is used when the solution to some design problem involves a sequence of steps: How to open digital combination lock w/ 3 buttons (“start”, “0” and “1”): Step 1: press “start” button Step 2: press “0” button Information Step 3: press “1” button remembered between Step 4: press “1” button steps is called state. Step 5: press “0” button Might be just what step we’re on, or might include results from earlier steps we’ll need to complete a later step. 11/1/2017 Comp 411 - Fall 2017 1 Implementing a “State Machine” Current State “start” “1” “0” Next State unlock --- 1 --- --- start 0 000 This flavor of “truth-table” is start 000 0 0 1 digit1 0 001 called a start 000 0 1 0 error 0 101 “state-transition start 000 0 0 0 start 0 000 table” digit1 001 0 1 0 digit2 0 010 digit1 001 0 0 1 error 0 101 digit1 001 0 0 0 digit1 0 001 digit2 010 0 1 0 digit3 0 011 This is starting to look like a … PROGRAM digit3 011 0 0 1 unlock 0 100 … unlock 100 0 1 0 error 1 101 unlock 100 0 0 1 error 1 101 unlock 100 0 0 0 unlock 1 100 error 101 0 --- --- error 0 101 6 different states → encode using 3 bits 11/1/2017 Comp 411 - Fall 2017 2 Now, We Do It With Hardware! 6 inputs →26 locations each location supplies 4 bits “start” button “0” button unlock “1” button ROM 64x4 Current state Next state 3 3 Q D Trigger update periodically (“clock”) 11/1/2017 Comp 411 - Fall 2017 3 Abstraction du jour: A Finite State Machine m n Clocked FSM A Finite State Machine has: ● k States S1, S2, … Sk (one is the “initial” state) ● m inputs I1, I2, … Im ● n outputs O1, O2, … On ● Transition Rules, S’(Si,I1, I2, … Im) for each state and input combination ● Output Rules, O(Si) for each state 11/1/2017 Comp 411 - Fall 2017 4 Discrete State, Discrete Time While a ROM is shown here in the feedback path any form of combinational logic inputs outputs can be used to construct a state machine. ROM Two design choices: (1) outputs *only* depend on state (Moore) STATE NEXT (2) outputs depend on inputs + state (Mealy) s s s state bits → 2s possible states Clock STAT E NEXT Clock Clock Clock Clock Clock Period Period Period Period Period 1 2 3 4 5 11/1/2017 Comp 411 - Fall 2017 5 State Transition Diagrams S, A state transition diagram is an abstract “graph” S S S S representation of a “state S 0 D1 1 D2 1 D3 0 U transition table”, where each U=0 U=0 U=0 U=0 U=1 state is represented as a node and each transition is represented as a as an arc. 0 0 1 1 0,1 It represents the machine’s behavior not its implementation! E S U=0 Heavy circle means INITIAL state 0,1, NAME of state = no buttons XXX 0 pressed U=0 INPUT OUTPUT when or INPUTs in this state causing (Moore) transition 11/1/2017 Comp 411 - Fall 2017 6 Example State Diagrams 1 0 MOORE Machine: 0 S0 S1 S2 1 1 0 0 Outputs on States 1 0 1/1 0/0 0/1 MEALY Machine: S0 S1 S2 1/0 Outputs on Transitions 1/0 0/0 Arcs leaving a state must be: (1) mutually exclusive can only have one choice for any given input value (2) collectively exhaustive every state must specify what happens for each possible input combination. “Nothing happens” means arc back to itself. 11/1/2017 Comp 411 - Fall 2017 7 Next Time Counting state machines 11/1/2017 Comp 411 - Fall 2017 8 FSMs and Turing Machines ● Ways we know to compute ○ Truth-tables = combinational logic ○ State-transition tables = sequential logic ● Enumerating FSMs Church (1903-1995) ● An even more powerful model: Turing’s PhD Advisor a “Turing Machine” ● Alan Turing What does it mean to compute? (1912-1954) ● What can’t be computed ● Universal TMs = programmable TM Kleene (1909-1994) Post (1897-1954) 11/1/2017 Comp 411 - Fall 2017 9 Let’s play State Machine Let’s emulate the behavior specified by the state machine shown below when processing the following string from LSB to MSB. 1 0 0 S0 S1 S2 1 1 0 0 1 0 39 = 0100111 10 input order 2 State Input Next Output It looks to me like this machine outputs a 1 T=0 S0 1 S1 0 whenever the bit sequence T=1 S1 1 S0 1 that it has seen thus far T=2 S0 1 S1 0 is a multiple of 3. T=3 S1 0 S2 0 (Wow, and FSM can T=4 S2 0 S1 0 divide by 3!) T=5 S1 1 S0 1 T=6 S0 0 S0 1 11/1/2017 Comp 411 - Fall 2017 10 FSM Party Games 1. What can you say about ROM the number of states? k k k States ≤ 2 x y z FSM1 FSM2 2. Same question: m-states n-states States ≤ m × n 3. Here's an FSM. Can you discover its rules? 11/1/2017 Comp 411 - Fall 2017 11 What’s My Transition Diagram? 1 0=OFF, 1=ON? 0 1 vs. 0 1 1 1 1 0 1 0 1 0 0 0 "1-1-1-1" = Surprise! • If you know NOTHING about the FSM, you’re never sure! • If you have a BOUND on the number of states, you can discover its behavior: K-state FSM: Every (reachable) state can be reached in < 2i x k steps. BUT ... states may be equivalent! 11/1/2017 Comp 411 - Fall 2017 12 FSM Equivalence 1 1 1 1 1 0 1 vs 0 1 0 . 0 0 0 0 ARE THEY DIFFERENT? NOT in any practical sense! They are EXTERNALLY INDISTINGUISHABLE, hence interchangeable. FSMs are EQUIVALENT iff every input sequence yields identical output sequences. ENGINEERING GOAL: • HAVE an FSM which works... • WANT simplest (ergo cheapest) equivalent FSM. 11/1/2017 Comp 411 - Fall 2017 13 Housekeeping issues… 1. Initialization? Clear the memory? 2. Unused state encodings? inputs ROM outputs - wastes ROM (use gates) or - meaning? gates STATE NEXT 3. Synchronizing input changes with s s state update? That symbol is 4. Choosing encodings for each state? starting to register 11/1/2017 Comp 411 - Fall 2017 14 2-Types of Processing Elements Combinational Logic: i Addr o Data Table look-up, ROM Fundamentally, everything Recall that there are precisely that we’ve i 2 learned so far 2 , i-input combinational functions. can be done with a ROM A single ROM can store ‘o’ of them. and registers Finite State Machines: i o ROM with State Memory Addr s Data Thus far, we know of nothing more powerful than an FSM 11/1/2017 Comp 411 - Fall 2017 15 FSMs as Programmable Machines ROM-based FSM sketch: An FSM’s behavior is completely Given i, s, and o, we need a ROM determined by its ROM contents. organized as: input outputs s i+s 2 words x (o+s) bits i s sN+1 o N 0...00 0...00 10110 011 So how many possible 0...01 i-input, i i+s o-output, 2 FSMs with s-state bits s exist? The number of “bits” in the ROM All possible i+s settings of the (o+s)2 ROM’s contents 2 o to: 1 or 0 (some may be equivalent) How many state machines are there with Recall how we were able to “enumerate” 1-input, 1-output, and 1 state bit? or “name” every 2-input gate? 2(1+1)4 = 28 = 256 Can we do the same for FSMs? 11/1/2017 Comp 411 - Fall 2017 16 These are the FSMs with 1 input and 1 output and 1 state bit. FSM Enumeration They have 8-bits in their ROM. GOAL: List all possible FSMs in some canonical order. • INFINITE list, but 28 • Every FSM has an entry in FSMs and an associated index. 64 input outputs 2 s 18,446,744,073,709,551,872 i sN o sN+1 0...00 0...00 10110 011 3.9402 x 10115 0...01 Every possible FSM can be associated with a unique number. This requires a few wasteful simplifications. First, given an i-input, s-state-bit, and o-output FSM, we’ll replace it with its equivalent n-input, n-state-bit and n-output FSM, where n is the greatest of i, s, and o. We can always ignore the extra input-bits, and set the extra output bits to 0. This allows us to discuss the ith FSM 11/1/2017 Comp 411 - Fall 2017 17 Some FavoRites FSM837 modulo 3 state machine FSM1077 4-bit counter FSM1537 Combination lock FSM89143 Cheap digital watch FSM22698469884 MIPs processor FSM23892749274 ARM7 processor FSM78436378389 Intel I-7 processor (Skylake) FSM78436378390 Intel I-7 processor (Kaby lake) 11/1/2017 Comp 411 - Fall 2017 18 Can FSMs Compute Every Binary Function? Nope! There exist many simple problems that cannot be computed by FSMs. For instance: Checking for balanced parentheses A function is specified by a deterministic output (()(()())) - Okay relationship for any given series of inputs, starting (()())) - No good! from a known initial state. PROBLEM: Requires ARBITRARILY many states, depending on input. Must "COUNT" unmatched LEFT parens. But, an FSM can only keep track of a “bounded” number of events.
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