Software/Hardware Engineer

Software and Hardware Engineering Positions Toronto, ON Timing and Power Modelling

Altera must guarantee our chips run at the speed we say they do, within a power budget. You will join one of the teams that make this happen. You must be a strong software developer who can write robust, maintainable, high-performance C++ code that balances runtime and memory consumption.

Memory Interface Design and Verification

High-speed memory controllers are widely used and demand careful high performance design. Work on such standards as DDR2/3/4, LPDDR2/3, QDRII/II+/IV, RLDRAMII, and RLDRAMIII memory PHYs and controllers. OpenCL

In Altera’s High Level Design Group, we’re transforming the way the world designs for FPGAs: instead of requiring clunky hardware description languages like Verilog or VHDL, we’re enabling vanilla software languages (C/C++/OpenCL) to be compiled directly into high- performance FPGA designs. This increases tenfold the user-base and significantly reduces the time to develop for the massively parallel and power-efficient FPGA; we can now target machine learning, cloud analytics, high performance computing, embedded automotive applications – emerging and rapidly changing markets that were previously inaccessible.

We’re looking for talented Computer Engineers, Electrical Engineers, and Computer Scientists to round out our team, with expertise in one or more of the following areas:

 COMPILER OPTIMIZATION – our innovative compiler, built on LLVM, creates a custom compute architecture that is tailored to each and every input software program, with customized datapath, functional units, and a custom memory system. We are constantly adding and improving optimization passes in our compiler to enable higher levels of parallelism and performance.  PROGRAMMING LANGUAGES – as a contributing member of the Khronos Group, we’re helping to define the OpenCL language specification, and driving the development of these languages in our clang front-end.  HIGH-PERFORMANCE FPGA HARDWARE DESIGN – our compiler uses a library of high-performance building blocks written in RTL. We’re constantly squeezing performance out of our custom datapaths by finding new and novel ways to transform for highest performance in the lowest area. We’re also automatically generating complete systems integrating the latest in periphery technology including QPI and Hybrid Memory Cube.  SOFTWARE DEVELOPER ECOSYSTEMS – we’ll need to provide a familiar development environment to the legions of software engineers using our toolchain. We are building debuggers, profilers, performance analysis tools, libraries, and optimization advisors, with the added challenge of needing to support a custom compute architecture which changes with every compile. Placement & Routing Algorithm and Software Infrastructure Development

In this position, you will develop improved synthesis, placement and routing algorithms and enhance the software infrastructure of Altera’s Quartus II CAD system. Placement and routing is one of the most computationally difficult problems in Computer-Aided Design, and finding algorithms with better result quality and reduced CPU time is a very challenging problem. Altera’s Quartus II CAD system is a very large and full-featured software program, leading to many interesting software engineering questions. Successful candidates will have, or be completing a degree in Computer Engineering, Electrical Engineering, Computer Science or Engineering Science. Software-heavy roles need knowledge of C/C++ and strong software engineering skills. Hardware-heavy roles need strength in digital logic and some programming. Partial Reconfiguration Altera’s Partial Reconfiguration development team is looking for talented, customer focused and dynamic individuals to help build out Altera’s partial reconfiguration solution. Partial reconfiguration combines the innovative solutions of leading edge silicon devices and advanced software design flows to enable customers the ability to dynamically change functionality for a portion of their design at run-time. Partial reconfiguration is a critical component in a number of important applications such as server side acceleration, cryptography, communications, and more! As a member of the Partial Reconfiguration team you will work closely with a team of engineers across R&D to develop leading edge solutions to the fast pace and challenging technical problems associated with PR. This includes the creation of customer reference designs in RTL, the writing of code in C++ for PR features, influencing the CAD flow and floorplanning solutions for PR customers, and the scripting of flows in Tcl, Perl, and Python. Partial Reconfiguration team members are routinely involved in all aspects of development including prototyping, testing, usability, customer engagements, and productization. In developing solutions for PR, our engineers make a direct impact on customers and the adoption of Altera FPGA for new applications.

The successful candidate's minimum qualifications will include the following: • BS degree in CS / CE / EE or equivalent with a minimum of 2 years of experience • Experience with Partial Reconfiguration is a plus • RTL design such as Verilog, VHDL • Scripting in Tcl, Perl, and Python • Programming in C++ • Experience with using large scale design environment • Experience with FPGA • Attention to details and customer experience • Self motivated