EDA Sign-off Analysis champion Invarian extends its portfolio with new offering in 3D with its 3D Frontier line, including Thermal and Mechanical Stress for chip/package analysis
Santa Clara, CA, May 29, 2012 — Invarian Inc., a leading provider of electronic design automation (EDA) software is now adding 3D thermal and mechanical stress to its physical sign-off tools. In addition to the InVar Pioneer suite of sign-off analysis tools, 3D Frontier will be on display at the Design Automation Conference (DAC) in San Francisco, CA June 3 – 6, 2012 in the Invarian booth #317 and in the Si2 booth.
With the growing need due to stacked die, increasing performance demands within a static power envelope and the introduction of FinFET transistors to extend Moore's Law comes a growing problem of heat. Invarian helps to plan for and alleviate that problem with the introduction of new analysis tools. InVar 3D Frontier Thermal is designed for true 3D-analysis which is especially important in stacked die applications. Along with the increasing need for analyzing thermal issues is the need to adhere to proper mechanical stress issues. InVar Mechanical Stress works in conjunction with our thermal tools to ensure a total solution encompassing the chip, the package and the entire 3D-environment.
The InVar 3D Thermal tool works within standard flows using an adaptive engine able to capture a thermal profile within minutes of actual runtime. The thermal analysis tool is highly accurate because it integrates into an overall concurrent engine that analyzes not only the thermal aspects, but also the timing, power, and voltage on a continuous basis. The engine runs on a parallel architecture and scales with the computing environment.
Validation becomes increasingly important and problematic as processes scale below 28nm because they not only scale by reducing gate-channels but also with the introduction of 3D devices. When you add to this the additional thermal and mechanical stress from the arrangement of a tighter package density due to stacked die and their associated vias and interconnect we have entered a new realm where thermal and mechanical stress analysis early in the design flow become important.
Moore’s Law is predicated on packing twice as many transistors into a given area, with equivalent yield, every 18-24 months. To continue this trend requires integration techniques that Invarian’s 3D Thermal and Mechanical Stress can play an important part.
The tools employ debug features and what-if capabilities to find-and-fix errors quickly and efficiently. The ability to scale to very large designs without sacrificing accuracy or suffering long run-times is achieved through the architecture of the tool itself.
5255 Steven Creek Blvd, Suite 246 Santa Clara, California 95051 www.invarian.com Phone +1 (408) 834-5942 Fax +1 (408) 689-1032 Invarian’s tools are designed for engineers who require fast, accurate results from the gate-level through the 3D-package environment. Using proprietary algorithms to achieve results that correlate with physical reality is the best bet for first time silicon success.
About Invarian:
Invarian develops and markets software and Intellectual Property for Electronic Design Automation (EDA), enabling integrated circuit designers to meet critical time-to-market objectives by delivering physical sign-off solutions that reduces re- spins and helps to get products to market faster. The Invarian sign-off analysis for analog, digital and mixed signal integrated circuits identifies post-manufacturing failures before tape-out, reducing costly re-spins. It is the most comprehensive solution on the market, and the only solution in terms of speed and accuracy.
Press Contact: [email protected] http://www.invarian.com