Computing
of the Future
Computing of the Future
Energy-Efficient Large-Scale High-Performance Computing
Place: Crowne Plaza Hotel, San Francisco Airport Date: February 29, 2008 Time: 8:00 am- 8:00 pm
What will Computing be like in 20 years? What is the future beyond the end of the current roadmap for CMOS microprocessors? The phenomenal advances in computing technology over the past two decades were enabled by Dennard scaling, whereby the exponential improvements in power efficiency and performance and cost-effectiveness of silicon technology tracked Moore’s Law improvements in integrating more devices on each chip. As we approach atomic scale lithography, the end of Dennard scaling puts future growth of the computing industry in jeopardy. Multicore has provided a temporary respite from stagnation of CPU clock frequencies, but creates daunting challenges to programmability, and drives today’s system architectures towards extreme levels of unbalanced communication-to-computation ratios! This workshop will promote discussions on a comprehensive strategy that directly addresses the challenges of power-density, bandwidth limits, programmability, and interconnect technologies. One of the central goals of the workshop is to discuss methods to eliminate the growing system imbalance performance gap by creating a new computing platform where bandwidth is uniformly plentiful across the entire system and is not traded off the power budget. A system with such uniform system-wide bandwidth offers significantly simpler optimization strategies for software architects that address many of the programmability concerns for multicore chips and massively parallel computing platforms. Addressing the three key areas of energy consumption, bandwidth scaling, and programmability will enable continued exponential improvements in power-efficiency, performance, and cost-effectiveness that drive the computing industry for the next 20 years.
This workshop addresses key opportunities and challenges of Future Computing, in the architecture, nanotechnologies, interconnection, and systems areas.
Topics
Applications and Architectures of Future Computing Systems Nanotechnologies beyond CMOS (nanophotonics, nanoelectronics, nanomagnetics) Novel Interconnection The phenomenal advances in computing technology over the past two decades were enabled by Dennard scaling, whereby the exponential improvements in power efficiency, performance, and cost-effectiveness of silicon technology tracked Moore’s Law improvements in integrating more devices on each chip. As we approach atomic scale lithography, the end of Dennard scaling puts future growth of the computing industry in jeopardy. While multicore processors are providing a temporary respite from stagnation of CPU clock frequencies, they have created daunting challenges to programmability and have ultimately driven today’s system architectures towards extreme levels of unbalanced communication-to-computation ratios!
This workshop addresses key opportunities and challenges of Future Computing, in the architecture, nanotechnologies, interconnection, and systems areas.
Place: Crowne Plaza Hotel, San Francisco Airport Date: February 29, 2008 Time: 8:00 am- 8:00 pm
Organizing Institutions: Center for Information Technology in the Interest of Society (CITRIS) Columbia University Cornell University Lawrence Berkeley National Laboratory University of California, Berkeley University of California, Davis Stanford University
Cooperating Organizations: HP, Hitachi, IBM, Intel, Lawrence Berkeley National Laboratory, NEC, Samsung Theme
What will Computing be like in 20 years? What is the future beyond the end of the current roadmap for CMOS microprocessors? The phenomenal advances in computing technology over the past two decades were enabled by Dennard scaling, whereby the exponential improvements in power efficiency and performance and cost-effectiveness of silicon technology tracked Moore’s Law improvements in integrating more devices on each chip. As we approach atomic scale lithography, the end of Dennard scaling puts future growth of the computing industry in jeopardy. Multicore has provided a temporary respite from stagnation of CPU clock frequencies, but creates daunting challenges to programmability, and drives today’s system architectures towards extreme levels of unbalanced communication-to-computation ratios! This workshop will promote discussions on a comprehensive strategy that directly addresses the challenges of power-density, bandwidth limits, and programmability, using nanoscale photonic interconnect technologies. One of the central goals of the workshop is to discuss methods to eliminate the growing system imbalance performance gap by creating a new computing platform where bandwidth is uniformly plentiful across the entire system and is not traded off the power budget. A system with such uniform system-wide bandwidth offers significantly simpler optimization strategies for software architects that address many of the programmability concerns for multicore chips and massively parallel computing platforms. Addressing the three key areas of energy consumption, bandwidth scaling, and programmability will enable continued exponential improvements in power-efficiency, performance, and cost-effectiveness that drive the computing industry for the next 20 years.
Topics
Applications and Architectures of Future Computing Systems Nanotechnologies beyond CMOS (nanophotonics, nanoelectronics, nanomagnetics) Novel Interconnection
Format
The workshop will be for one entire day (including lunch and dinner) on February 29, 2008, featuring presentations by key contributors to the field in intermixed with working sessions to create a group consensus of promising future directions. The workshop will produce a report suitable for use by decision makers and technologists. Co-Chairs: S. J. Ben Yoo, Venkatesh Akella, (UC Davis), Keren Bergman (Cornell University), Horst Simon (Lawrence Berkeley National Laboratory), S. J. Ben Yoo (UC Davis) Agenda (Tentative)
February 29, Friday, 2008
Day: Friday, February 29 7:30 am Breakfast 8:15 am Registration 9:00 am Workshop Introduction, Overview, and Goals S. J. Ben Yoo, UC Davis 9:30 am Industry: Prospects for Computing Beyond CMOS Logic, Jerry Bautista, Intel 10:00 am Government: UNÍC: Intrachip Photonic Communications, Jag Shah, DARPA MTO 10:30 am Break 11:00 am Technology: Programming Techniques to Harness Exaflops, John Shalf, LBL 11:30 am Industry: Sprinting Toward the Practical Limits of ComputationComputing Architecture with Nanophotonic Interconnects, TBD Norm Jouppi, HP Labs 12:00 Noon Technology: Optical Interconnects , David A. B. Miller, Stanford 12:30 pm Lunch 1:30 pm Technology:Balanced Computing, V. Akella/ and Keren Bergman, (UCDavis/Columbia Univ.) 2:00 pm Industry: IntraChip Optical Networks for a Future Supercomputer-on-a-ChipSupercomputer on a Chip (ICON), Jeffrey Kash, IBM Research 2:30 pm Technology: Plasmonics: Bridging nanoelectronics and nanophotonics, Shanhui Fan, Stanford Univ. 3:002:45 pm Technology: Nanowires: Massively Parallel Interconnects, UC Davis 3:00 pm Results from the Zettaflops Workshop, Erik P. DeBenedictis, Sandia National Labs 3:30 20 pm Break 43:00 50 pm Discussions: Computing of the Future 5:30 pm Social 6:00 pm Dinner Banquet 7:00 pm Speaker: TBD Registration
Participation is by gracious invitation only. Contact [email protected] if you need an invitation. Additional invitations are subject to space availability. Register on line (registration website will open soon at: http://sierra.ece.ucdavis.edu/html/html/workshop.htm ):
Note: On-line registration closes February 26, 2008 at 11:59pm (PDT). Registration will still be available at the door. Accommodations Crowne Plaza Hotel http://www.sfocp.com/
1177 Airport Blvd Burlingame, CA 94010 Phone: 877-252-1558 / 800-411-7275
Sleeping Room Block: The organizers have reserved a block of rooms at $159 + tax per night ($140+tax with Government ID). These rooms have been guaranteed and non-local participants are requested to contact the organizers if they cannot use these arrangements. Please call 800-411-7275 and provide the Group Name: “Computing.”
Check-In/Check-Out: Crowne Plaza respectfully requests a 4:00 pm check-in and a 12 noon check-out. Conference Meals
Breakfast, lunch and dinner will be provided for registered conference attendees on February 29, 2008.
All meals will be served buffet-style in the dining rooms.
Morning and afternoon refreshment breaks will be provided and replenished continually throughout the day.
Driving Directions
From San Francisco International Airport: Take Highway 101 South to Broadway exit. Follow the Airport Boulevard signs and travel east across the overpass. Turn right on Old Bayshore Road and follow straight into the hotel driveway. approximately 1.5 miles
From San Jose Airport: Take Highway 101 North to the Broadway/Burlingame exit. Turn right and follow straight into the hotel driveway approximately 33 miles
From Oakland Airport: Take I-880 South to Highway 92 ( San Mateo Bridge) West to Highway 101 North. Stay on Highway 101 to the Broadway/Burlingame exit. Turn right and follow straight into the hotel driveway. approximately 30 miles Contact Us
For questions regarding the technical program, please contact: S. J. Ben Yoo, [email protected], UC Davis CITRIS Director &, General Conference Workshop Chair Phone: (530) 752-7063
For questions regarding conference logistics, please contact: Sonia Rivera, [email protected], UCDavis CITRIS Program Manager, Phone: (530) 752-7007