Fatima Jinnah Women University Department of Software Engineering BSE III (Section B) Fall 2012
LABORATORY MANUAL DIGITAL LOGIC DESIGN
Instructed By: Ms. Sidra Minhas
Assisted By: BSE Digital Logic Design
Mr. Majid Shafiq
FJWU, The Mall, Rawalpindi 2 BSE Digital Logic Design
Table of Contents
1 Introduction:...... 3 2 The Laboratory Notebook...... 4 3 Personal Tools and Components...... 5 4 Working Code...... 6 5 Basic Knowledge of Trainer 6 Experiment No. 1: Familiarization with logic trainer and verification of truth table of basic gates...... 7 7 Experiment No. 2: Working with universal Logic Gates...... 14 8 Experiment No. 3: Implementation of boolean expression through logic gates & also verification of Demorgan’s Law...... 21 9 Experiment No. 4: Implementation of a XOR and XNOR gates using NAND gates...... 24 10 Experiment No. 5: Implementation of combinational functions using various logic gates...... 29 11 Experiment No. 6: Implementation of half adder & full adder...... 34 12 Experiment No. 7: Design the BCD-to-seven-segment decoder circuit...... 39 13 Experiment No. 8: Introduction, implementation and working with multiplexers, decoders and encoders...... 43 14 Experiment No. 9: Implementation of full adder with 2, 2*4 decoders...... 50 15 Experiment No. 10: Implementation of full adder with 8*1 MUX...... 56 16 Experiment No. 11: Verification of the truth table of RS flip flop...... 60 17 Experiment No. 12: Verification of the truth table of JK flip flop...... 64 18 Experiment No. 13: Shift register operation (night rider) ring counter...... 68 19 Appendix A: Use good construction practices...... 70 20 Appendix B: Troubleshooting...... 71 21 Appendix C: Safety...... 72
FJWU, The Mall, Rawalpindi 3 BSE Digital Logic Design
1. Introduction:
The primary purpose of this laboratory is to improve your ability to design, build, characterize and troubleshoot electronic circuits. A secondary objective is to demonstrate principles that you have covered in other classes. A third objective is to improve your written and oral communication skills. A forth objective is to develop team skills by working on an engineering team to develop a prototype of a product. The skills you develop in this laboratory should make you a more valuable hardware engineer and improve your interviewing skills. Much of the emphasis will be on very practical ideas that are not covered in text books but are based on industrial experience. You will also consider marketing and economic issues, efficiency, reliability and product safety. You will design electronic circuits to meet certain electrical and economic specifications. As a team you learn about scheduling time and resources to finish objectives on time. Laboratory safety and ESD prevention will be stressed.
You will have opportunities to work alone and with a partner but much of your grade for the course will depend on the performance of your "engineering team". This team will consist of about 4 students. Teamwork, scheduling, organization and productivity will be important to realize the design objectives of the course.
It is important for you to share your problems and solutions with the class and your instructor. Your grade will depend on your end results. Recognizing problems and getting help to solve them if needed is very important. You often learn more by correcting a mistake or learning about another group's problems and solutions than you do when everything "plugs-and-plays". If something doesn't seem right or is confusing to you, be sure to figure it out and get help if needed. Mistakes in the laboratory are expected if you are working on something significant, and if you learn from them you'll make fewer and fewer errors as you gain experience.
The details of the laboratory procedures, reports, prelab work, and grading will be covered by your laboratory instructor during the laboratory sessions. As mentioned earlier frequent discussions of your ideas, progress and problems with your instructors will save time in the end and should result in a better design. You are expected to attend all lecture sessions and the beginning of each laboratory period for your section.
Students with good laboratory skills and experience are encouraged to work with weaker students; both will benefit. Preparations for experiments are important and will be checked.
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2. The Laboratory Notebook
Keeping good laboratory notebooks is important to the success of engineers in many positions. Such records are often used by companies for legal purposes. Good habits formed now will serve you well in your career. Your notebook should be bound and you should number and sign each page. The guidelines from Lab 1 will be useful but this lab is not as strict.
Each student is required to keep a detailed laboratory notebook of his or her individual work with each page signed, numbered, and dated. Your lab book should contain a record of preliminary design work, the results and comments of your lab work and summary comments and results in consecutive order. This is not a "formal" document but, neatness, organization and completeness is important. You should be able to go back to your notebook five years from now and reconstruct the important facts about your work. In fact, the evaluation of your notebook will be largely determine by how effectively it can be used by you or someone else to describe or reproduce important details about a completed experiment. In industry, lab notebooks are the legal property of the company. They are kept for many years and are very important for legal reasons such as patent applications and lawsuits. The success of your career (and the company) may depend on how well you keep your notebook. Don't erase or remove information. Just draw a line through mistakes or bad data; mistakes may be very useful later. Imagine that 15 years from now another engineer will examine your laboratory notebook to get information to use in a multimillion dollar patent suit. It happens. Your laboratory instructor will do this during the semester at least once.
The first few pages of your book should be reserved for a table of contents and a list of the projects you are working on with the present status noted. You may keep device pin outs and specifications sheets in the section where you use them. It is important to discuss your plans ahead of time to optimize your time in the laboratory. Preliminary or Prelab requirements should be presented to your laboratory before you start the laboratory work. If you have problems in the lab or get results that you don't understand you should first try to resolve the situation yourself and then ask for help. Circuit diagrams must follow the guidelines given in The Art of Electronics reference.
FJWU, The Mall, Rawalpindi 5 BSE Digital Logic Design
3. Personal Tools and Components
We suggest that every student have the following tools and equipment:
Tools Miniature flush cutters (electronic grade) Wire strippers (12-26 AWG) Small tool box (with engraved name) Small screwdriver set (regular and Phillips) Tweaker screwdriver for trimmer adjustments 3-in-1 wire wrap tool (hand tool which strips, wraps and unwraps) Small soldering iron (for personal projects!)
Miscellaneous
Breadboard (Proto, Elite, etc.) Dissecting Probe (for making test connections) Electronic grade cored solder Solder-wick (to remove solder from IC pins, etc.) Test Leads (Clip leads) Straight Edge (Long enough to rule a vertical line down a page of a notebook) Components
You may obtain components for this lab from any source. Lab II kits will NOT be sold by IEEE because selecting components for most of your designs is an important part of the project. Since the experiments vary from group to group you should plan ahead for your needs. Components can be checked out from the Electronics Shop near the laboratory for new designs and some components are available in the laboratory. If you plan ahead you can get many components as samples via the Internet. Design around available components but note in your report and notebooks how performance could be improved with different components.
FJWU, The Mall, Rawalpindi 6 BSE Digital Logic Design
4. Working Code
WORK AREAS WILL BE KEPT CLEAN AND NEAT. At the end of each laboratory period return all books, components and instruments that are not normally located at your bench to their proper locations. Clean off the working surface of the bench and put the litter into the waste can.
ABUSE OR MISUSE OF EQUIPMENT: Treat all equipment with respect and care. If you are not sure how to operate a piece of equipment then read the manual.
5. LABORATORY REFERENCE MATERIAL: There is a large variety of reference books, data books, and equipment manuals on the laboratory bookshelves. Please replace these on the shelves after you have finished with them.
6. BASIC KNOWLEDGE OF TRAINER
a. Toggle Switches: Used for input
b. LEDs: Used to display input/output states
c. Breadboard:
FJWU, The Mall, Rawalpindi 7 BSE Digital Logic Design
FJWU, The Mall, Rawalpindi 8 BSE Digital Logic Design
EXPERIMENT # 1
FAMILIARIZATION WITH LOGIC TRAINER AND VERIFICATION OF TRUTH TABLE OF BASIC LOGIC GATES.
1. Objectives: Having completed this experiment you will be able to: i. Understand the different options, facilities and provisions provided on the logic trainer. ii. Recognize the different logic gates. iii. Verify the truth table of basic logic gates: 1. AND 4081 2. OR 4071 3. NOT 4049 4. NAND 4011 5. NOR 4001 6. X-OR 4070 7. EX-NOR 4077
2. Basic Information: A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two binary conditions low/false (0) or high/true (1), represented by different voltage levels. The logic state of a terminal can, and generally does, change often, as the circuit processes data. In most logic gates, the low state is approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V).There are seven logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR. a. Logic Gates Symbols and Truth Tables: NOT gate (inverter)
The output Q is true when the input A is NOT true, the output is the inverse of the input: Q = NOT A. A NOT gate can only have one input. A NOT gate is also called an inverter.
A Q Input A Output Q A Q 0 1 1 0
Traditional symbol IEC symbol Truth Table
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AND gate
The output Q is true if input A AND input B are both true: Q = A AND B An AND gate can have two or more inputs, its output is true if all inputs are true.
Input A Input B Output Q A Q A Q 0 0 0 0 1 0 1 0 0 B B 1 1 1
Traditional symbol IEC symbol Truth Table NAND gate (NAND = Not AND)
This is an AND gate with the output inverted, as shown by the 'o' on the output. The output is true if input A AND input B are NOT both true: Q = NOT (A AND B). A NAND gate can have two or more inputs, its output is true if NOT all inputs are true.
A Q A Q Input A Input B Output Q 0 0 1 0 1 1 1 0 1 B B 1 1 0
Traditional symbol IEC symbol Truth Table OR gate The output Q is true if input A OR input B is true (or both of them are true): Q = A OR B. An OR gate can have two or more inputs, its output is true if at least one input is true.
A Q Input A Input B Output Q A Q 0 0 0 0 1 1 1 0 1 B B 1 1 1
Traditional symbol IEC symbol Truth Table
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NOR gate (NOR = Not OR)
This is an OR gate with the output inverted, as shown by the 'o' on the output. The output Q is true if NOT inputs A OR B are true: Q = NOT (A OR B). A NOR gate can have two or more inputs, its output is true if no inputs are true.
Input A Input B Output Q A Q A Q 0 0 1 0 1 0 1 0 0 1 1 0 B B
Traditional symbol IEC symbol Truth Table
EX-OR (EXclusive-OR) gate
The output Q is true if either input A is true OR input B is true, but not when both of them are true: Q = (A AND NOT B) OR (B AND NOT A).This is like an OR gate but excluding both inputs being true. The output is true if inputs A and B are DIFFERENT. EX-OR gates can only have 2 inputs.
Input A Input B Output Q A Q A Q 0 0 0 0 1 1 1 0 1 1 1 0 B B
Traditional symbol IEC symbol Truth Table
EX-NOR (EXclusive-NOR) gate
This is an EX-OR gate with the output inverted, as shown by the 'o' on the output. The output Q is true if inputs A and B are the SAME (both true or both false): Q = (A AND B) OR (NOT A AND NOT B). EX-NOR gates can only have 2 inputs.
FJWU, The Mall, Rawalpindi 11 BSE Digital Logic Design
A Q Input A Input B Output Q A Q 0 0 1 0 1 0 1 0 0 B 1 1 1 B
Traditional symbol IEC symbol Truth Table
Universal Gates:
The NAND and NOR gates can be said to be universal gates, since combinations of them can be used to accomplish any of the basic operations and can, thus produce an inverter, an OR gate or an AND gate. The non-inverting gates do not have this versatility since they can't produce an invert.
3. Experimental Work: a. Material Required: Logic Trainer Connecting Wires Components (IC’s) b. Procedure: Connect the logic Trainer to 220V Ac power supply. Turn the Trainer On and verify the voltage of power supply by using voltmeter. Install the IC chip under experiment on the trainer breadboard. Wire the circuit according to the diagram provided; supply the +5V and ground to pin number 14 and 7 respectively. Use logic switches to provide “0” and “1” for input of each gate one at a time as A and B. For the output indication use LED Lout. Verify the output according to the truth tables of each gate. Fill the truth table in at step 3.4 according to the results obtained. Write down your observation & comments at step 3.4 as per your concept developed during this experimental work.
FJWU, The Mall, Rawalpindi 12 BSE Digital Logic Design c. Experimental Results.
AND GATE (4081) OR GATE (4071)
Input A Input B Output Q 0 0 0 1 1 0 1 1
NAND GATE (4011) NOR GATE (4001) Input A Input B Output Q Input A Input B Output Q 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
FJWU, The Mall, Rawalpindi 13 BSE Digital Logic Design
X-OR GATE (4070) NOT GATE (4049) Input A Input B Output Q 0 0 Input A Output A’ 0 1 0 1 0 1 1 1
Observations and Comments: ______
IN CASE OF TROUBLE: Check the power supply. Check the Vcc and GND at pin number 14 and 7 of the IC under test. Check all the wire connections and remove the breaks. Check the IC under test using truth table.
FJWU, The Mall, Rawalpindi 14 BSE Digital Logic Design
INSTRUCTOR VERIFICATION SHEET
For each verification, be prepared to explain your answer and respond to other related questions that the lab Instructor or Theory Instructor might ask.
Name: Date of Lab:
Verified: Date/Time:
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EXPERIMENT # 2
WORKING WITH UNIVERSAL LOGIC GATES.
1. Objective: After completion of this experiment Students shall be able to understand the behavior of logic NAND & NOR as the universal gates by obtaining the result like basic AND, OR, NOT gates.
2. Basic Information of Universal Gates:
The NAND and the NOR gate can be said to be universal gates since combinations of them can be used to accomplish any of the basic operations and can thus produce an inverter, an OR gate or an AND gate. The non-inverting gates do not have this versatility since they can't produce an invert.
a. NAND Gate
A Q A Q Input A Input B Output Q 0 0 1 0 1 1 B B 1 0 1 1 1 0 Traditional symbol IEC symbol Truth Table
b. NOR Gate:
A Q A Q Input A Input B Output Q 0 0 1 0 1 0 B 1 0 0 B 1 1 0 Traditional symbol IEC symbol Truth Table
3. Experimental Work :
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This Experiment has two parts. Part-1: Working with NAND Gate Part-2: Working with NOR Gate
3.1. Material Required Logic Trainer Connecting wires Components: 4011, 4001
3.2. Procedure: Install the ICs on trainer’s breadboard. Wire the pins 14 &7 of IC’s to +5v and GND respectively. Wire the circuit according to the diagrams provided in step 4.1 & 4.3 for NAND and NOR gates. Mention the input as “A” “B” and output as A’, A+B, and AB with respective logic circuit. Write down the results of Boolean expression of the interconnected gates at step 4.2, 4.4 with respect to the basic logic gates in the table provided.
3.3. Working with NAND Gate
a. EXPERIMENTAL RESULT
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AND NOT OR Output Input A Output A’ Input Output Input A Input B Input A AB 0 B A+B 0 0 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1
3.4. Working with NOR GATE
a. EXPERIMENTAL RESULT
AND Truth Table NOT Truth Table OR Truth Table Input Input Output Input Input Output Input Output A’ A B A+B A B AB A 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 1 1 1
INSTRUCTOR VERIFICATION SHEET
FJWU, The Mall, Rawalpindi 18 BSE Digital Logic Design
For each verification, be prepared to explain your answer and respond to other related questions that the lab Instructor or Theory Instructor might ask.
Name: Date of Lab:
Verified: Date/Time:
FJWU, The Mall, Rawalpindi 19 BSE Digital Logic Design
EXPERIMENT # 3
IMPLEMENTATION OF BOOLEAN EXPRESSION THROUGH LOGIC GATES & ALSO VERIFICATION OF DEMORGAN’S LAW
1. Objectives Having completed this experiment you will be able to. Implement the Boolean Expression through Logic Gates Recognize the De Morgan’s LAW in the light of Logic Gate’s behavior.
2. Basic Information: Boolean algebra is an algebra that deals with binary variables and logic operations. A Boolean function described by an algebraic expression consists of binary variables, the constants 0 and 1, and the logic operations symbols. For a given value of the binary variables, the function can be equal to either 1 or 0.
3. Experimental Work: 3.1. Material Required: Logic Trainer Connecting Wires Power Supply Components: 4081, 4049, 4071
3.2. Procedure: Consider as an example for the following Boolean function:
F1 =x + y’z
The function F1 is equal to 1 if x is equal to 1 or if both y’ and z are equal to 1, F1 is equal to 0 otherwise. The complement operation dictates that when y’=1 then y=0. Therefore, we can say that F1=1 if x=1 or if y=0 and z=1. A Boolean function expresses the logical expression for all possible values of the variables.
A Boolean function can be represented in a truth table. A truth table is a lot of combinations of 1’s and 0’s assigned to the binary variables and a column that shows the value of the function for each binary combination. The number of rows in the truth table is 2n, where n is the number of variables in the function. The binary combinations for the truth table are obtained from binary numbers by counting from 0 through 2n-1. Following table shows the truth table for the function F1.
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3.3. Truth Table for F1
Input X Input Y Input Z Output F1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Gate implementation of F1=x+y’z
4. Verify Demorgan’s Theorem
Demorgan’s law can be stated in terms of logic terms, which is the 1st law states that, (x+y)’= x’y’ Theorem 1 And the second law state that (xy)’= x’+ y’ Theorem 2
4.1. Truth Table that verifies the above given Theorem 1,
Input X Input Y (x+y)’ X’Y’ 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0
a. Logic Diagram for 1st Demorgan’s Law:
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4.2. Truth Table that verifies the above given Theorem 2
Input X Input Y (xy)’ X’+Y’
b. Implement the logic diagram for the 2nd Demorgan’s Theorem:
5. IN CASE OF TROUBLE: Check the power supply. Check the Vcc and GND at pin number 14 and 7 of the IC under test. Check all the wire connections and remove the breaks. Check the IC under test using truth table.
FJWU, The Mall, Rawalpindi 22 BSE Digital Logic Design
INSTRUCTOR VERIFICATION SHEET
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
FJWU, The Mall, Rawalpindi 23 BSE Digital Logic Design
EXPERIMENT # 4
IMPLEMENTATION OF XOR AND XNOR GATES USING NAND GATES
1. Objectives: Having completed this experiment you will be able to: Implement XOR and XNOR gates using NAND gates
2. Basic Information:
Digital circuits are more frequently constructed with NAND and NOR gates than with AND and OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. The graphic symbols for NAND, XOR, and XNOR gates together with their algebraic functions are given below:
Figure 4.1: Logic gates
Truth Table for XOR gate: Input A Input B Output F 0 0 0 0 1 1 1 0 1 1 1 0
The NAND logic diagram for XOR is obtained from Boolean function in the following way:
1. The implementation of a XOR function with NAND gates requires that the function be simplified in the sum of products form. F = A’B + AB’ equation. 2.1 2. Draw a NAND gate for each product term of the function that has at least two literals. This constitutes a group of first level gates.
Figure 4.2: First level gates
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3. Draw a single NAND gate within the second level, with inputs coming from the outputs of first-level gates.
Figure 4.3: Second level gates
4. A two input NAND gate can be used as an inverter by applying logic 1 at one of the inputs.
Figure 4.4: NAND implementation of XOR gate
3. Experimental Work: 3.1. Material Required: Logic Trainer Connecting Wires Components(IC’s): 4011
3.2. Procedure: It is clear from the logic diagram that the NAND gate implementation of XOR gate requires five NAND gates. You will need two quad- 2 in NAND gate ICs to perform this experiment. Gets the required number of ICs containing NAND gates and other apparatus from the lab attendant. Plug in the ICs in the breadboard of the Logic Trainer. Connect 5Vdc power supply and ground on pins 14 and 7 respectively. For other pin configuration consult the data sheet (we have already used NAND gates in the first lab so it should not be a problem). Wire your circuit according to the logic diagram for XOR gate as given above. Once you have wired the circuit, check it with your instructor and, if approved, power up your circuit. The outputs should be connected to the LEDs on the Logic Trainer for monitoring purpose. Apply different input combinations at the input and note down the outputs and fill in the following truth table. This truth table should confirm to the one given in theory. Repeat the same procedure for NAND gate implementation of XNOR gate.
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4. EXPERIMENTAL RESULT Fill in the following truth table in the presence of the lab instructor.
4.1. Truth Table for XOR Gate: (Details above) Input A Input B Output F 0 0 0 1 1 0 1 1
4.2. Write Boolean function for XNOR gate:
F = ------
a. Draw NAND logic diagram for the XNOR gate:
b. Truth Table for XNOR Gate: Input A Input B Output F 0 0 0 1 1 0 1 1
FJWU, The Mall, Rawalpindi 26 BSE Digital Logic Design
INSTRUCTOR VERIFICATION SHEET
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
FJWU, The Mall, Rawalpindi 27 BSE Digital Logic Design
EXPERIMENT # 5
IMPLEMENTATION OF COMBINATIONAL FUNCTIONS USING VARIOUS LOGIC GATES
1. Objectives Having completed this experiment you will be able to Understand the technical problems in a more logical way. Recognize and implement the logic gates in combinational digital circuit design. Understand the relationship between logic circuit, Boolean function and the Truth table.
2. Introduction: a. Combinational Logic Circuit A combinational circuit consists of logic gates whose output at any time is determined directly from the present combination of inputs without regard to previous inputs. A combinational circuit performs a specific information-processing operation fully specified logically by a set of Boolean function.
b. Combinational Function. An expression that has only two values, TRUE (1) or FALSE(0), consisting of a logical variable or of logical variables connected by logical operators. Boolean expressions are used to implement digital circuits with efficiency. First of all we construct the truth table and from that we generate the Boolean expression and translate that expression into gates. In designing digital circuits, the designer often begins with a truth table describing what the circuit should do. The design task is largely to determine what type of circuit will perform the function described in the truth table. While some people seem to have a natural ability to look at a truth table and immediately envision the necessary logic gate or relay logic circuitry for the task, there are procedural techniques available for the rest of us. Here, Boolean algebra proves its utility in a most dramatic way.
Example:
To illustrate this procedural method, we should begin with a realistic design problem. Suppose we were given the task of designing a flame detection circuit for a toxic waste incinerator. The intense heat of the fire is intended to neutralize the toxicity of the waste introduced into the incinerator. Such combustion-based techniques are commonly used to neutralize medical waste, which may be infected with deadly viruses or bacteria. So long as a flame is maintained in the incinerator, it is safe to inject waste into it to be neutralized. If the flame were to be extinguished, however, it would be unsafe to continue to inject waste into the combustion chamber, as it would exit the exhaust un-neutralized, and pose a health threat to anyone in close proximity to the exhaust. What we need in this system is a sure way of detecting the presence of a flame, and permitting waste to be injected only if a flame is "proven" by the flame detection system.
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Several different flame-detection technologies exist: optical (detection of light), thermal (detection of high temperature), and electrical conduction (detection of ionized particles in the flame path), each one with its unique advantages and disadvantages. Suppose that due to the high degree of hazard involved with potentially passing un-neutralized waste out the exhaust of this incinerator, it is decided that the flame detection system be made redundant (multiple sensors), so that failure of a single sensor does not lead to an emission of toxins out the exhaust. Each sensor comes equipped with a normally-open contact (open if no flame, closed if flame detected) which we will use to activate the inputs of a logic system.
Suppose that one of the three sensors were to fail in such a way that it indicated no flame when there really was a good flame in the incinerator's combustion chamber. That single failure would shut off the waste valve unnecessarily, resulting in lost production time and wasted fuel (feeding a fire that wasn't being used to incinerate waste).
It would be nice to have a logic system that allowed for this kind of failure without shutting the system down unnecessarily, yet still provide sensor redundancy so as to maintain safety in the event that any single sensor failed "high" (showing flame at all times, whether or not there was one to detect). A strategy that would meet both needs would be a "two out of three" sensor logic, whereby the waste valve is opened if at least two out of the three sensors show good flame.
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3. Experimental Work:
In this experiment, you will Implement a combinational logic by applying the various inputs, according to the table given here under and find out the results with respect to the Boolean expression.
Input A Input B Input C Input Output F 0 0 0 ABC 0 0 1 ABC 0 1 0 ABC 0 1 1 ABC 1 0 0 ABC 1 0 1 ABC 1 1 0 ABC 1 1 1 ABC
3.1. Material Required
IC component: 4073, 4072, 4049 Connecting Wires Logic Trainer
3.2. Procedure
Connect the Logic trainer to 220 volts AC power supply. Install the ICs on trainer’s breadboard. Wire the circuit according to the diagram shown as here under. Use logic switches to provide inputs at A, B and C as per table provided in step 3. Connect the output of the circuit to the LED provided on the breadboard. Verify the truth table with respect to the inputs and outputs to satisfy the system design.
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3.3. Experimental results
FILL IN THE TABLE PROVIDED IN STEP 3 AS AN OUTPUT FOR YOUR COMBINATIONAL LOGIC CIRCUIT DESIGNED
4. In case of Trouble. Check the power supply. Check the Vcc and GND at pin number 14 and 7 of the IC under test. Check all the wire connections and remove the breaks. Check the IC under test using truth table. 5. Self-Task:
Another Combinational circuit has four input and one output the output is equal to 1 when
a) All the input is are equal to “1”. b) None of the inputs are equal to one. c) The odd number of inputs equal to one
Obtain the truth table. Find the simplified output function in SOP. Draw the logic diagram.
INSTRUCTOR VERIFICATION SHEET
FJWU, The Mall, Rawalpindi 31 BSE Digital Logic Design
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
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EXPERIMENT # 6
IMPLEMENTATION OF HALF ADDER & FULL ADDER
1. Objectives: Having completed this experiment you will be able to Understand the use of logic gates in arithmetic operations. Understand the addition of two binary digits using. Logic circuit as a half adder. Understand the performance of combinational circuit that performs the addition of three bits (two significant bits and a previous carry) called a full- adder.
2. Basic Information: 2.1. Half Adder:
Half Adder is combinational logic circuit that generates the sum of two binary numbers (each having 1 bit length). The logic circuit has two inputs and two outputs i.e. Sum & Carry abbreviated as SHA & CHA respectively. First of all, we shall construct Truth Table of Half Adder x y
SHA= x + y
(To LED)
CHA=x y
(To LED)
Now we write Boolean function from above Truth Table as
SHA =xy + xy CHA = xy 2.2. Full Adder:
Full Adder is combination logic circuit that performs the sum of 3 input binary numbers, (each having 1 bit length). Two of the binary input variables are x and y represent the two significant bits to be added the third input z, represents the carry from previous lower significant position. Outputs of Full Adder are Sum and Carry represented as SFA and CFA respectively.
FJWU, The Mall, Rawalpindi 33 BSE Digital Logic Design x y z
HA1 HA2
SFA = (x + y) + z To LED
CFA = (x + y) z + xy To LED
3. Experimental Work
3.1. Material Used: Connecting wires Logic Trainer Components: (fill in yourself)
3.2. Procedure: Wire the circuit according to the pins supply indicator i.e. +5v to pin number 7, 14 respectively. Interconnect the basic logic gates as per logic diagrams given for half adder and full-adder Implement the given Boolean expression by basic logic gates, verify and write the result in the truth table
3.3. Experimental Results
Truth Table
Inputs Output
SHA = xy+xy CHA = x y X Y Actual Observed Actual Observed 0 0 0 1 1 0 1 1
Truth Table
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i/p’s o/p’s
SFA CFA x y z Actual Observed Actual Observed 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Sum = xyz+xyz+xyz+xyz
Simplifying by using Boolean Postulates & theorems/k-map, we get Sum =(xy+xy) . z + (xy+xy).z
SFA = (x y ) z
Carry = xyz + xyz + xyz+xyz
Simplifying by using Boolean Postulates & theorems/k-map, we get Carry = (xy+xy) . z+xy
CFA = (x y) z + xy
4. In Case of Trouble: Check the power supply. Check the Vcc and GND at pin number 14 and 7 of the IC under test. Check all the wire connections and remove the breaks. Check the IC under test using truth table.
INSTRUCTOR VERIFICATION SHEET
FJWU, The Mall, Rawalpindi 35 BSE Digital Logic Design
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
FJWU, The Mall, Rawalpindi 36 BSE Digital Logic Design
EXPERIMENT # 7 DESIGN THE BCD-TO-SEVEN-SEGMENT DECODER CIRCUIT.
1. Objective: Having completed this experiment you will be able to Understand the basic concept of BCD to Seven segment decoder.
2. Basic Information For this laboratory, the combinational logic circuit is used to convert a four-bit binary coded decimal (BCD) value to the signals required for a seven-segment display. BCD-to-seven-segment decoder is a combinational circuit that accepts a decimal digit in BCD (binary-coded decimal) and generates the appropriate output for selection of segments in a display indicator used for displaying the digit. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding segment in the display as shown in figure:
a
f b g
e d c
Figure 6.1: 74ls47 decoder interfacing with Seven – Segment display You are likely familiar with the idea of a seven-segment indicator for representing decimal numbers. Each segment of a seven-segment display is a small light-emitting diode (LED) or liquid-crystal display (LCD), and a decimal number is indicated by lighting a particular combination of the LED's or LCD's elements is shown below: a a a a a
f b f b f b f b f b g g g g g
e e e e e d c d c d c d c d c a a a a a
f b f b f b f b f b g g g g g
e e e e e d c d c d c d c d c Figure: Indication of decimal number on Seven – Segment display
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Bindary-coded-decimal (BCD) is a common way of encoding decimal numbers with 4 binary bits as shown below: BCD Code Decimal Digit 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9
Fill in the truth table for seven segment device whose display elements are active low. That is, each element will be active when its corresponding input is '0'.
Truth Table: Inputs A B C D a b c d e f g 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Truth table for seven – segment display
Rest of bit combinations are used with don’t care condition.
3. Experimental Work 3.1. Material Used:
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Logic trainer Connecting wires Seven-Segment Display Components: 7447 Power supply
3.2. Procedure Wire the IC chip and connect the +5v (Vcc) and ground the pin number 16 and 8 respectively. The BCD (8421) code is listed in table given from this table you can determine the relation between each BCD bit and the decimal digits in order to analyze the logic. For instance, the most significant bit of BCD code, A3 is always a “1” for decimal digit 8 and 9. An OR expression for bit A3 in terms of a decimal digits can there for be written is A3= 8+9 Bit A2 is always a one a decimal digit is always “1” for 4, 5, 6 or 7 and can be expressed as an OR function as follows. A2= 4+5+6+7 Bit A1 is always a one for decimal digit 2,3, 6 or 7 and can be expressed as A1 =2+3+6+7 Finally a zero is always a 1 for decimal digit 1,3,5,7, or 9 the expression for zero is A0=1+3+5+7+9
4. Questions
Modify the BCD to Decimal decoder circuit provided to give output of all 0’s when any invalid input combination occurs.
INSTRUCTOR VERIFICATION SHEET
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For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
EXPERIMENT # 8
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INTRODUCTION, IMPLEMENTATION AND WORKING WITH MULTIPLEXERS, DECODERS AND ENCODERS
1. Objectives: Having completed this experiment you will be able to Verify the basic operation and principle of Multiplexer, decoder and encoder.
2. Basic Information. a. A digital Multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and “n” selection lines whose bit combination determine which input is selected. b. A decoder is a combinational circuit that converts binary information from n input lines to maximum of 2n unique output lines. The decoders are represented as n-to-m where n is number of inputs and m is number of outputs. Hence, 2-to-4 decoder means that two inputs are decoded into 4 outputs. c. An encoder is a digital function that produces a reverse operation from that of a decoder. An encoder has 2n input lines and n output lines. The output lines generate the binary code for the 2n input variables.
3. Experimental Work. 3.1. Material Used. Components: 4073, 4049, 4071 Connecting Wires Logic Trainer 3.2. Procedure. We will implement the multiplexer circuit first. It is clear from the logic diagram that the AND, OR and NOT gate implementation of multiplexer requires four 3-input AND gates, one 4-input OR gate and two NOT gates. Get the required number of ICs containing above mentioned gates and other apparatus from the lab attendant. Install the ICs in the breadboard of the Logic Trainer. All three IC models used are 16 pin ICs. These are designed in such a way that pin number 8 is considered as ground and power is given to pin number 16. For other pin configuration consult the data sheet (we have already used these gates in the first lab so it should not be a problem). Wire your circuit according to the logic diagram for multiplexer circuit as given above. Once you have wired the circuit, check it with your instructor and, if approved, power up your circuit. The outputs should be connected to the LEDs on the Logic Trainer for monitoring purpose. Repeat the same procedure for decoder and encoder circuit.
a. Multiplexer
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Multiplexer, simply called Mux, is a data selector and is capable of “selecting” one of many input lines (usually 2n) and display its input status on the only output line available.
A Mux has 1. Select lines 2. Data input lines 3. Output line.
Block diagram of 2x1 MUX
I0 data i/p lines 2X1 MUX Y output I1
S
select line The function table of 2x1 Mux is
Select line o/p S Y
0 Io
1 I1
The Boolean function for 2x1 Mux is: Y = I1 s + I0 s
Logic Diagram of 2x1 Mux is
I1 s I0
I1 s
I1 s + I0 s' = Y To LED s'
I0 s'
Block diagram of 4x1 MUX
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I0
I1 Y data i/p lines 4X1 MUX I2 output I3
S1 S0
select lines
I0, I1, I2 and I3 are inputs of Mux S1 and S0 are select lines Y is output
The Boolean function for 4x1 Mux is
Y = I0 S1 S0+ S1 S0 I1+ S1 S0 I2+ S1 S0I3
Logic Diagram of 4x1 Mux is
S1 S0
I0 I0
I1 I1 Y To LED 2 I I2
I3 I3
b. Block diagram of 2x 4 Decoder
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D0 A D1 2 x 4 Decoder D2 B D3
The truth table of 2-to-4 line decoder is given below. The output variables of a decoder are mutually exclusive because only one output can be equal to 1 at any time.
Inputs Outputs
A B D0 D1 D2 D3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1
Draw the logic diagram of 2x4 decoder:
Draw the Block Diagram of 4-to-2 Encoder:
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Draw the logic diagram of 4x2 Encoder
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4. EXPERIMENTAL RESULT
Fill in the following truth tables while observing the outputs.
Truth table for 4x1 multiplexer:
Select inputs Output
S1 S0 Y
Truth table for 2x4 decoder: Inputs Outputs
A B D0 D1 D2 D3
Truth table for 4x2 encoder: Inputs Outputs
D0 D1 D2 D3 X Y
INSTRUCTOR VERIFICATION SHEET
FJWU, The Mall, Rawalpindi 46 BSE Digital Logic Design
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
EXPERIMENT # 9
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IMPLEMENTATION OF FULL ADDER WITH TWO, 2X4 DECODERS
1. Objective: Having completed this experiment you will be able to: Realize the use of decoders to implement full adders
2. Basic Information:
Decoder : n 2n. n = No. of input lines. 2n = No. of outputs of a Decoder. Decoder is a circuit that convert binary information from n-input lines to max of 2n output lines e.g. if we have 2 inputs i.e. x, y then there will be 4 outputs of a Decoder and size of Decoder will be 2x4.
Block Diagram of 2X4 Decoder . s e s
n d0 i e l x
n t i d1 l
u 2X4 t p u
n DECODER i d2 p
y t a u t
d3 o a d
E
Truth Table of 2X4 Decoder
x y E d0 d1 d2 d3 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1
Boolean Functions for 2 x 4 Decoder
do = E x′ y′ d1 = E x′y d2 = E x y′ d3 = E x y
Implementation
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3. Experimental Work 3.1. Material Used: Components: 4071, Connecting Wires Logic Trainer
3.2. Procedure: Implement Half Adder with 2x4 Decoder.
Truth Table of Half Adder
i/p’s o/p’s
x y SHA CHA 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
Truth Table of 2X4 Decoder
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i/p’s o/p’s
x y d0 d1 d2 d3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1
By comparing Truth Tables of half Adder and 2 X 4 Decoder.
We can see that SHA = d1 + d2 CHA= d3
Block Diagram of Half Adder with Truth Table of 2X4 Decoder
do open
x d1
2X4 SHA DECODER d2
y d3 = CHA
E
Note: By connecting an OR gate with output Pin 1 & 2 of 2X4 Decoder. Half Adder can be implemented with 2X4 decoder. Similarly by connecting two Half Adders, we can form a Full Adder by using 2, 2X4 Decoder.
FJWU, The Mall, Rawalpindi 50 BSE Digital Logic Design
Truth Table of Full Adder
i/p’s o/p’s
x y z SHA CHA 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
Block Diagram of Full Adder with 2, 2X4 Decoders .
Using the concept of implementation of Half Adder with 2X4 Decoder, we can implement Full Adder with 2, 2 X 4 Decoders.
do do open open
x d1 d1 2X4 SFA=x+y+z 2X4 DECODER DECODER d2 d2 SHA=x+y
y Z d3 d3 =CFA
=CHA CFA
E
Pin Configuration of 74LS139
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+5 V E 1 VCC 16 2 15
p x / HA i
s E S = x+y
e
a t
9
n
i l a 3 14
y p
/
D
3 i
s
e
a
t n
1
13 i l open 4 z a d0 D 5 S 12
d1 L d0 open s
4
p
e /
a 6 11
n t
7
s
i o l
1
a e
d2 d
a
d
p n
t
i /
HA l S =x+y a o 7 10 D d3 d2 8 9 (Cx+y+z)' SFA=x+y+z GND d3
CFA
(Cx+y)' Pin Configuration of 74LS139 (2, 2X4 DECODER)
INSTRUCTOR VERIFICATION SHEET
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For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
FJWU, The Mall, Rawalpindi 53 BSE Digital Logic Design
EXPERIMENT # 10
IMPLEMENTATION OF FULL ADDER WITH 8x1 MUX
1. Objective: Having completed this experiment you will be able to: Realize the use of multiplexer to implement full adders
2. Basic Information:
MUX: 2n 1. n = No. of select lines. 2n = No. of inputs of MUX if n = 3, size of MUX is 8x1 i.e.
BLOCK DIAGRAM:
I0
I1
2 s I e n i l
I3 t
u 8X1 MUX p
n 4 Y i I
a t output a
D I5
I6
I7
x y z select lines Function Table:
Select lines o/p x Y z Y
0 0 0 Io
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
Truth Table of Full Adder
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Inputs of Full Adder Outputs x y z S C 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
Function Table of 8x1 Mux
i/p of Full Adder = Select lines o/p of 8x1 o/p of 8x1 o/p of 8x1 of MUX mux mux mux x y z S = Y C = Y
0 0 0 0 0 I0
0 0 1 1 0 I1
0 1 0 1 0 I2
0 1 1 0 1 I3
1 0 0 1 0 I4
1 0 1 0 1 I5
1 1 0 0 1 I6
1 1 1 1 1 I7
3. Experimental Work: 3.1. Material Used: Components Connecting Wires Logic Trainer
3.2. Procedure: Connect the selection switches of both MUX to input bits.
First of all we check/implement Carry of Full Adder (having 3 inputs) using 8X1 Mux, for this take:
FJWU, The Mall, Rawalpindi 55 BSE Digital Logic Design
I0 = I1 = I2 = I4 = 0, I1 = 0, I2 = 0, I3 = I5 = I6 = I7 = 1, from Carry column of Truth table of Full Adder and then select x, y, z from Function table of 8X1 Mux and then observe outputs at Y Pin, that should be equal to Carry of Full Adder for combination of x, y, z at select lines, which is inserted through data switches, this step is repeated for all x, y, z combinations, at select lines to observe Carry of Full Adder.
Then we check/implement Sum of Full Adder for 3 input variables, using 8X1 Mux for this, we take: I0 = 0, I1 = 1, I2 = 1, I3 = 0, I4 = 1, I5 = 0, I6 = 0, I7 = 1, from Sum column of Truth Table of Full Adder, as data inputs to 8X1 Mux, and then for each combination of x, y, z at select lines from Function table, we see output at Y Pin of the IC, which should be equal to value of Sum of Full Adder for x, y, z combination at select lines, which is inserted through data switches, this step is repeated for all x, y, z combinations, at select lines to observe Sum of Full Adder.
4. Experimental Results:
Draw the complete circuit diagram of above arrangement
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INSTRUCTOR VERIFICATION SHEET
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
FJWU, The Mall, Rawalpindi 57 BSE Digital Logic Design
EXPERIMENT # 11
VERIFICATION OF THE TRUTH TABLE OF RS FLIP FLOP
1. Objective: Having completed this experiment you will be able to Understand the basic concept of Flip Flops Recognize its working according to their truth table. Working with the IC chip of RS flip flop. Design a circuit of RS flip flop using NAND and NOR gates.
2. Basic Information. Flip-flops (FFs) are devices used in the digital field for a variety of purposes. When properly connected, flip-flops may be used to store data temporarily. Flip-flops are bistable multivibrators. The types used in digital equipment are identified by the inputs. They may have from two up to five inputs depending on the type. They are all common in one respect. They have two, and only two, distinct output states. The outputs are normally labeled Q and Q’ and should always be complementary. When Q = 1, then Q’ = 0 and vice versa.
The R-S FF is used to temporarily hold or store information until it is needed. A single R-S FF will store one binary digit, either a 1 or a 0. The standard symbol for the R-S FF is shown in figure below.
S Q
FF
R Q’
2.1: Draw the RS flip flop using NOR gates:
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To understand the operation of the RS-flip-flop (or RS-latch) consider the case when S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0. Hence both inputs to the top NOR gate are equal to one, thus, Q=1. Hence, the input combination S=1 and R=0 leads to the flip-flop being set to Q=1. S=0 and R=1: Similar to the arguments above, the outputs become Q=0 and Q'=1. We say that the flip-flop is reset. S=0 and R=0: Assume the flip-flop is set (Q=0 and Q'=1), then the output of the top NOR gate remains at Q=1 and the bottom NOR gate stays at Q'=0. Similarly, when the flip-flop is in a reset state (Q=1 and Q'=0), it will remain there with this input combination. Therefore, with inputs S=0 and R=0, the flip-flop remains in its state. S=1 and R=1: This input combination must be avoided.
Truth Table for RS flip-flop with NOR Gates:
Inputs Outputs Comments R S Q Q’ 0 1 1 0 Set 0 0 1 0 Hold 1 0 0 1 Reset 0 0 0 1 Hold 1 1 ? ? Avoid Truth table RS flip flop
3. Experimental Work: 3.1 Material Used. Logic trainer Connecting wires IC: 4011, 4001 Power supply
3.2 Procedure: The NOR gate implementation of RS flip-flop requires NOR gates AND gates. Get the required ICs and other apparatus from the lab attendant. Install the IC 7400 in the breadboard of the Logic Trainer. Connect 5Vdc power supply and ground on pins 14 and 7 respectively. For other pin configuration consult the data sheet (we have already used these gates in the first lab so it should not be a problem). Wire your circuit according to the logic diagram you have drawn. Once you have wired the circuit, check it with your instructor and, if approved, power up your circuit. The outputs should be connected to the LEDs on the Logic Trainer for monitoring purpose. Apply different input combinations at the input and note down the Q and Q’ outputs and fill in the following truth table. This truth table should conform to the one given in theory. If there are problems, consult the appendix on troubleshooting given at the end of lab manual. If the problem persists, request the lab supervisor for help.
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4. Experimental Results: Fill in the following truth table by observing the outputs.
Truth Table for RS flip-flop with NOR Gates:
Inputs Outputs Comments S R Q Q’ 0 0 0 1 1 0 1 1
5. Question: Draw the circuit of RS Flip flop using NAND gates and also draw its truth table.
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INSTRUCTOR VERIFICATION SHEET
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
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EXPERIMENT # 12
VERIFICATION OF THE TRUTH TABLE OF JK FLIP FLOP
1. Objectives: Having completed this experiment you will be able to Understand the basic concept of Flip Flops Recognize its working according to their truth table. Working with the IC chip of JK flip flop. Design a circuit of JK flip flop using NOR and AND gates
2. Basic Information. A JK flip flop is a refinement of the RS flip-flop such that the undetermined state of the RS type is defined in the JK type. It has two inputs, traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge. If J and K are both low then no change occurs. If J and K are both high at the clock level then the output will toggle from one state to the other. The JK flip-flop is represented by the following graphic symbol:
Q Q’
J K
CP Graphic symbol for JK flip-flop
In a clocked JK flip-flop, output Q is ANDed with K and CP (clock pulse) inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q’ is ANDed with J and CP inputs so that flip-flop is set with a clock pulse only if Q’ was previously 1.
Characteristic table for JK flip-flop is given below: Q J K Q(t+1) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 Characteristics table for JK flip - flop
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2.1: Draw the logic diagram of a JK flip flop using NOR and AND gates:
Fill the following characteristics table for NAND gate JK flip flop:
Q J K Q(t+1) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Characteristics table NAND gates JK flip - flop
3. Experimental Work: 3.1 Material Used. Logic trainer Connecting wires IC: 4011, 4001 Power supply
3.2 Procedure: The implementation of JK flip-flop requires two 2-input NOR gates and two 3-input AND gates. Get the required ICs and other apparatus from the lab attendant. Install the ICs in the breadboard of the Logic Trainer. Connect 5Vdc power supply and ground on pins 14 and 7 respectively. For other pin configuration consult the data sheet (we have already used these gates in the first lab so it should not be a problem). Wire your circuit according to the logic diagram you have drawn. Once you have wired the circuit, check it with your instructor and, if approved, power up your circuit. The outputs should be connected to the LEDs on the Logic Trainer for monitoring purpose. Apply different input combinations at the input and note down the Q (t+1) outputs and fill in the
FJWU, The Mall, Rawalpindi 63 BSE Digital Logic Design following truth table. This truth table should conform to the one given in theory. If there are problems, consult the appendix on troubleshooting given at the end of lab manual. If the problem persists, request lab supervisor for help.
Repeat the same procedure for implementation of JK flip-flop with NAND gates.
4. Experimental Results: Fill in the following truth tables by observing the outputs. JK with NOR gates: Q J K Q(t+1)
Observed characteristics table for NOR JK flip - flop
JK with NAND gates: Q J K Q(t+1)
Observed characteristics table for NAND gates JK flip - flop
INSTRUCTOR VERIFICATION SHEET
FJWU, The Mall, Rawalpindi 64 BSE Digital Logic Design
For each verification, be prepared to explain your answer and respond to other related questions that the lab TA’s or Instructors might ask.
Name: Date of Lab:
Verified: Date/Time:
FJWU, The Mall, Rawalpindi 65 BSE Digital Logic Design
Appendix A: Use good construction practices
ESD (Electro-Static Discharge) prevention: The failure rate of electronic components (including IC's) that are produced worldwide is only a few PPM (parts per million). The failure rate in our labs, where we don't use proper techniques to prevent ESD damage due to handling seems to be more like 10%. Could it be that we are damaging the parts?!! Most successful companies will train you in ESD damage prevention, but would then FIRE you for handling parts the way we do in most KSU labs. Use wrist straps and understand ESD damage prevention. Use ONE common ground point. Keep inputs and low-level signal stages away from digital, output, and high power stages. You may even create an unwanted oscillator if you don't do this. For some applications, you need to isolate stages with a transformer or an opto-isolator to avoid ground problems. Be sure that your logic levels are all the same or provide level shifters. Beware of mixing TTL and CMOS. Do not leave inputs of "unused" op amps, comparators, or CMOS logic gates open. Connect them to an appropriate fixed voltage. DO leave the outputs floating.
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Appendix B: Troubleshooting
o Turn on the DC power first, and then the signals. (Avoid latch-up) o Keep a current copy of your circuit diagram beside the circuit and correct it as you make changes. Keep a paper trail, or listing, of your lab work. o Keep your layout neat and label nodes on bigger circuits. o Check your DC power supply currents. If you have current limiting on the supplies, set it just above what you expect for the total current. o Watch for smoke and/or hot parts. (Use saliva on your digit temperature sensor to avoid burns.) o Be sure that the COMmon of the power supply is connected to ground. The "ground" of many power supplies is isolated from the supply outputs. o Check the DC level at the output of each active device. If it's about equal to the positive or negative supply it's saturated or cut-off. Check all DC bias points.
Vbe's should be about .7V and FET gates should be greater than VT's if they're supposed to be on. o Look for loose wires. o Now start checking signals: Use an oscilloscope to monitor signals starting at the input. o Recheck your circuit wiring one more time. This is the most common error and by now you should have a good idea where the problem is located. o If you observe 60Hz where signals should be you probably had an open ground somewhere. o Isolate parts of the circuit if you can and test individual circuits. This will not always work with feedback circuits, because the feedback may be required to give a stable operating point. o If you suspect a bad part, turn off the signal first, and then the dc power. Finally, remove and replace the part. o Perhaps the most important thing is to understand what each part of the circuit is supposed to do and then play like a detective. o Make measurements as near full scale on the meter as possible. o Make a note of measured voltages on the circuit diagram. o Think!
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Appendix C: Safety
Freedom from preventable accidents is an important measure of the foresight and capability of supervision in the engineering industries. The student should give thought to the subject of accident prevention early in his or her training. He or she should prepare mentally to recognize and avoid dangerous situations, and to cope with emergencies. A set of rules cannot be made to apply to all situations. The student should develop the ability to analyze a particular situation. An engineer's reputation for reliability is seriously injured if his lack of foresight results in injury to himself, associates, or equipment. Haste causes many accidents. Work deliberately and carefully. Verify your work as you go along. Documentation and good planning before coming to the laboratory will promote safety.
When working on live electrical apparatus, use only one hand as far as practical, keeping the other hand disengaged from circuitry. All ac power circuits are dangerous. Adjustment in energized circuits should be made with caution. Do not permit any part of your body to complete a circuit. Close power switches quickly and positively. Hesitant closing may result in an electric arc. Burns from an electric arc maybe severe and slow-healing. You can depend on the circuit breakers and fuses in the circuit to prevent over-currents. (Electric arcs and contact lenses are a bad combination.) Be careful to keep watch bands, rings, necklaces, and other metallic objects out of contact with live parts when working around electrical apparatus. It is a good idea to remove watches with metal bands while working in the laboratory. Long hair should be "up" when working around rotating machinery. Likewise, loose clothing, neckties, etc., should be avoided around rotating machinery. Make sure the banana plugs fit snugly in their sockets. Sometimes they get old and worn so that they slide out too easily. Never splice two banana cords together so that electrically "hot" metal is exposed on the bench. There are a number of banana sockets on the bench which can be used if splicing is necessary. If any banana jack connectors are loose on their cords, or if any sockets are loose, report them immediately to the lab instructor. When wiring a circuit, always connect to the source of power as the last step. When disassembling a circuit, disconnect from the power source as the first step. Never work alone in the laboratory. Injury could occur and there would be no one present to help you.
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