Department of Electrical and Computer Engineering s4

Department of Electrical and Computer Engineering, University of Calgary FINAL EXAM FOR ENEL415 DECEMBER 12th 1998 3 HOURS

NAME:- ID#:-

PLEASE WRITE CLEARLY. USE AN HB GRADE OR SOFTER (DARKER) PENCIL! WHAT I CAN=T READ WILL MARKED WRONG.

CLOSED BOOK EXAM DO NOT BRING ANY UNAUTHORIZED MATERIAL INTO THE EXAM ROOM However, students are allowed to bring in an unmarked copy of the Motorola 68000 reference charts. You have been provided with a PI/T, D/A, A/D and SDS reference sheet as part of the exam handout. NO CALCULATORS ARE ALLOWED IN THIS EXAM

Attempt all THREE questions from SECTION A and ANY TWO questions from SECTION B. All questions are approximated weighted equally in terms of marks, but not difficulty Indicate your estimate of your performance in the table below for a maximum bonus of 5 marks

A hint of the time to spend on each part of a question is given by the relative number of marks associated with that question part. Answer the questions in the space provided on the exam sheet. The space and marks allocated are an indication of the depth of the answer expected. Make sure that you provide appropriate documentation of code and answers as marks are allocated for this documentation. Follow standard AC/C++@ conventions and recommended safe practices in your coding. Good software engineers keep track of their progress and can estimate their success. In the table below, indicate questions attempted and your estimate of how well you have answered the question. For each estimate that matches the mark you actually receive, you will receive a bonus mark to make up for the time lost answering this section -- maximum bonus 5 marks

MAXIMUM YOUR MARK ESTIMATE OF YOURCircle Give Expected Grade Mark 22 marks available SECTION A Q1 A B C D F Basic general knowledge Recorded out of 20 Basic general knowledge / SECTION A Q2 20 A B C D F Public Safety Issues 21 marks available Basic general knowledge / SECTION A Q3 A B C D F Recorded out of 20 Interrupt Service Routines

SECTION B Q4 21 marks available A B C D F Array and stack handling Recorded out of 20 22 marks available SECTION B Q5 A B C D F CISC/DSP comparison Recorded out of 20

SECTION B Q6 20 A B C D F Design using Laboratory 4 Concepts

SECTION B Q7 20 A B C D F Your choice of question and answer

YOUR ESTIMATE OF Process management component of the exam Bonus if prediction of mark on a question is accurate to +-1 (estimates of unanswered questions excluded) Bonus if prediction of final mark on quiz is accurate to +-3 Maximum of 5 Bonus marks PAGE 1 OF 15 Q1. Consider the Screen Dump shown above for assembly language program displayed within the SDS development environment

A) Circle, and label with an A, the menu option that will allow you to specify the processor to be simulated. – 1 mark

B) Circle, and label with a B, an example of a value that will be on the DATA BUS during the FETCH phase of an instruction. -- 1 mark

C) Circle, and label with a C, an example of a value that will be on the ADDRESS BUS during the FETCH phase of an instruction. -- 1 mark

D) Circle, and label with a D, an example of a value that will be on the DATA BUS during the WRITEBACK phase of an instruction. -- 1 mark

E) Circle, and label with a E, an example of a value that will be on the ADDRESS BUS during the WRITEBACK phase of an instruction. -- 1 mark

F) Just BEFORE the RTS instruction is started what will be the 32- bit value in REGISTER D1 ______-- 1 mark

G) As you START the RTS instruction. what will be the value in the program counter? ______-- 1 mark

H) As you START the RTS instruction. what will be the value in memory location 0x7000? ______-- 2 marks

I) What will be the value returned by this subroutine? ______-- 2 marks PAGE 2 OF 15 J) Using the information in the 3 windows on the previous page, determine the storage location in memory of the NEXT INSTRUCTION to be executed AFTER the RTS instruction? ______-- 1 mark

Suppose that this subroutine is a new set of code that a student has added to some previously tested and working code. Simply by looking at the three windows associated with the code sequence on the previous page, and thinking about the answer to PART J, I, as an instructor can see that a DEFECT has some how occurred in the student’s code and the program will very shortly crash.

K) Using SOFTWARE ENGINEERING TERMINOLOGY, what is a DEFECT? -- 2 marks

L) What is the problem that I have spotted, and why can I be sure that the problem is a DEFECT and not an ERROR?  3 marks

M) Consider the 3 MOVE instructions at memory locations 0x101E, 0x1020, 0x1024 on the screen dump. Suppose that they were being executed on an XXXX processor that could execute 68K machine code instructions, but this processor was designed to operate where instruction phases involving memory fetches take twice as long as any other instruction phase. Determine how long it would take this XXXX processor to execute these 3 instructions if the processor did not have PREFETCH capability. Determine how long with PREFETCH capability. Use the tables below to show how you reached these conclusions -- 5 marks

WITHOUT PREFETCH WITH PREFETCH FETCH DECODE EXECUTE WRITEBACK FETCH DECODE EXECUTE WRITEBACK

OF 15 Q2 A) Would a 68K processor branch after the following instruction sequence? Explain! 2 marks

MOVE.B #254, D0

______MOVE.B #2, D1 SUB.B #4, D1 ______CMP.B D1, D0 BEQ TO_BRANCH_OR_NOT_TO_BRANCH ______

I would claim that determining whether a student programmer could correctly answer Q2 A) should be a significant part of any interview for an embedded system job involving PUBLIC SAFETY

B) What is AN EMBEDDED SYSTEM, and would it more likely involve the use of MICROPROCESSORs or MICROCONTROLLERS, and what has PUBLIC SAFETY got to do with it? 3 marks

C) Write a SDS compatible, 68K assembly language code segment that would correctly handle the following requirements. Both address registers A0 and A1 contain pointers to memory locations that store a signed char value. Write a code segment that will add together those 2 signed char values and store the correct result in memory location 0x2000 6 marks

Out of all the ENEL415 classes I have taught in the last 5 years, I think that the 1998 class is the one that is the most aware of the effect that poor programming practices have with the important public safety issues with which all engineers should be concerned. Despite this, I will claim that if Q2C had been the assembly language test question for the job interview mentioned after Q2A, then 65% or more of the class would have failed the interview.

If you are going back to find and correct the problem, then a little hint :- it is not a SYNTAX type problem but a DESIGN problem and will loose you 2 of the 6 marks associated with Q2C if not corrected.

CLASS CHALLENGE – I believe that, despite the warning about the design error in Q2C, 30% or more of the class will be unable to find and correct the DESIGN error. I will have Teaching Assistant. James mark this question and keep track of how many students still make this error. If less that 30% of the class make the design error, I will apologize to the class by sending in a $25 donation to the Salvation Army Christmas Relief Fund in their name. PAGE 4 OF 15 D) Just what would the PARTIAL DECODE LOGIC look like to activate the chipselect line (CS) for a PI/T with a base address of 0x41A000. HINT: Consider that the PI/T here has the same register configuration as those in the laboratory so you will need the information associated with PITNAMES.H (see back of front cover of this exam). Assume you have as many 4-input AND gates and 1-input inverters as necessary to build the LOGIC --- 3 marks

You are provided with a routine void ResetPIT(signed char *pt) written in “C/C++”. This routine will correctly configure the PI/T in the laboratory (pointed to by the parameter pt) so that all 8-pins on PORT B can act as non- latched input and no interrupts are active.

E) What does the expression “non-latched input” mean? -- 1 mark

F) Write a SDS compatible, 68K assembly code routine signed char ReadPIT(signed char *pt) that uses the function void ResetPIT(signed char *pt) to reset the PI/T, and then reads and returns the value presented by an external device to the PORTB inputs -- 5 marks

Q3 A) Reverse engineering of assembly code (understanding the assembly code in terms of various AC/C++@ language constructs) is an important skill to have.

What would be the PROBABLE AC@ language PROTOTYPES for the functions being called in the following code segments. Note the key words -- PROTOTYPES for the functions 3 marks

JSR FirstFunc ______ADD.B D0, D3

MOVE.L A0, 0(SP) JSR SecondFunc ______MOVE.L D0, D3

MOVE.L #6, 4(SP) JSR ThirdFunction ______

Consider the following “C/C++” code sequence

#pragma interrupt void SomeFunction(long int *pt) {

Lots of “C/C++” code here

B) What is the student attempting to do, and will it work? If not – why not? 2 marks

Consider the interrupt service routine (ISR) shown in the above screen capture.

C) How fast would this ISR operate on a 32 MHz 68K processor. Make your procedure for doing this calculation clear or there will be no way I can give full or partial marks. 5 marks

OF 15 D) i) One important part of an ISR is the need to ACKNOWLEDGE (or clear) THE INTERRUPT. What happens if you don’t acknowledge the interrupt? 1.5 marks

ii) You have no real way of knowing, but if you were going to hazard a guess which instruction from the screen dump was the ACKNOWLEDGE THE INTERRUPT instruction, which one would you guess and why that instruction and not one of the others? 1.5 marks

iii) I can almost guarantee that the use of this code will crash the program – why, and what would you need to do to fix the problem? State the answer, don’t code it 1.5 marks

iv) It is very important that interrupt service routines occur quickly – Why and what happens if they don’t? 1.5 marks

v) Recode the instructions from the screen dump so that the same operations occur, but they occur as fast as possible, and correctly. 3 marks

vi) Write a 68K assembly language code segment that will enable the interrupt service routine from the screen dump to be activated by the instruction TRAP #4 2 marks

OF 15 SECTION B ATTEMPT ANY 2 QUESTIONS FROM THIS SECTION THE QUESTIONS IN THIS SECTION ARE INTENDED TO BE MORE DIFFICULT THAN THOSE FROM SECTION A

Q4) A) When different programmers are building a stack for use within a “C/C++ compatible assembly language subroutine” which of the following items on the stack can be placed in the order the programmer would like, without regard to any coding conventions? 1.5 marks

Return address, return values, incoming parameters, outgoing parameters, arrays, local variables

B) A common problem in the laboratories is that students don’t remember to PUT THINGS ONTO THE STACK, AND TAKE THINGS OFF OF THE STACK as LONGs. Why do you have to do this? 1.5 marks

______

C) As the resident expert in assembly language programming, you have been asked to customize (optimize for speed) the “C/C” system call long int strlen(char *pt) which returns the length of an ascii character string. 5 marks

Example: If we had char pt[] = “0123456789” then strlen(pt) would return 10. Remember that in “C/C++”, all ascii character strings are terminated by the NULL or End-of-String Character.

#define EOS ‘\0’

______

of 15 This question is related to a device that is very similar to the COFFEEPOT device in Laboratory 2. The BASEADDRESS for this COFFEEPOT is 0x120000. The COFFEEPOT device registers are all 8 bits wide.

There is a CONTROL – REGISTER which is offset from the BASEADDRESS by 10 bytes. Bit 0 of this CONTROL- REGISTER is a RESET_BIT which the programmer must activate in order to make the device operate. When Bit 1, the ALARM bit is set, then a warning will sound.

The TEMPERATURE register is offset from the BASEADDRESS by 4 bytes. The temperature sensor provides temperature readings from –64C to +63.5C in 0.5C increments. Bit 7 of the CONTROL-REGISTER is the READ_READY bit which indicates that the analog-to-digital converter attached to the temperature sensor attached to the water reservoir is giving a valid reading.

D) What is an ANALOG-to-DIGITAL converter and why would you need one? 2 marks

______

E) Why would it be necessary to have a READ_READY bit? After all, the water in the water reservoir will either be hot or not – time does not have anything to do with it. 2 marks

F) Design, Document and Code a “C/C++” compatible, SDS 68K assembly language subroutine void ReadTemperatureAndStore(signed char *ptARRAY, short int number). This subroutine resets the COFFEEPOT device and then samples number of temperature values and stores each of them into a signed char array pointed to by the parameter ptARRAY. Before storing the values it will be necessary to adjust the temperature as it is known that the temperature sensor was bought second-hand and always reads 10C too low. 9 marks

If you are pushed for time, then remember where I tend to put the marks for a DESIGN, DOCUMENT and CODE question.

______

______PAGE 9 OF 15 Q5 POST LABORATORY QUIZ 0 – ENEL515 – JANUARY 1999 At this point in the term I am getting rather pushed for time. I am trying to prepare for my ENEL515 laboratories which will make use of the Analog Devices ADSP21060 SHARC processor. I am unfamiliar with this processor so I am currently trying to program it using the pretend that it is really a 68K processor technique.

To help me get prepared for this new course, and at the same time develop questions for the ENEL415, I have decided that you and I will explore this processor, its architecture and instruction set by comparing and contrasting this new processor with the 68K processor used in the labs.

A) According to Analog Devices advertizing brochures, the name SHARC actually stands for Super Harvard Architecture Computer in contrast to the 68K processor’s von-Neumann Architecture. In diagrams and words, explain the difference between these two architectures. If you don’t know what a Super Harvard Architecture looks like, you’ll get almost as many marks for describing the Harvard Architecture 3 marks

______

B) The SHARC processor has 16 data registers and 16 address registers (called index registers). Why would this offer a speed advantage over the 68K’s 8 data and 8 address registers? 1.5 marks

______

C) The SHARC processor has instructions that are 40-bits wide. Why would these op-codes offer a speed advantage over the 16-bit op-codes of the 68K processor? 1.5 marks

______

D) The SHARC processor has an on-board instruction cache of about 40 instructions. Under what circumstances would this cache be useful? 1.5 marks

______

______E) The SHARC processor operates with three instruction phases – FETCH, DECODE and a combined EXECUTE/WRITEBACK phase. With branch, jump or subroutine calls, the processor operates with what is known as a DELAYED BRANCH mode where the processor always executes the 2 instructions after the JUMP before the JUMP instruction is completed. Explain the speed advantage this offers the programmer? 2.5 marks

Q5F) To correctly apply the coding convention for passing parameters into subroutines using the ADSP21061 is rather complicated. However, in its simplest form, the first 3 parameters are passed into subroutines using the 21061 registers R4, R8 and R12. If we just consider setting up the stack and passing 3 parameters into a 68K subroutine, how much faster is the ADSP21061 approach to parameter passing than then 68K processor, when this simple case applies? Explain your answer and any assumptions you have made. 4 marks

______

Q6G) It is possible to add two registers together and place the answer into a third register using the single 21061 instruction R4 = R3 + R2 (nice assembly language syntax Eh!). What would be the equivalent operation on the 68K processor? If the 21061 processor is capable of performing 1 instruction every clock period and runs at 180 MHz, how much faster will it perform this register add compared to an 8 MHz 68K processor? Explain your reasoning 4 marks

______

Q6 H) The main advantage of the 21061 is its crazy DSP-useful addressing modes using its index (address) registers (I0 to I15), MODIFY registers (M0 to M15), LENGTH registers (L0 to L15) and BASE registers (B0 to B15)

PRE-MODIFY ADDRESSING MODE -- R4 = dm(Mx, Ix) -- means place the value at data memory location Mx + Ix into register R4

POST-MODIFY ADDRESSING MODE – R5 = pm(Ix, Mx) – means place the value at program/data memory location lx into register R5 and then modify (increment) the index register by the value Mx

POST-MODIFY ADDRESSING MODE WITH MODULO ADDRESSING – R7 = pm(Ix, Mx, Lx) – means place program/data memory location lx register R5 and then increment the index register by the value Mx, and if the new index register value Ix is greater not in the range Bx to Bx + Lx - 1, then perform the operation Ix – Lx until it is that range.

The following is a SINGLE ADSP21061 instruction that can be performed in ONE CYCLE and is very useful for operations such as the Fast Fourier Transform algorithm (which you may know as the FFT)

R0 = R3 + R4, R1 = R3 – R4, R5 = dm(M1, I1), R6 = pm(I5, M5, L5)

Just how many 68K instructions would be necessary to perform the same operation? Explain. 4 marks

______

______PAGE 11 of 15

Q6) In England, a favourite candy (sweet) is HUNDREDs and THOUSANDs. This is a very tiny candy almost the size of dust – typically coloured RED and YELLOW which is collected into a small plastic bag. Your job is to DESIGN, DOCUMENT and DEVELOP a program using a combination of “C/C++” and 68K assembly code to fill bags with the candies. If you are pushed for time, then remember where I will be concentrating the marks in a design question.

This is also an open-ended Design question and you are required to make some educated, engineering relevant design decisions.

A) The first step is to hook up the PI/T interface to the equipment showing which pins are input and output (see diagram above). 4 marks  Bit 7 is connected to the clock. Every time this clock goes high the device is considered to be ready.  Bits 0 and 1 are connected to the RED counter – These two bits represent a value of 0, 1, 2 or 3 indicating how many RED Hundred and Thousands have dropped past the sensor  Bit 2 is connected to the RED Hopper. Setting this to 1 causes the RED candy to start dropping into the bag  Bits 3 and 4 are connected to the YELLOW counter -- These two bits represent a value of 0, 1, 2, 3  Bit 5 is connected to the YELLOW Hopper. Setting this to 1 causes the YELLOW candy to start dropping  Bit 6 is connected to the alarm  Bit H2 is connected to the EMPTY signals from both hoppers. These signals are HARDWIRED as an OR GATE by connecting them together and then connecting them, via a 10K resistor to +5V – a typical real-life configuration

B) There are many ways to develop this design, with and without interrupts – it is going to be your choice. Read through the rest of the question, and then develop a “C/C++” callable 68K assembly code subroutine void ResetPIT(unsigned char *pt) which will initialize the PI/T in the configuration you have designed 3 marks

______

C) Assume that the device has already been RESET. You are to write a “C/C++” callable 68K assembly code return short int CountYellow(unsigned char *pt) which reads the YELLOW COUNTER bits and returns the number of YELLOW Hundreds and Thousands that have gone past – the YELLOW COUNTER never overflows. CAREFUL 4 marks ______

______

______PAGE 12 of 15

D) Making use of the diagram and functions of the previous page, you are to design, document and code a “C/C++” main() function that will activate the hoppers to start releasing the RED and YELLOW hundreds and thousands into the plastic bag. The plastic bag is considered full when there are 1000 pieces in the bag. To maximize profits, keep the number as close to 1000 as possible, Don’t put in less than 1000 as you’ll be ripping off all the kiddies, and also remember what happened to the BAKERs in Henry II day and resulted in the need for a BAKER’S DOZEN! You may assume that the routine short int CountRed(unsigned char *pt) is available for you to use. 9 marks ______

______

______PAGE 13 of 15

Q7) Don=t you just hate it when you=ve got some neat ideas about some concept, or have done research beyond the course content, and then the examiner does not ask any questions in that area! Here is a chance to overcome that problem.

Make up a question related to this course and answer it. (20 marks)

TO RECEIVE FULL MARKS the question should satisfy the following criteria  Be at a difficulty level suitable for a final exam question in the 3rd year of an Electrical and Computer Engineering program. Quick test -- Would it be suitable for next year=s final?  It should NOT be equivalent to any exam question already asked in this course.  It should not be a regurgitation of an idea I=ve done in class or presented in a previous quiz/exam. Give me something different. Give me a question that, under different circumstances, would present A CHALLENGE FOR YOU to answer in either Section A or Section B of a final exam.

______

______Page 14 of 15

______

______Page 15 of 15 EXTRA PAGE ---- IN-CASE YOU NEED IT FOR A LONG ANSWER

______

// pitnames.h

// The following are the definition for major register offsets MC68230 PIT // We are using label names from Clements // Offsets are different as lowest line on board is A4 and on Clements A1 #define PGCR 0x0000 // Port general control register R/W #define PSRR 0x0010 // Port service request register R/W #define PADDR 0x0020 // Port A data direction register R/W #define PBDDR 0x0030 // Port B data direction register R/W #define PCDDR 0x0040 // Port C data direction register R/W #define PIVR 0x0050 // Port interrupt vector register R/W #define PACR 0x0060 // Port A control register R/W #define PBCR 0x0070 // Port B control register R/W

#define PADR 0x0080 // Port A data register R/W #define PBDR 0x0090 // Port B data register R/W #define PAAR 0x00A0 // Port A alternate register R #define PBAR 0x00B0 // Port B alternate register R #define PCCR 0x00C0 // Port C control register R/W // Can't use PSR as "as68000" claims that it is reserved word. #define PIT_PSR 0x00D0 // Port Status register R/W //// 00E0 //// 00F0

#define TCR 0x0100 // Timer Control Register R/W #define TIVR 0x0110 // Timer interrupt vector register R/W //// 0120 #define CPRH 0x0130 // Counter preload register high R/W #define CPRM 0x0140 // Counter preload register medium R/W #define CPRL 0x0150 // Counter preload register low R/W //// 0160 #define CNTRH 0x0170 // Counter register high R #define CNTRM 0x0180 // Counter register medium R #define CNTRL 0x0190 // Counter register low R #define TSR 0x01A0 // Timer status register R/W //// 01B0 //// 01C0 //// 01D0 //// 01E0 //// 01F0

EXTRA PAGE ---- IN-CASE YOU NEED IT FOR A LONG ANSWER

______