Gray Code Conv. Lab

CSE/ECE 378 Computer Hardware Design D. M. Hanna Fall 2006 R. E. Haskell

Lab 7 – UART and RAM

Write a VHDL program called Lab7.vhd that will download some interesting and/or useful data from a file on the PC through the serial port on the Spartan 3 board and store this data in the SRAM on the back of the board that you use as a video RAM. Display the contents of the video RAM on the VGA monitor.

1. Implement the transmit, UART_TX, component for transmitting 8 bits of data using synchronous serial communication described in 10.1:9-20. Use these components to implement the transmit test component described in 10.1:21-30. Remove the debounce circuit and the clock divider from the design so that the transmitter is run directly from the mclk signal. Perform a functional simulation for the serial transmitter to ensure that it works properly.

2. Carefully follow the instruction in Appendix 7.1 to measure the power and energy consumed for transmitting a byte of data. Hand in a printout of the Power Report for the 5 MHz experiment.

3. Next, implement the receive, UART_RX, component for receiving 8 bits of data described in 10.1:31-38. Design a state machine controller for this component that will receive data through the serial port and store this data in the SRAM on the back of the board.

4. Finally, create a state machine that uses the SRAM data as the data for the VGA monitor.

5. Demonstrate the operation of your program to your lab instructor and get his signature on a copy of Lab7.vhd.

6. Hand in a listing of Lab7.vhd as well as files that define your datapath and control unit(s). Also, hand in a printout of the power report for the 5 MHz experiment in #2.

7. Be prepared to demonstrate and discuss your program to the class during lecture. Bring your .bit file plus your file to download on your USB stick in a separate directory. Points will be deducted if both the .bit file and the file to download are not immediately accessible in class, if asked.

1 APPENDIX 7.1: POWER AND ENERGY REQUIREMENTS

The FPGA requires a minimum power while sitting idle. Additionally, the FPGA consumes more power while executing. We will measure the power and energy required to send 8-bits of data. Perform a functional simulation for the top-level component, uart_tx_test. The options for the Functional Simulation are shown below.

Set the top-level by selecting the input files, namely uart_txt_test.vhd.

Choose the uart_tx_test top level.

Check the box to use the Default Waveform.

Click OK

Set the stimulators for the following signals:

SW: Value of 16#A5 mclk: Clock signal of 25 MHz BTN(3): A formula signal of “0 0 ns, 1 20 ns, 0 50 ns” (a 30 ns pulse for the clr) BTN(1): A formula signal of “0 0 ns, 1 100 ns, 0 200 ns” (a 100 ns pulse for the “GO” following the clr)

Run the simulation for 1.5 ms Click the Zoom-to-Fit icon to zoom out.

The “A5” is sent out 1 0 1 0 0 1 0 1 least significant bit first. 5 A (reading right to left)

Save this Waveform as txwaveform. 2 We will use XPower to obtain information about the power required for sending our “A5” using a 25 MHz clock. In order to do this, we need to Synthesize and Implement the design to the correct FPGA.

Select the correct top-level and FPGA details from the Synthsis Options and Synthesize the uart_tx_test. After synthesis is complete, Implement the design. Create a .ucf file according to the nets shown below using PACE. Don’t forget to set the .ucf file in the Implementation Options. It is not necessary to create a .bit file since we will not be downloading this to our board for testing.

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments NET "BTN<0>" LOC = "M13" ; NET "BTN<1>" LOC = "M14" ; NET "BTN<2>" LOC = "L13" ; NET "BTN<3>" LOC = "L14" ; NET "LD<0>" LOC = "K12" ; NET "LD<1>" LOC = "P14" ; NET "LD<2>" LOC = "L12" ; NET "LD<3>" LOC = "N14" ; NET "LD<4>" LOC = "P13" ; NET "LD<5>" LOC = "N12" ; NET "LD<6>" LOC = "P12" ; NET "LD<7>" LOC = "P11" ; NET "mclk" LOC = "T9" ; NET "SW<0>" LOC = "F12" ; NET "SW<1>" LOC = "G12" ; NET "SW<2>" LOC = "H14" ; NET "SW<3>" LOC = "H13" ; NET "SW<4>" LOC = "J14" ; NET "SW<5>" LOC = "J13" ; NET "SW<6>" LOC = "K14" ; NET "SW<7>" LOC = "K13" ; NET "TxD" LOC = "R13" ;

After Implementation is complete, click the Analysis icon and select the Options for XPower.

Be sure that NCD/CXT file is filled in. If not, Browse to find uart_tx_test.ncd.

The Constraint file should also be filled in automatically. 3 Click OK.

Now, click the XPower Icon to launch the Xilinx XPower program.

In order to conduct a timing simulation

Idle FPGA power: the power required to power the FPGA with the design stored without executing anything.

4 Click the Power Subtotals tab.

The power required by clocks, inputs, logic, outputs, and signals are all zero. The power required by these are all zero because we have not applied a clock or any other information to our design. At this point, XPower is making calculations assuming that no signals are changing, that is, the FPGA is idle.

It takes more power to generate a clock and switch signals internal to the FPGA than it does to just sit idle. The power, therefore, is dependent on how frequently signals change. If there is no change, the chip is simply idle. In order to obtain any sort of power estimates, we must apply a clock and give some general information about the various types of signals in our design.

Click on the plus sign next to Data Views to expand the Data Views folder.

Next, expand the Types folder.

A list of signal types appear. Select Clocks.

Enter 25.00 in the mclk_BUFGP/IBUFG and press the Tab key. The others will automatically fill in.

The clock power and the inputs power changes accordingly.

5 Since we have applied a clock, there are signals changing in the FPGA and therefore more power is required than when the chip was idle. If you change the 25.00 MHz to other values, the power required will change. After experimenting with different clock frequencies, return the mclk to 25 MHz since that is what our design was configured for.

Now, we must estimate the activity rates of other signals such as inputs and internal signals. From the menubar, select Tools  Estimate Activity Rates. The data screen will show a list of all signals where we can enter the frequency at which each of these is likely to change.

This is where we enter the estimates for how frequently the inputs and internal signals will change.

For our example, the switches are constant and the buttons are only used for reset and “go” signals. Since no signals change frequently, this is the best estimate that we can make. Finally, click the Summary tab.

The total power is now estimated at 37.57 mW. This estimate is based solely on our inputs for how frequently signals change. When we estimated how frequently signals change, we had no way of estimating internal signals, etc… Estimating is only useful if your inputs are changing at or close to a certain frequency, otherwise it is not very accurate. So far, we estimate that the FPGA requires 37.00 mW to idle and to execute our transmit state machine it requires 37.57 mW.

Instead of estimating how frequently signals will change, XPower allows us to input a Variable Change Dump (VCD) file. This file contains how frequently signals change. Convenientally, we can save a waveform from a timing simulation using Aldec Active-HDL. Exit XPower, when prompted to save changes, you may answer NO since there is no reason to save our basic estimates. 6 At this point, we need to perform a timing simulation. In order to do so, we must generate a testbench. We will generate a testbench using the stimulators from the functional simulation waveform that we saved earlier. This means that the timing simulation will be for a 1.5 ms execution transmitting an “A5”.

The screenshot below reviews how to generate a testbench.

Expand the library in your design.

Right-click on the top-level component and select Generate TestBench…

This will start the testbench wizard.

Click Next on the first step. Click the checkbox next to the Test Vectors From File option and browse for the functional simulation waveform that we saved earlier, TXWaveForm.awf. Click Next to proceed.

Click Next and then Finish to complete the wizard.

7 Notice that the wizard created a new TestBench folder with a new .vhd file in it containing the top-level for the test bench, uart_tx_test_TB.vhd

Right-click on the new test bench top-level file and click Compile All with File Reorder to compile the test bench.

When it is finished, a green check mark will appear next to the .vhd file.

Now, select the Options for the Timing Simluation. Change the files and top-level to the test bench that you just generated. At first, the list will display the incorrect file and top level. Delete the incorrect file using the delete icon.

Then, click the Files icon and select the uart_tx_test_TB.vhd file from the list of files.

Then, click Choose to choose the top-level. Delete the old top level from the text box and select uart_tx_test_tb and click the Add button.

When you have completed these operations, the options will appear as shown.

Click OK.

Click the timing simulation icon from the design flow menu to launch the timing simulation. Run the simulation. 8 As expected, the timing simulation shows the “A5” sent out the TxD signal. If the timing simulation did not work properly, be sure:

1. The constraints file is correct and has been linked to the design using the Implementation Options to specify a custom .ucf file.

2. The correct files and top-levels have been set in the timing simulation options as shown in the diagram on the previous page.

Save the waveform as TXtiming.awf. This time, we will also save the waveform as a .VCD file to use with XPower. This .VCD file will contain information about every signal as it changes throughout execution. Using this file, we can obtain a more exact power value.

Select File ExportWaveforms. In the file dialog box, select VCD – Xilinx Xpower support (*.VCD) from the Save as type pull down list.

Then, use TXtiming as the file name and click Save.

You will be prompted with a dialog box, click the OK button to accept the dialog box.

9 From the Design Flow menu, click Analysis and select the options button for XPower.

Using the Browse button, select the .VCD file that we just saved from the timing simulation.

Click OK.

Click XPower from the Analysis menu to launch XPower.

XPower immediately computes the power based on the signals provided in the .VCD file.

Notice that the power required is 37.58 mW. This is up slightly from our previous estimate of 37.57 mW before we created the .VCD file. Although this is minor in this design, the difference may be major depending on the activity of the signals on the chip. For larger

10 designs, the power values obtained using an actual timing simulation are often necessary to obtain any meaningful power calculations.

According to XPower, this design requires 37.58 mW of power. Power is independent of time; it is the rate of change in energy. In order to compute the actual energy required (power over time), we must multiple the power times the time. For our design, the total energy required to send the 8 bits is given by:

37.58 mW x 1.5 ms = 56.37 micro-Joules

Part II: Altering the Clock Frequency

It is not necessary to run our transmitter at 25 MHz. In fact, most of the time is spent in a delay state. Alter the source for the uart_tx to use a bit_time for a 5 MHz clock:

--constant bit_time: STD_LOGIC_VECTOR (11 downto 0) := X"A28"; (25 MHz) constant bit_time: STD_LOGIC_VECTOR (11 downto 0) := X"206"; --(5 MHz)

Repeat the process using this new file:

1. Perform a functional simulation using the same stimulators except use a 5 MHz clock for mclk. Run the simulation for 1.5 ms and save the waveform as TXWaveform5.awf. 2. Synthesize and Implement the design again 3. Create a test bench use the vectors from the new waveform file TXWaveform5.awf. Compile the new test bench. 4. Run a timing simulation using this new test bench and save the waveform. Export the waveform as a .VCD file. 5. Set the XPower options to use this new .VCD file 6. Run XPower

What is the power required at 5 MHz? What is the energy required at 5 MHz?

Exapnd the Report Views folder and click on the reports to view a nicely formatted power report. Print this report and hand it in with this lab.