Results Status Report

ECE4006: Design Progress Report

Ashley Lee Shaun Rosemond 11/20/2001 After conducting the preliminary research, the basic functionality of the Agilent optomodule and its interface with the Intel Network Card was understood and thus improvements could be made to enable differential capabilities of the module. When reviewing the design, the functionality of all circuit components and their contribution to the overall performance of the transceiver module within the network card was comprehended. With the knowledge needed to implement the apparatus in differential mode, the next step stage in the project process is to test the implementation designed, and that is the focus of this paper. The topics discussed include the test setup used in the evaluation of the performance of the evaluation boards, the results obtained and how they compare to the IEEE 802.3z standard established for Ethernet data transfer, and the potential obstacles overcome and that led to the successful operation of the evaluation board and those that still persist concerning interface with the Intel network card.

Test Set up

A block diagram of the set up used to test the evaluation boards is shown in

Figure 1. It consists of a Tektronix TDS 694C Digital Oscilloscope, a Microwave Logic gigaBERT-1400 Tx Pattern Generator, a Microwave Logic gigaBERT-1400 DRx Bit

Error Tester, and the evaluation board designed to optimize the performance of the transceiver module. The set up was arranged such that the output signals of the pattern generator were sent to the transmit ports of the transceiver module (pins 7 and 8 of module); one of the receive signals from the module on the evaluation board was then sent to Channel 1 on the oscilloscope, and the inverted signal was connected via coaxial cable to the bit error tester, where it was then connected to Channel 2 on the oscilloscope

(pins 2 and 3 of module). Connected to Channel 3 on the oscilloscope was the clock of the pattern generator so it could be used as a triggering source when viewing the data stream waveforms on the oscilloscope. Finally, the fiber optic cable was connected optical cable ports on the transceiver module.

Evaluation Pattern Digital Board Generator Oscilloscope Rx Tx

Bit Error Tester

Figure 1. Block diagram of equipment utilized in test set up.

The configuration of the pattern generator was as follows: Initially, to verify the functionality of its design, it was set to produce a square wave with an amplitude 0.5V and a frequency set to 1GHz. Later the frequency was varied to determine error rates at higher data rates. Along with varied frequencies, the bit pattern was also varied to evaluate the performance of the evaluation board was the bit error tester used to measure the error rate in the data received from the transceiver module. It was initially set with a patent of 27-1, and it was later varied to 223-1. A patent is a set pattern of ones and zeros used by the bit-error tester to calculate the error rate during data transfer. Calculations of error rates at higher patents are more accurate because higher patents can catch errors that would elude lower patents at high data rates. IEEE Standard 802.3z

One significant mark of successful data transfer is an “eye pattern” between the superimposed images of the data waveforms from a transmitting source on an oscilloscope. According to the IEEE standard 802.3z for 1000BASE-LX receivers, the required transmitter pulse shape characteristics are specified in the form of a mask of the transmitter eye diagram shown in Figure 2:

Figure 2. IEEE standard eye mask.

Therefore, if that mask can be used to determine successful data transmission, it also verifies successful data at the receive end as well. The eye mask shown in Figure 2 is implemented using a fourth-order Bessel-Thompson filter and is defined as follows:

The eye formed from the superimposition of the data waveforms must have an opening with a width that is between 62.5 and 78 percent of the bit interval time, it must also have a normalized amplitude that can be as low as 20 percent (not preferred) or as high as 80 percent. The definition of this eye mask stated by the IEEE standard 802.3z must be applicable to the display of the received data from the transceiver to verify proper functionality and an eye with those characteristics defined by the eye mask is what is expected to be observed after testing the evaluation board.

Results

After preparing the equipment and arranging the set up as described, the equipment was run and the resulting output waveforms shown on the digital display of the oscilloscope are shown in Figure 3.

Figure 3. Eye diagram of received data.

Channels 1 and 2 of the oscilloscope are the inverted and non-inverted signals from the receiver output ports. The waveform on channel 3 is the clock from the pattern generator used to trigger the display on the oscilloscope. Preliminary observation shows that the eye diagram of the waveform on the oscilloscope display would easily encapsulate eye mask, thus proving superior functionality. If the knowledge of the mask was unknown however, a bit more detailed look at the eye would show that the eye opening was approximately 80 percent of the bit period, which is favorable characteristic for eye diagrams because it displays that the eye is in fact very wide and open.

In addition to the qualitative verification of the transceiver functionality provided by the eye mask being able to be inscribed in the eye diagram, quantitative results in the form of BER were also provided by the bit error tester. Table 1 shows the different bit error rates (BER) for different patterns and different frequencies created by the packet generator:

Table 1. Error rates (errors/sec) calculated by bit error tester

Bit Error Rate (BER) Pattern Frequency 0 at 10-11 27-1 1GHz 1.1*10-8 223-1 1.2GHz 6.8*10-6 223-1 1.4GHz

As displayed in the table, there were zero errors per 1011 bits in the transmitted data when transmitting at 1GHz, which means the transceiver topped out at zero errors in

100 seconds utilizing the 1GHz data rate. Then, the frequency was increased to 1.2 and

1.4GHz, and the pattern was varied to 223-1. Changing the pattern to this increased setting allows more accurate bit error rates to be calculated. The pattern is a set stream of ones and/or zeros inserted into the data stream when generating the data so that a known reference can be utilized when calculating the bit error. Increasing the pattern to 223-1 is appropriate because when operating at high data rates such as 1GHz or more, low patterns are not sufficient enough to handle high speeds; not only that, but higher patterns resemble more of the demanding applications found in data transmission today, and errors that are more noticeable which may be eluded in small patterns which makes it more efficient for testing the maximum performance of the transceiver. Ultimately, the eye diagram and the BER are directly related: The larger the opening of the eye the better

BER for data transfer.

Design Issues Encountered

Thus far, we have encountered a few design issues. First, a problem was discovered during initial testing. A signal was input to both differential inputs, and no output signal was detected. After eliminating testing equipment problems, the evaluation board was looked at. On the board, there are four holes for electronically connecting the top of the board to the bottom of the board. These are shown in Figure 4. Since the board uses both sides for signal transmission, they have to be connected. During our initial testing, the evaluation board had all four holes open. To solve this problem, we took short segments of wire from a resistor and soldered it across the holes. Figure 4. Diagram of Location of Veering Pins.

In addition, we wanted to make sure there were no other problems with the setup

on the board. Using a voltage meter and a power supply, the board was tested for power

connectivity across the power and supply paths on the board. It was discovered that both

power supply voltages were relatively zero volts. Since the top of the board needs to

carry the power supply voltage, the power supply leads need to be soldered to the top of

the board. In our board design, the power supply connector is soldered on the bottom

side of the board resulting in no connection to the top of the board. The power supply

connectors had to be unsoldered and replaced making sure that upon soldering, the solder

drips down to the top of the board for each pin connection. Upon solving this problem,

the power supply voltage from pin 1 to 5 and pin 6 and 9 on the optomodule was

relatively 5 volts.

Future Design Issues Our next design issue is going to be soldering a short wire from pin 4 of the optomodule to pin 4 on the Intel board. This pin is used for the Signal Detect for the optomodule. Further testing is still required to determine if this pin is in fact being used, but there is a high probability that it is. In this case, a small segment of coaxial cable will more than likely be used, with connectors removed from either end to connect pin 4 on the optomodule and Intel board. Since this wire is operating by itself, the shield will be left unconnected.

Upon soldering the coaxial cables to the Intel board, more needs to be done to prevent the soldered connections from breaking during handling. A likely solution will be to hot glue the coaxial cables to the extreme edge of the board, where the optomodule used to be. This has to be done so that it will be possible to remove the glue and the cables without destroying the board. Also, the gun used for hot gluing the cables to the board needs to be a low temperature gun to prevent damage of temperature sensitive chip devices on the Intel board. Overall, this solution seems to be the best given the durability and other issues discussed. With regard to temperature, soldering the coaxial cables to the board could pose problems because of the high temperatures used for soldering. To prevent damage to the chip components on the Intel board, the temperature of the soldering iron must be turned down to around 4000 C and cannot be touched to the surface for a prolonged amount of time.

Next, the Intel board poses several problems that will be encountered. There are terminating resistors for the transmission lines on pins 7 and 8 of the optomodule. Since the transmission lines will be terminated directly before the optomodule, these four resistors will be removed from the Intel board. On the receiver side of the optomodule, pins 2 and 3, bias resistors are located on the Intel board and the evaluation board. These resistors will need to be removed from the Intel board for the circuit to work. The removal of all resistors will not affect the performance of the circuit because these resistors are connected to ground. On receive and transmit channels, there are .01μF capacitors along the transmission lines. Since these capacitors likely pose no problems, and it might be difficult to remove and short the connections, these capacitors will be left in place. If further testing dictates the removal and shorting of these connections, then methods will be sought to remedy the problem. On the SD pin, the evaluation board does not contain resistors to bias the lines, but the Intel board does contain the resistor necessary for this operation. Also, after using the short segment of wire, the line will become a transmission line. We are assuming that the circuitry used to perform the termination on pins 2 and 3 will also be present on pin 4.

Conclusion

Thus far, the results that have been obtained are the eye diagrams and the bit error rates. Running at frequencies in excess of 1 GHz, the eye diagrams and bit error rates proved to be very satisfactory. The eye diagrams showed a very open eye, and the bit error rates of 1.1*10-8 and 6.8*10-6 are error rates of 1 error every million bits. With forward error correction, these error rates could actually be much greater such as close to

10-4. The next part of the experiment involves connecting the evaluation board to the

Intel board and putting it into a computer. After this setup begins to work in the computer, connectivity tests will be run and bit error rates will be tested here as well.

Finally, our Gigabit Ethernet card will be connected to an original Intel Gigabit Ethernet card, and data will be send across the channel. The problems encountered thus far have been minimal and have been solved rather quickly. Completion of the project will be determined by the complexity of the problems presented above and our ability to quickly provide a solution.

Resources

Introduction to Gigabit Ethernet http://www.cisco.com/warp/public/cc/techno/media/lan/gig/tech/gigbt_tc.htm

IEEE Std 802.3, 1998 Edition Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical http://gtel.gatech.edu:2172/search97/s97is.vts? Action=Search&SearchPage=VSearch.htm&ResultTemplate=Toc_Result.hts&ViewTem plate=lpdocview.hts&queryText=(isnumber15560)&collection=stds&SortFiel d=hpag&SortOrder=desc&ResultCount=15

Eye Diagrams http://www.samsungelectronics.com/fiberoptics/downloads/tr851sa.pdf http://www.rfpowernet.com/pdfs/AN_Datacom.pdf

10-Gigabit Ethernet Alliance http://www.10gea.org/tech-faqs.htm

10-Gigabit Ethernet Alliance Technology Overview White Paper http://www.10gea.org/10GEA_Whitepaper_0901.pdf