Describing Entity in Terms of Its Subcomponents and How They Are Connected

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Structural Modeling

Describing entity in terms of its subcomponents and how they are connected. Hierarchical arrangement of interconnected components. Ports and their interconnection are central focus. Has to be supported at some level by behaviorial description.

Structural Steps Component Declaration Component Specification Component Instantiation

1.1 Component Declaration

 Describes local interface name ports and generics  Appears in declarative areas.  Format: COMPONENT identifier_name [GENERIC(local_generic_list);] [PORT(local_port_list);] END COMPONENT;

Example:

COMPONENT and2 PORT(a,b: IN std_logic;c: OUT std_logic); END COMPONENT;

1.2 Component Specification

 Identifies which design entity is to be used as component.  States: name of entity name of architecture  Format: FOR component_instantiation_label:component_name USE binding_indication;  Binding_indication: ENTITY library.entity_name[(architecture_name)]

Example: FOR U1: and2 USE ENTITY work.and_gate(behav);

1.3 Component Instantiation

 Places component in relationship to other components.  Identifies signals connected to component ports.  Associates values to generics.

1  Format: label: component_declaration_name --label required [GENERIC MAP (association_list)] -- Note no ";" [PORT MAP (association_list)];

Example: u2: and2 PORT MAP(signal1,signal2,signal3);

1.4 Structural Example

Specification :

Create model of entity with three input ports(a,b,c) and one output port (d). Signals a and b are ANDed and the result(x) is ORed with signal c to produced output signal d.

a x U1 b U2 d c

Analysis:

Two components will be declared, specified, and instantiated. One for the and_gate and the other for the or_gate. In addition an internal signal x which represents the output of the and_gate and input of the or_gate will be declared.

--Module 1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY and_gate IS PORT(x,y: IN STD_LOGIC; z: OUT STD_LOGIC); END and_gate;

ARCHITECTURE behav OF and_gate IS BEGIN z <= x AND y; END behav;

--Module 2

2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or_gate IS PORT(x,y: IN STD_LOGIC; z: OUT STD_LOGIC); END or_gate;

ARCHITECTURE behav OF or_gate IS BEGIN z <= x OR y; END behav;

--Module 3

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY my_thing IS PORT (a,b,c: IN STD_LOGIC;d: OUT STD_LOGIC); END my_thing;

--Structural modeling using position association

ARCHITECTURE structure OF my_thing IS COMPONENT and2 PORT(x,y: IN STD_LOGIC; z: OUT STD_LOGIC); END COMPONENT and2;

COMPONENT or2 PORT(x,y: IN STD_LOGIC; z: OUT STD_LOGIC); END COMPONENT or2;

FOR u1: and2 USE ENTITY work.and_gate(behav); FOR u2: or2 USE ENTITY work.or_gate(behav);

SIGNAL x: STD_LOGIC; BEGIN u1: and2 PORT MAP(a,b,x); --position association u2: or2 PORT MAP(x,c,d); --position association END structure;

--Another structural modeling using name association

ARCHITECTURE structure2 OF my_thing IS COMPONENT and2 PORT(In1,In2: IN STD_LOGIC; Out1: OUT STD_LOGIC); END COMPONENT and2;

COMPONENT or2 PORT(In1,In2: IN STD_LOGIC; Out1: OUT STD_LOGIC); END COMPONENT or2;

FOR u1: and2 USE ENTITY work.and_gate(behav); FOR u2: or2 USE ENTITY work.or_gate(behav);

3 SIGNAL x: STD_LOGIC;

BEGIN u1: and2 PORT MAP(a=>In1,b=>In2,x=>Out1); --name association u2: or2 PORT MAP(x=>In1,c=>In2,d=>Out1); --name association END structure2;

Simplorer Structural Modeling steps.

Component Declaration is not required, since each existing model has an embedded component declaration in package.

and21 or21 vec vec1 AND2 vec OR2 vec2

vec vec3

Analysis:

The following components are located in the DIGITAL library:

ENTITY and2 IS GENERIC (TP_LH : REAL := 0.0; TP_HL : REAL := 0.0); PORT (x1,x2 : IN BIT := '0'; y : OUT BIT := '0'); END ENTITY and2;

ARCHITECTURE behav OF and2 IS CONSTANT lh : TIME := TP_LH * 1 sec; CONSTANT hl : TIME := TP_HL * 1 sec; SIGNAL AND_OUT : BIT; BEGIN AND_OUT <= x1 AND x2 ; Y <= AND_OUT AFTER hl WHEN AND_OUT = '0' ELSE AND_OUT AFTER lh; END behav;

ENTITY or2 IS GENERIC (TP_LH : REAL := 0.0; TP_HL : REAL := 0.0);

4 PORT (x1,x2 : IN BIT := '0'; y : OUT BIT := '0'); END ENTITY or2;

ARCHITECTURE behav OF or2 IS CONSTANT lh : TIME := TP_LH * 1 sec; CONSTANT hl : TIME := TP_HL * 1 sec; SIGNAL OR_OUT : BIT; BEGIN OR_OUT <= x1 OR x2 ; y <= OR_OUT AFTER hl WHEN OR_OUT = '0' ELSE OR_OUT AFTER lh; END behav;

ENTITY vec IS GENERIC (ton : REAL := 0.0; toff : REAL := 0.0); PORT (SIGNAL s_val : OUT BIT); END ENTITY vec;

ARCHITECTURE behav OF vec IS CONSTANT ton_period : TIME := 1 sec*ton; CONSTANT toff_period : TIME := 1 sec*toff; BEGIN PROCESS BEGIN s_val <='0'; WAIT FOR toff_period; s_val <= '1'; WAIT FOR ton_period; END PROCESS; END ARCHITECTURE behav;

and_or1

vec vec1 and_or

vec vec2

vec vec3

LIBRARY DIGITAL; ENTITY and_or IS PORT(SIGNAL a, b, c:IN BIT; SIGNAL d:OUT BIT); END ENTITY and_or;

ARCHITECTURE behav OF and_or IS SIGNAL x: BIT; BEGIN U1: ENTITY DIGITAL.and2(behav) GENERIC MAP(TP_LH=>0.0, TP_HL=>0.0) PORT MAP(x1=>a, x2=>b,y=>x); --name association

U2: ENTITY DIGITAL.or2(behav)

5 GENERIC MAP(TP_LH=>0.0, TP_HL=>0.0) PORT MAP(x1=>x, x2=>c,y=>d); --name association

END ARCHITECTURE behav;

ARCHITECTURE pos OF and_or IS SIGNAL x: BIT; BEGIN U1: ENTITY DIGITAL.and2(behav) GENERIC MAP(TP_LH=>0.0, TP_HL=>0.0) PORT MAP(a, b, x); --position association

U2: ENTITY DIGITAL.or2(behav) GENERIC MAP(0.0, 0.0) PORT MAP(x, c, d); ----position association

END ARCHITECTURE pos;

1.2 vec1.s_val

0.8 0.6 0.4 0.2

-0.2 00.2m 0.6m 1m 1.4m 2m t [s]

1.2 vec2.s_val 0.8 0.6 0.4 0.2 -0.2 00.2m 0.6m 1m 1.4m 2m t [s]

1.2 vec3.s_val

0.2 -0.2 00.2m 0.6m 1m 1.4m 2m t [s]

6 1.2 and_or1.d

0.8 0.6 0.4 0.2

-0.2 0 0.2m 0.6m 1m1.2m 1.6m 2m t [s]

1.5 Behavioral, Data Flow, and Structural Modeling Example

A VHDL data flow description and a register transfer language description are similar in that they describe the function of a design by defining the flow of information from one input or register to another register or output.

A data flow description uses a large number of concurrent signal assignment; concurrent statements used in data flow descriptions include the following:

 BLOCK statement  Concurrent PROCEDURE call  Concurrent ASSERT statement  Concurrent SIGNAL assignment statement

The given circuit will be described using behavioral, data flow and structural. a o1 U1 b o3 U3 U4 e c U2 d o2

ENTITY my_ckt IS PORT( a, b, c, d : IN STD_LOGIC ; e : OUT STD_LOGIC); END my_ckt;

1.5.1 Behavioral Modeling Architecture of my_ckt

ARCHITECTURE behavior OF my_ckt IS BEGIN

7 e <= NOT((a AND b) OR (c AND d)); END behavior;

1.5.2 Data Flow Modeling Architecture of my_ckt

ARCHITECTURE dataflow OF my_ckt IS SIGNAL o1, o2, o3 : STD_LOGIC; --specify internal signals or wires BEGIN e <= NOT o3; o1 <= a AND b; o2 <= c AND d; o3 <= o1 OR o2; END dataflow;

1.5.3 Structural Modeling Architecture of my_ckt

ARCHITECTURE structural OF my_ckt IS COMPONENT and2 PORT(a, b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT and2;

COMPONENT or2 PORT(a, b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT or2;

COMPONENT inv PORT(a : IN STD_LOGIC; b : OUT STD_LOGIC); END COMPONENT inv;

SIGNAL o1, o2, o3: STD_LOGIC; FOR U1, U2 : and2 USE ENTITY work.and_gate(behav); FOR U3: or2 USE ENTITY work.or_gate(behav); FOR U4: inv USE ENTITY work.inv(behav);

BEGIN U1: and2 PORT MAP(a, b, o1); U2: and2 PORT MAP(c, d, o2); U3: or2 PORT MAP(o1, o2, o3); U4: inv PORT MAP(o3, e); END structural;

1.6 Test Bench Example

8 nand2_tb U1 U2 nand2_test nand2 a a a c c b b b

ENTITY nand2 IS PORT(a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END ENTITY nand2;

ARCHITECTURE arch_nand2 OF nand2 IS BEGIN c <= a NAND b; END ARCHITECTURE arch_nand2;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ------entity nand2_test is port (a,b:out std_logic; c:in std_logic); end nand2_test; ------architecture behav of nand2_test is begin test_process: process is begin a<='1'; b<='1'; wait for 1 ns; assert (c='0') report "Not Working" severity error;

wait for 10 ns; a<='0'; b<='1'; wait for 1 ns; assert (c='1')

9 report "Not Working" severity error;

wait for 10 ns; a<='1'; b<='0'; wait for 1 ns; assert (c='1') report "Not Working" severity error;

wait for 100 ns; end process test_process; end behav;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity nand2_tb is end nand2_tb; ------architecture behav of nand2_tb is component nand2 port (a,b:in std_logic; c:out std_logic); end component; component nand2_test port (a,b:out std_logic; c:in std_logic); end component; for U1:nand2_test use entity work.nand2_test(behav); for U2:nand2 use entity work.nand2(arch_nand2); signal a, b, c:std_logic; begin U1: nand2_test port map(a, b, c); U2: nand2 port map(a, b, c); end behav;

Simplorer Implementation of gate_tester

nand2_test1 nand21

gate_tester NAND2

10 ENTITY nand2_test IS port (a,b:out BIT;--change to BIT to make it compatible with gate input data type c:in BIT); END ENTITY nand2_test;

ARCHITECTURE behav OF nand2_test IS BEGIN test_process: process is begin a<='1'; b<='1'; wait for 1 ns; assert (c='0') report "Not Working" severity error;

wait for 100 ns; end process test_process;

1.2 nand2_test1.a

0.2 -0.2 0 5n 10n 15n 20n 25n 30n 35n 40n t [s]

11 1.2 nand2_test1.b 0.8 0.6 0.4 0.2 -0.2 0 5n 10n 15n 20n 25n 30n 35n 40n t [s]

1.2 nand21.y 0.8 0.6 0.4 0.2 -0.2 0 5n 10n 15n 20n 25n 30n 35n 40n t [s]

When nand2 gate is replaced by or2 gate, simulated does not work. There is no means of displaying theassert statements. The simulation simply abort.

REFERENCES

1. “Analog and Mixed-Signal Modeling Using the VHDL-AMS Language”, E.C. Beaverton et.al., 36th Design Automation Conference, New Orleans, June 21-25, 1999. 2. “Simulation System SIMPLORER VHDL-AMS Tutorial,” English Edition, © 2003 Ansoft Corporation. 3. Simulation System SIMPLORER® v.6.0 User Manual, English Edition, © 1996-2002, Ansoft Corporation.