School of Computing, Engineering and Mathematics

SCHOOL OF COMPUTING, ENGINEERING AND MATHEMATICS SEMESTER 2 EXAMINATIONS 2011/2012

DIGITAL ELECTRONICS EO128 C.S. KNIGHT & DR. S.C. BUSBRIDGE

Time allowed: TWO hours

Answer: Answer ALL FIVE questions Each question carries 20 marks This is a CLOSED-BOOK examination

Items permitted: Any approved calculator

Items supplied: Data sheet for CD74HCT112 Data sheet for CD74HCT283

Marks for whole and part questions are indicated in brackets ( )

May/June 2012 Page 1 of 6 Question 1

(a) Explain briefly what is meant by the terms combinational logic and truth table when applied to digital electronic systems. (4 marks)

(b) This part of the question refers to the following logical expression:

Z  A  BC  AB

(i) Draw a circuit diagram to directly implement the above expression.

(4 marks)

(ii) Use Boolean algebra to show how the circuit could be simplified.

(6 marks)

(iii) Use Boolean algebra (including if necessary De Morgan’s theorem) to simplify the expression to one involving just a single quad dual-input NOR gate chip. (6 marks)

Question 2 commences on the next page

EO128 (2011/2012) Page 2 of 6 Question 2

(a) Explain briefly the terms synchronous, asynchronous, active low and active high when applied to sequential logic systems. (4 marks)

(b) (i) Write down the truth table for a JK flip flop. Hence show how it is possible to derive the functions of a D-type and a T-type flip flop from a JK flip flop. (4 marks)

(ii) Show, with the addition of extra gates, how it would be possible to obtain the functions of a JK flip flop from a D-type flip flop. (6 marks)

(c) The waveforms shown in Fig. Q2.1 are applied to various inputs of a CD74HCT112 flip flop (J and K are permanently connected to Vcc).

Show, on the same time scale for t > 0 s, the waveform of the Q output.

(6 marks)

Figure Q2.1

(a) Draw up a truth table for a single-bit full adder. Hence derive the minimised equations for the ‘sum’ and ‘carry’ outputs. (8 marks)

(b) Draw a diagram showing how one single-bit half-adder and three single-bit full adders may be connected to produce a 4-bit full adder. (6 marks)

(c) A data sheet for the CD74HCT283 4-bit binary full adder is supplied.

Draw a diagram showing how two of these integrated circuits (IC) may be connected to form an 8-bit full adder (that does not receive a carry from a previous stage). Ensure that all inputs to, and outputs from each IC are clearly labelled.

(6 marks)

Question 4 commences on the next page

Part of a mixed-voltage digital system contains a 74HCT112 integrated circuit (IC) – a data sheet is supplied. The power supply to this IC is 2 V and the circuit drives a TTL load.

(a) For this IC, determine the following:

(i) The minimum voltage for a logic '1' output. (1 mark) (ii) The worst-case noise margin. (3 marks) (iii) The maximum output sink current for a logic ‘0’ output. (1 mark)

(iv) What is the maximum temperature under which this IC can operate?

(1 mark)

(b) The output of one of the flip-flops is to be connected to an input of an IC that runs from a 6 V power supply. Name the type of digital output that could be used to implement the interface between these two ICs. Explain the principles of operation of the interface and draw a diagram to illustrate your answer.

(7 marks)

(c) Explain what is meant by the term ‘tristate’ with respect to a digital output. Draw the circuit symbol for a tristate inverting buffer and explain its function. Under what circumstances might this type of device be used? (7 marks)

A self-starting, synchronous, mod-10 down counter is to be designed using T-type flip-flops with appropriate additional combinational logic for the feedback circuitry.

(a) Draw up a full state diagram for this function. (6 marks)

(b) Hence produce a state table and derive minimised equations for the flip-flop inputs. Note that a circuit diagram is NOT required. (14 marks)

EO128 (2011/2012) Page 6 of 6