<p>s</p><p>SCHOOL OF COMPUTING, ENGINEERING AND MATHEMATICS SEMESTER 2 EXAMINATIONS 2011/2012</p><p>DIGITAL ELECTRONICS EO128 C.S. KNIGHT & DR. S.C. BUSBRIDGE</p><p>Time allowed: TWO hours</p><p>Answer: Answer ALL FIVE questions Each question carries 20 marks This is a CLOSED-BOOK examination</p><p>Items permitted: Any approved calculator</p><p>Items supplied: Data sheet for CD74HCT112 Data sheet for CD74HCT283</p><p>Marks for whole and part questions are indicated in brackets ( )</p><p>May/June 2012 Page 1 of 6 Question 1</p><p>(a) Explain briefly what is meant by the terms combinational logic and truth table when applied to digital electronic systems. (4 marks)</p><p>(b) This part of the question refers to the following logical expression:</p><p>Z  A  BC  AB</p><p>(i) Draw a circuit diagram to directly implement the above expression.</p><p>(4 marks)</p><p>(ii) Use Boolean algebra to show how the circuit could be simplified.</p><p>(6 marks)</p><p>(iii) Use Boolean algebra (including if necessary De Morgan’s theorem) to simplify the expression to one involving just a single quad dual-input NOR gate chip. (6 marks)</p><p>Question 2 commences on the next page</p><p>EO128 (2011/2012) Page 2 of 6 Question 2</p><p>(a) Explain briefly the terms synchronous, asynchronous, active low and active high when applied to sequential logic systems. (4 marks)</p><p>(b) (i) Write down the truth table for a JK flip flop. Hence show how it is possible to derive the functions of a D-type and a T-type flip flop from a JK flip flop. (4 marks)</p><p>(ii) Show, with the addition of extra gates, how it would be possible to obtain the functions of a JK flip flop from a D-type flip flop. (6 marks)</p><p>(c) The waveforms shown in Fig. Q2.1 are applied to various inputs of a CD74HCT112 flip flop (J and K are permanently connected to Vcc).</p><p>Show, on the same time scale for t > 0 s, the waveform of the Q output.</p><p>(6 marks)</p><p>Figure Q2.1</p><p>EO128 (2011/2012) Page 3 of 6 Question 3</p><p>(a) Draw up a truth table for a single-bit full adder. Hence derive the minimised equations for the ‘sum’ and ‘carry’ outputs. (8 marks)</p><p>(b) Draw a diagram showing how one single-bit half-adder and three single-bit full adders may be connected to produce a 4-bit full adder. (6 marks)</p><p>(c) A data sheet for the CD74HCT283 4-bit binary full adder is supplied.</p><p>Draw a diagram showing how two of these integrated circuits (IC) may be connected to form an 8-bit full adder (that does not receive a carry from a previous stage). Ensure that all inputs to, and outputs from each IC are clearly labelled.</p><p>(6 marks)</p><p>Question 4 commences on the next page</p><p>EO128 (2011/2012) Page 4 of 6 Question 4</p><p>Part of a mixed-voltage digital system contains a 74HCT112 integrated circuit (IC) – a data sheet is supplied. The power supply to this IC is 2 V and the circuit drives a TTL load.</p><p>(a) For this IC, determine the following:</p><p>(i) The minimum voltage for a logic '1' output. (1 mark) (ii) The worst-case noise margin. (3 marks) (iii) The maximum output sink current for a logic ‘0’ output. (1 mark)</p><p>(iv) What is the maximum temperature under which this IC can operate?</p><p>(1 mark)</p><p>(b) The output of one of the flip-flops is to be connected to an input of an IC that runs from a 6 V power supply. Name the type of digital output that could be used to implement the interface between these two ICs. Explain the principles of operation of the interface and draw a diagram to illustrate your answer.</p><p>(7 marks)</p><p>(c) Explain what is meant by the term ‘tristate’ with respect to a digital output. Draw the circuit symbol for a tristate inverting buffer and explain its function. Under what circumstances might this type of device be used? (7 marks)</p><p>EO128 (2011/2012) Page 5 of 6 Question 5</p><p>A self-starting, synchronous, mod-10 down counter is to be designed using T-type flip-flops with appropriate additional combinational logic for the feedback circuitry.</p><p>(a) Draw up a full state diagram for this function. (6 marks)</p><p>(b) Hence produce a state table and derive minimised equations for the flip-flop inputs. Note that a circuit diagram is NOT required. (14 marks)</p><p>EO128 (2011/2012) Page 6 of 6</p>