Comparative Study of Noise Performance in Single and Double Gate Nano Scale SOI Mosfets

Comparative Study of Noise Performance in Single and Double Gate Nano Scale SOI MOSFETs Using SILVACO TCAD. Indra Vijay Singh and M.S Alam Department of Electronics Engineering, Z.H. College of Engineering & Technology, Aligarh Muslim University Aligarh, U.P India.- 202002. Email: [email protected]

In this paper the noise performance of sigle Abstract: enhances the immunity towards the short channel eﬀects gate and double gate nano scale Silicon- on – Insulator (SOI) MOSFET is compared using SILVACO TCAD. (SCEs) and provides an almost ideal sub-threshold slope It is observed that the significant improvement in the [5]. noise figure (N.F) in double gate structure, also obeserved that the subthreshold behavoiur is much improved in double gate SOI MOSFET with a slope S However, these advanced structures = 69 mv/dec. presence of P type impurity in the channel perceptibly shifts the transfer characteristics and have distinctly different material is and process degrade the drive current Ion by 6%. technology requirements and associated challenges. 1. INTRODUCTION Metallic gate electrodes will be necessary in order for these devices to provide the maximum performance

Excellent high- frequency behavior, benefit over bulk-Si MOSFETs. together with a reduced influence of hot carriers and Several theoretical, process and physics-based short – channel effects have been claimed for Silicon-on- Insulator (SOI) MOSFETs, thus analysis have been reported related to short channel becoming the mainstream alternative to bulk silicon effects observed on the DC properties of the devices MOSFETs devices [1]. In particular, the analysis of the noise performance of the transistors is critical in [6,7], the limitation or degradation of the high frequency order to develop low-noise applications with a reduced cost. Simulation tools are the best solution and noise Characteristics along the down-scaling of the to carry out this study, thus helping to further channel length has not been described widely .In this develop silicon technologies. paper, the Small signal and RF noise properties of up-to- The use of low power, low noise devices date and up- coming SOI MOSFETs will be discussed at for future electronic applications is becoming more and the theoretical point of view. Accurate compact more important. Especially, SOI devices are excellent modeling of noise is a prerequisite for RFCMOS circuit candidates to become an alternative to conventional bulk design [7–8]. CMOS. Advanced MOSFET structures such as ultra Hence, in this paper we present a thin-body silicon-on-insulator (SOI) single-gate analytical method for RF and noise modeling including transistor and the double-gate (DG) transistor can be short channel effects. In The first section, the DC, RF and scaled more aggressively than the bulk Si structures [1– high frequency noise Model is presented. The model is 4], hence, may be adapted for IC production. A fully based on the concept of channel segmentation. In the depleted double gate (DG) silicon-on-insulator (SOI) is second, section the high frequency performances are regarded as a near ideal technology, offering a higher analyses through the use of analytical expressions of the drive current than its single gate (SG) counter part due to cut-off frequency fT and Maximum frequency of larger control over channel region, and this strongly

1 max [7]The time step between two solutions of oscillation f ; some trends related to their variations Poisson’sequationis = 0.2 fs. The instantaneous t along the down scaling will be provided. In the third section, the noise terminal currents are Calculated on the basis of the properties of the devices are discussed. Special Ramo-Shockley theorem which has been proved to be attention is paid to figure out how a DC tunneling gate leakage current, due to decrease of the oxide correct for time-varying electrode potentials [8].The thickness, might influence the small signal technique described by Babiker etal is used here [8].The properties as well as the noise performance of MOSFETs. Accurate compact modeling of induced noise and RF analysis is performed as follows. First, the gate noise is a Prerequisite for RFCMOS circuit design. Existing models under estimate the induced spectral densities of current fluctuations are extracted gate noise for short-channel devices. The model from instantaneous terminal currents computed for 250 accurately describes noise without fitting any additional parameters. ps in steady-state regime. Second, the response to a step The present work described the voltage successively applied to VGS and VDS is analyzed comparative study of noise in single gate and double gate nano scale SOI MOSFETs for radio frequency to extract Yij(ω) parameters by fourier decomposition of applications, such as a low noise amplifier, power transient currents [7].The equivalent circuit components amplifier and modulator. may be then deduced together the noise parameters as 2. DEVICE DESIGN the noise figure NF. PARAMETERS

The atomistic approach developed to treat the electron-ion interaction in the presence of discrete impurities was presented previously [4]. It has been successfully used to calculate the Electron mobility in Si resistors versus average doping and to Study the effect of impurity position in the channel of 50 nm bulk- MOSFETs [5]. The inﬂuence of atomistic doping on carrier transport and noise in nano-resistors has been Fig.1 Schematic view of simulated SGMOS and G Si OX tackled too[6]. DGMOS with L =60nm, Lch =50nm, T = 15nm, T The simulated devices (Fig.1) consist =3 nm, and W = 30nm. of ultra-thin SG and DG transistors with 17 nm long 3. SIMULATION unintentionally doped Channel (called SG1 and DG1, RESULTS respectively). They operate With mid gap gate material and power supply VDD =1V. Source/ channel and Figure2 shows the transfer channel/drain junctions are assumed to be abrupt with characteristics ID-VGS of simulated devices at VDS =1V. 19 −3 The SG1 device exhibits quite Poor subthreshold continuous doping of 5×10 cm in S/D regions. characteristics because of too small form factor Lch/TSi However, we consider the possible presence of a single = 3. 4 to effectively control short-channel effects. The subthreshold behaviour is much better in DG1 and residual P type impurity in the channel of a DG- DG2 with a slope S = 69mV/dec.The presence of a single P type impurity in the channel perceptibly shifts MOSFET called DG2. The position of this impurity is the transfer characteristics and degrades the drive chosen so as to have the maximum effect on the drain current Ion by 6%.We compare in Fig.3 the velocity proﬁle along a line going through the impurity (DG2, current, i.e.5.25nm from the source-end of the channel

2 solid line) with the profile along A line with out structures arise when comparing the induced impurity (DG1, dashed line). The impurity being fluctuations in the gate current: the fluctuations are located near the source-end of the channel, the consistently higher in the double Gate structure. In injection velocity is strongly affected, which is strong contrast with this, we found a better global consistent with the current degradation. noise performance in the DG structure (see Fig.5). The Noise Figure (NF) is lower in the DG structure. This can be explained in terms of the cross correlation coefficient (C) between gate and drain terminals (Equation1). C exhibits higher values in the DG structure for the same level of DC current and the same frequency.

Fig.2 ID-VGS characteristics of SG1, DG1 and DG2 at VDS = 1V.

Fig.3 Electron velocity in the channel for DG1 (no Fig.4 Comparison of the spectral densities of current impurity, dashed line) and DG2 (solid line) along a ﬂuctuations for the drain current (a) and the gate line going through the impurity located in XI =5.25nm. current (b) in SG1 and DG1.

In spite of the steadily increasing level of gate currents as the transistor’s dimensions shrink the global noise performance remains governed by the fluctuations of the carrier velocity in the channel if the device operates beyond the weak inversion region ;i.e. for VGS >VT. In this section we present the preliminary results on thermal noise calculation for the above presented structures operating at a given drain bias (VDS =1V). In Fig.4 we plot the spectral densities of the drain and Gate current fluctuations (Sid and Sig, respectively) for three sets of gate bias providing nearly the same levels of DC drain Current in both SG1 and DG1. It can be observed that at given DC Fig.5 Noise figure versus frequency in SG1 and DG1. current the SG structure exhibits only slightly higher values of the Sid .The main differences between both

3 Fig.6 Comparison of (a) Sid and (b) Sig in DG1 (1) and DG2.

The impact of the presence of a single impurity in the Channel (structure DG2) on the noise behavior is presented In Fig.6 and 7. The influence of the undesired impurity is clearly less pronounced on Sid than on Sig. The impurity modifies the fluctuations of the drain current through the action on the carrier mobility in the channel and this effect is mitigated as the current is increased since the greater amount of carriers in the channel tends to screen the impurity. Nevertheless this picture changes if we consider Sig. The action of the channel’s charge on the gate electrode is carried out through a capacitive coupling and the presence of a fixed charged impurity greatly Fig.7 Noise figure versus frequency in DG1 and DG2. enhances the fluctuations of the gate current. 4. CONCLUSION Figure7 presents the NF variation with the frequency in DG1 and DG2. It clearly shows that the presence of the impurity modifies the dependence of In this paper, the DC, RF the NF on the DC drain Current (i.e. the gate bias). and noise properties of DG and SG SOI MOSFETs Where as that in DG1 the NF in-creases with the drain have been described. Asystematic analysis technique current ,in DG2 we find that the NF decreases in the for the two structures is presented based on surface same range of drain current. potential formalism and the channel segmentation technique for small-signal and noise analysis. The noise performance of double-gated and single-gated MOSFETs is compared. We found a noticeable improvement of the noise figure in the DG structure that is explained interns of a favorable increase of cross-correlation between the Drain and gate currents. Finally, we show that the presence of A residual undesired charged impurity in the channel of a DG Structure induces perceptible changes in the spectral density Of the gate current fluctuations that modifies the noise figure REFERENCES

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