Several Multi-Purpose (40 Bit) and Function Specific Registers

TMS320C31 Architecture

 Several multi-purpose (40 bit) and function specific registers

 2K words (32-bit) of internal or on-chip memory 24  2 or 16 million words of addressable memory containing program, data, and input/output space

 Modified Harvard architecture

 Allows for four levels of pipelining and concurrent access to program and data memory.

 Single cycle multiplier/accumulate (MAC) function for fast and efficient operations.

 One serial port

 40-ns instruction cycle time, provides for 50 million floating-point operations per second (MFLOPS) or 25 million instructions per second (MIPS)

 Seven internal busses for program and data

CPU Registers 2.2

1. R0-R7: eight 40-bit registers that allow for extended-precision results; can store 32-bit integer and 40-bit floating-points numbers 2. AR0-AR7: eight general-purpose auxiliary registers commonly used for indirect memory addressing 3. IR0 and IR1: used for address indexing 4. ST: indicates status of the CPU 5. SP: system stack pointer, contains the address of the top of the stack 6. BK: to specify the block size of a circular buffer 7. IE, IF, and IOF: interrupt enable, interrupt flag, and I/O flag, respectively 8. RC: specifies repeat count for executing a block of code 9. RS and RE: block code starting and ending addresses, respectively 10. PC: program counter contains the address of the next instruction to be fetched 11. DP: specifies one of 256 data pages, each page with 64K words

Memory Space 2.3

 RAM block 0 and RAM block 1 each contains 1K words (32-bit) of on-chip memory

 Starting address of internal memory RAM block 0 is 0x809800

 Starting address of internal memory RAM block 1 is 0x809C00

 Last 256 (0xFF) internal memory locations of the C31 on the DSK board are used for the communications kernel and vectors, only address 0x809C00 to 0x809EFF are available when using the DSK.

 The DSK initializes the DSP in the Microcomputer/bootloader mode and loads the programs directly into memory via an interface to the parallel port on your PC.

Addressing Modes 2.4

Indirect Addressing - addressing with displacement and indexing

Registers ARn, n = 0, 1, ...,7 represent the eight general-purpose auxiliary registers AR0- AR7 commonly used to specify or point to memory addresses.

*ARn : the * symbol denotes the content in memory with the address specified or pointed by ARn.

*ARn++(d) : same as above except after the value in that memory location is fetched, ARn is postincremented by d (d is an 8-bit unsigned integer). A double minus (--), instead of double plus, would update or postdecrement ARn

*++ARn(d) : same as above except after the value in that memory location is fetched, ARn is preincremented by d (d is an 8-bit unsigned integer). A double minus (--), instead of double plus, would update or predecrement ARn

*++ARn(IRn) :The index registers IR0 and IR1 can be used as the displacement .

*ARn++(d)% : Same as above cases except that the modulus operator % (modulo arithmetic) represents a circular mode of addressing. After ARn reaches the bottom or 2.5 higher-address of a circular buffer, it will then point to the top address of that circular buffer when incremented next. Must initialize memory address to start on addresses that are multiples of 2^n (size of buffer < 2^n) and set up the BK register with the size of circular buffer.

*ARn++(IR0)B : similar to above cases except that the B designates a bit-reversal process. This bit-reversal process with a reverse carry allows the necessary resequencing of data in an FFT algorithm.

Direct Addressing - Data address is formed by the concatenation of the 8 least significant bits of the DP register and the least 16 significant bits of the instruction word.

Example LDP @0x80, DP ; Load Data Page register ADDI @0x009802,R0 ;Add integer at 809802h to value in R0

The symbol @ represents direct addressing Assembler Directives 2.6

Assembler directives such as .set begin with a period. An assembler directive is a message for the assembler and is not an instruction.

The starting addresses of different sections can be specified with assembler directives, thereby eliminating the need for a linker:

.include "prog1.asm" .start ".text",0x809900 .start ".data",0x809C00 LENGTH .set 32

A source file prog1.asm is "included" The text and the data sections start in memory locations 0x809900 and 0x809C00, respectively. The label LENGTH is set to 32.

.include "prog.asm" ;to include the source file prog.asm A .set 5 ;A is set to the value 5 2.7

B .word k ;B is initialized to the 32-bit integer value k C .float k ;C is initialized to the 32-bit floating-point value k .text ;to assemble into program memory section, ; equivalent to .sect ".text" .data ;to assemble into data memory section, ; equivalent to .sect ".data" .start "sect",addr ;to start assembling at address addr.

; .start serves the function of a linker, where sect could be .text ; .sect "mysect" to assemble into user's defined section mysect. ;Must have a .start directive before defining a section

.entry addr ;starting address when loading a file .brstart "sect",n ;align named section (sect) as a circular buffer to ; the next n address boundary, with n a power of 2 .align K ; align section program counter SPC on ; a boundary with K being a power of 2 .loop n ; loop n times through a block of code .endloop ; end of loop .end ; end of program 2.8

.if cond ; assemble code if cond is not zero (true) .else ; otherwise (else), assemble if cond is zero (false) .endif ; end of conditional assembly of code A .space n ; reserve n words in current section with A as the ; beginning address of the reserved space .ieee k ; k is converted to IEEE single-precision 32-bit ; format .fill 45,0 ; to fill 45 memory locations with zero 2.9

Examples:

;SINE4P.ASM - GENERATES A SINE USING ONLY 4 POINTS .start ".text",0x809900 ;starting address for text .start ".data",0x809C00 ;start address for data .include "AICCOM31.ASM" ;AIC communication routines .data ;data section AICSEC .word 162Ch,1h,4892h,67h ;Fs= 8 kHz SINE_ADDR .word SINE_VAL ;address of sine values .brstart "SINE_BUFF",16 ;align sine table SINE_VAL .word 0,1000,0,-1000 ;sine values LENGTH .set 4 ;length of circular buffer .entry BEGIN ;start of code .text ;text section BEGIN CALL AICSET ;initialize AIC LDI LENGTH,BK ;BK=size of buffer LDI @SINE_ADDR,AR1 ;AR1=addr of sine values LOOP LDI *AR1++%,R7 ;R7=table value CALL AICIO_P ;call AICIO for output BR LOOP ;loop back .end ;end 2.10

Examples:

;MATRIX.ASM - MATRIX/VECTOR MULTIPLICATION (3x3)x(3x1)=(3x1) .start ".data",0x809C00 ;starting address for data .start ".text",0x809900 ;starting address for text .data ;data section A .float 1,2,3,4,5,6,7,8,9 ;values for matrix A B .float 1,2,3 ;values for matrix B A_ADDR .word A ;starting address of matrix A B_ADDR .word B ;starting address of matrix B OUT_ADDR .word $ ;output (current) address .entry BEGIN ;start of code .text ;text section BEGIN LDP A_ADDR ;init to data page 128 LDI @A_ADDR,AR0 ;AR0=starting address of A LDI @B_ADDR,AR1 ;AR1=starting address of B LDI @OUT_ADDR,AR2 ;AR2= output address LDI 3,R4 ;R4 used as LOOPI counter LOOPI LDF 0,R0 ;initialize R0=0 LDI 2,AR4 ;AR4 used as LOOPJ counter LOOPJ MPYF3 *AR0++,*AR1++,R1 ;R1=A[I,J]*B[J] ADDF3 R1,R0,R0 ;accumulate in R0 DB AR4,LOOPJ ;decrement AR4.Branch until AR4<0 2.11

FIX R0,R2 ;convert R0 from float to integer STI R2,*AR2++ ;store integer output in memory LDI @B_ADDR,AR1 ;AR1=starting address of matrix B SUBI 1,R4 ;decrement R4 BNZ LOOPI ;branch while R4 is not zero BR $ ;branch to current address (itself)