1. Low-Power and Area-Efficient Carry Select Adder-2012 2. Design and Characterization of Parallel Prefix Adders using FPGAs -2011 3. Simulation of Image Encryption using AES Algorithm – 2011 4. An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs 5. -2011 6. A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER/SUBTRACTOR 7. -2011 8. Implementation of Convolutional Encoder and Viterbi Decoder using Verilog HDL- 2011 9. Design and Simulation of UART Serial Communication Module Based on VHDL- 2011 10. Design of three-lift controller based on FPGA -2011 11. A Review on Power Optimization of Linear feed back shift register (LFSR) for Low Power BIST.- 2011 12. The Design of an 8-bit CISC CPU Based on FPGA-2011 13. Optimized Design of UART IP Soft Core based on DMA Mode-2010 14. Design of SHA-1 Algorithm based on FPGA-2010 15. Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology -2010 16. FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression-2010 17. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm. -2010 18. Test data Compression using efficient bit mask and dictionary selection method- 2010 19. FPGA Implementation of efficient FFT algorithm based on complex sequence-2010 20. Simple Traffic light Controller: A Digital System design product-2010 21. Implementation of FIR Filter on FPGA Using DAOBC Algorithm -2010 22. FPGA based implementation of high performance Architectural Low Level Power 32 bit RISC Core-2009 23. 24. A Fast VLSI design of SMS4 Cipher based on twisted BDD s-box architecture-2009 25. A FPGA IEEE-754 2008 Decimal 64 Floating Point Multiplier-2009 26. Design and implementation of lossless high speed data compression and Decompression using VHDL 27. Design and implementation of Encryption module in DES for SECURITY using VERILOG 28. Design and implementation of Decryption module in DES for SECURITY using VERILOG 29. Implementation of real time Candy mechanic using VHDL 30. Design and implementation of pattern generator for circuit under test using VERILOG 31. Efficient design of butterfly architecture for radix 8 fast Fourier transform using VHDL 32. Design and implementation of Digital Code Lock using VHDL 33. Implementation of First in First out design using VHDL 34. VLSI design of Traffic Light Controller using VHDL 35. Design and implementation of Encryption module for AES core using VERILOG 36. Design and implementation of Decryption module for AES core using VERILOG 37. Design and implementation of Elevator Controller using VHDL 38. Design and implementation of LFSR for low power applications using VERILOG 39. Design and implementation of Serializer and deserializer using VHDL 40. Implementation of Frequency Distributor module using VHDL 41. Design and implementation of Vending machine controller using VHDL 42. Design and implementation of Finite impulse response filter using VHDL 43. VLSI design of 8 bit microprocessor implementation using VHDL 44. Design and implementation of array multiplier in VERILOG 45. Design and implementation of state machine controller 46. Design and implementation of Content Addressable Memory using VHDL 47. Design and implementation of House hold alarm system using VHDL 48. VLSI design of Reduced Instruction Set Computer Processor core using VHDL 49. VLSI implementation of Memory Core design using VHDL 50. Design and implementation of Random number Generator using VERILOG 51. Design and implementation of USB Transmitter 52. Design and implementation of Booth multiplier 53. Design and implementation of Wallace Tree multiplier 54. Performance evaluation of high speed and low power adders. 55. Design of an ATM (Automated Teller Machine) Controller