OBJECT CLASS Identifier ,Identifier : TYPE :=Value ;

Lecture-6

Data Object:

Every VHDL code needs some identifiers as the name of either the keyword or user-defined name as stated above. Those identifiers or elements which are used to hold some values are viewed in VHDL as a so called object or data object. Each data object of a VHDL program must be declared prior to its use. A data object holds a value of some specified type. The declaration syntax of a data object is :

OBJECT_CLASS identifier [,identifier ...] : TYPE [:=value];

In the above syntax, an identifier is the name specified to the object, and type is the permitted kind of value that a object can have. Object class specifies the class of the object which may be classified into one of the following four classes: signal, constants, variable.

Object Class: Every data objects fall under the following categories: Signal: A data object of signal class represent the logic signal, or wires in a digital circuit. A signal class object holds a list of values, which include the current value of the signal, and a set of possible future values that are to appear on the signal which can be assigned using signal assignment statements (<=). The syntax of the signal object is:

SIGNAL signal_name : type_name ;

In the above syntax, type_name determines the legal values that the signalcan have and its legal uses in VHDL. The signal types in VHDL are: BIT, BIT_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, SIGNED, UNSIGNED, INTEGER, ENUMERATION and BOOLEAN.

Signals objects can be declared at the following places in VHDL:

I. In the entity declaration

II. In the declaration section of the architecture between architecture and begin

III. In the declaration section of the package

Examples of signal object declaration is:

SIGNAL CLK : BIT;

SIGNAL gate_delay : TIME := 20 ns;

SIGNAL data_1 : BIT_VECTOR (3 downto 0); SIGNAL nibble_2 : BIT_VECTOR (1 to 4);

Then the assignment data_1<= “0011” would mean data_1 (3)=0 which is MSB, data_1 (2)=0, data_1 (1)=1, and data_1 (0)=1. But assigning nibble_2 <= “0011” would mean nibble-2(4)=1, nibble-2(3)=1, nibble-2(2)=0, nibble-2(1)=0, see the order of assignment now.

Constant:

A constant is a data object whose value cannot be changed during simulation. It can have a single value of a given type. The syntax of a constant object is as follows,

CONSTANT name_of_constant: type [ := initial value] ; If the initial value is not assigned at the time of declaration then the constant object is called a deferred constant. The deferred constant can only appear inside the package declaration, however the complete constant declaration and its associated value must appear in the package body. Constants can be declared at the start of an architecture and can then be used anywhere within the architecture. Constants declared within a process can only be used inside that specific process. The whole purpose of using the constant declaration is to improve the code readability, by using the name of the constant in place of a value or a number. As an example:

CONSTANT zero : STD_LOGIC_VECTOR (3 downto 0) := “0000”;

Then in the VHDL code we can use the word zero instead of “0000” to indicate and mean the same. The word zero thus would clearly mean 0000. It should be clearly emphasized that the name of the constant must match with the kind of value. Some of the example are: CONSTANT RISE_FALL_TME: time := 2 ns;

CONSTANT DELAY1: time := 4 ns;

CONSTANT RISE_TIME, FALL_TIME: time:= 1 ns;

CONSTANT DATA_BUS: integer:= 16;

Variable: As the name indicate, the variable class of object can be assigned different values at different times during . That is they are used to hold the result of computation and for the index variables in loop. However at a time it can hold only a single value of the specified type. The variable is updated without any delay as soon as the statement is executed, whereas as SIGNAL object get the value after some delay (at the end of that process). Variables must be declared inside a process (and are local to the process).

The syntax of the variable is:

VARIABLE name_of_variable : type [ := initial value] ;

As seen from the syntax, the variable can be assigned with a value at the time of declaration or it can be assigned at a later time. This is shown in the examples given below:

VARIABLE FLAG-1 : BOOLEAN := ‘1’;

VARIABLE SUM: integer range 0 to 100 :=10;

VARIABLE FLAG-2 : BOOLEAN;

In the first statement, the variable FLAG-1 is assigned a TRUE (‘1’) value. The second statement assigns 10 to the variable SUM from the specified range of integer 0 to 100. The last statement does not assign any value in the declaration. In such case, when the simulation starts, the variable FLAG-2 will have a default value as the initial value. The default value in VHDL is T’LEFT, where T is the object type and LEFT which is predefined attribute of a type that gives the leftmost value among a set of values in the range of that type. In the case of 3rd statement the variable FLAG-2 will have the value ‘0’ which is false.

Difference between variable and signal

Sl Category Signal Variable

1 Syntax SIGNAL : type[:=value]; VARIABLE : type[:=value];

Then used as: Then used as:

X <= ‘1’; X := ‘1’;

X <= a and b; X := a and b;

X <= “1010”; X := “1010”;

2 Place of All places except process, function Only inside process, functions and Decratation and procedures procedures

3 Scope Throughout the code Only inside the process, functions and procedures where declared

4 Memory More memory is required Require less memory

5 Updation With a delay, updated once inside Immediate, can be updated number of a process; time, the latest value can then be used

6 Operator <= :=

7 Wait It require wait statement if value is Does not require wait statement as the statement to be updated for next statement value is updated immediately usage

8 Converted to Signals are synthesized into wires No wire

9 No. of times Normally the last vale that is Can be updated and used any number used passed inside a process is used of times inside a process, any updation will occur only at the end of process.

10 Inferred as FF are inferred when a change on FF are inferred when the variable get a FF a signal occur due to an event on new value as a result of an event on a another signal signal and this updated value of variable is assigned to another signal.

11 Attribute Has number of attribute Very few attributes