ECE 5452 System on Chip Architecture and Design

fall 2007

midterm

due: November 6, 2007

Name: ______2.1. This For problem the circuit examines in the followingsources of Figure, skew and assume jitter. a unit delay through the Register and Logic blocks (i.e., tR = tL = 1). Assume that the registers, which are positive edge-triggered, have a set-up time tS of 1. The delay through the multiplexer tM equals 2 tR. 1 Determine the minimum clock period. Disregard clock skew. 2 Repeat part a, factoring in a nonzero clock skew: δ = t′θ – tθ = 1. 3 Repeat part a, factoring in a non-zero clock skew: δ = t′θ – tθ = 4. 4 Derive the maximum positive clock skew that can be tolerated before the circuit fails. 5 Derive the maximum negative clock skew that can be tolerated before the circuit fails. a. A balanced clock distribution scheme is shown in the following Figure. For each source of variation, identify if it contributes to skew or jitter. Circle your answer in the following Table. b. Consider a Gated Clock implementation where the clock to various logical modules can be individually turned off as shown in the following Figure. (i.e., Enable1,..., EnableN can take on different values on a cycle by cycle basis). Which approach (A or B) results in lower jitter at the output of the input clock driver? Explain. 3. Design and simulate, using SPICE, a CMOS circuit that generates an optimal differential signal as shown the following figure

4. The following figure shows a dynamic CMOS circuit in Domino logic. In determining source and drain areas and perimeters, you may use the following approximations: AD = AS = W · 0.625mm and PD = PS = W + 1.25mm. Assume 0.1 ns rise/fall times for all inputs, including the clock. Furthermore, you may assume that all the inputs and their complements are available, and that all inputs change during the precharge phase of the clock cycle. a. What Boolean functions are implemented at outputs F and G? If A and B are interpreted as two-bit binary words, A = A1A0 and B = B1B0, then what interpretation can be applied to output G? b. Which gate (1 or 2) has the highest potential for harmful charge sharing and why? What sequence of inputs (spanning two clock cycles) results in the worst-case charge- sharing scenario? Using SPICE, determine the extent to which charge sharing affects the circuit for this worst case.

5. a. In order to drive a large capacitance (C = 20 pF) from a L minimum size gate (with input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in the following figure. Assume that the propagation delay of a minimum size inverter is 70 ps. Also assume that the input capacitance of a gate is proportional to its size. Determine the sizing of the two additional buffer stages that will minimize the propagation delay.

b. If you could add any number of stages to achieve the minimum delay, how many stages would you insert? What is the propagation delay in this case?