An Algebraic Approach to Hardware Description and Verification By
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An Algebraic Approach to Hardware Description and Verification by Luca Cardelli Doctor of Philosophy University of Edinburgh 1982 CO Abstract We apply algebraic techniques to various aspects of hardware description and verification, with particular emphasis on VLSI (Very Large Scale Integration) circuit design. A simple and uniform notation for the description of networks of hardware components is introduced. It is shown how to impose planarity constraints, and how to treat regular and repetitive structures in convenient ways. The notation is applied to several examples of hardware networks. All these examples constitute different levels of description in the process of translating behavioural specifications into VLSI circuits. A formal semantics is given for the topmost level. Algorithms are given for the translation of purely topological planar stick expressions into metric structures from which layouts can be generated. The implementation of an experimental VLSI design system is described which uses algebraic concepts to hide detailed geometrical information. Geometric layouts are introduced as an abstract data type in a general purpose functional programming language and considerable advantages over traditional design systems are demonstrated with respect to the user interface. On the semantic side, two different formal frameworks are defined for the description of systems developing in continuous time. The emphasis is again algebraic, and techniques of both denotational and operational semantics are used. In the operational framework nondeterministic systems can be treated in a natural way, and it is possible to precisely formulate the behaviour of synchronous and asynchronous systems and to study their interactions. Acknowledgements I would like to thank first of all my supervisor, Gordon Plotkin, for his help, encouragement and precise hints in the development of this thesis. I regard this thesis as much a product of the Edinburgh environment as my own and I find it difficult to sort out all the ideas great and small which have been transmitted to me during these years. I would like to thank Robin Milner and Matthew Hennessy for continual assistance; Mike Gordon, Glynn Winskel, Kevin Mitchell, Igor Hansen and Marc Snir for helpful talks; Jeff Tansley and Irene Buchanan for getting me involved in VLSI; and the "system people" for providing some concreteness and an enjoyable computational environment. During my stay I have been supported by a scholarship of the Italian National Research Council and a scholarship of the University of Edinburgh. Declaration This thesis has been composed by myself and the work is my own, under the guidance of my supervisor Gordon Plotkin. Parts of Chapters 1 and 2, produced in different form in collaboration with Gordon Plotkin, appear in [Cardelli 81a]. Chapter 3 is [Cardelli 81b], Chapter 4 is (Cardelli 801 and Chapter 5 is an extended version of (Cardelli 821. Sections 2.5-2.6 have been submitted for publication. Contents 0. Introduction 0.1 The Past 0.1.1 Microelectronics 0.1.2 Design Tools 0.1.3 Semantics 0.2 This Thesis 1. Algebra of Networks 1.1 Introduction 1.2 Many—sorted Algebras 1.3 Net Algebras 1.3.1 Sorts 1.3.2 Signatures 1.3.3 Net Expressions and Laws 1.3.4 More on Net Expressions 1.4 Net Morphisms 1.5 Net Algebras and Flow Algebras 1.6 The Initial Net Algebra 1.7 Planar Networks 1.8 Bunched Networks 1.9 Planar Bunched Networks 1.10 Molecules, Rypercubes, Mosaics and Klein Bottles 1.11 Main Example: The Foster & Kung Pattern Matcher 1.12 Appendix: Some Proofs Needed for the Initiality Theorem 6 2. Hardware Networks for VLSI - 2.1 Introduction 2.2 Layouts 2.3 Clocked Networks 2.3.1 Clocked Transition Algebra (CTA) Expressions 2.3.2 Main Example 2.3.3 Formal Semantics of CTA 2.3.4 Semantics of the Main Example 2.4 Connectc r—Switch—Attenuator (CSA) Networks 2.4.1 The Value Domain 2.4.2 Connectors, Switches and Attenuators 2.4.3 Basic CSA Circuits 2.4.4 Static Semantics of CSA 2.4.5 Main Example 2.4.6 From CA to CSA 2.5 Stick Networks 2.5.1 Sticks 2.5.2 Stick Expressions 2.5.3 Examples 2.6.4 From CSA to Sticks 2.6 Grid Networks 2.6.1 Grids 2.6.2 Discrete Stretch Transformations 2.6.3 Normal Grid Composition 2.6.4 Grid Expressions 2.6.5 Grid Recomposition 2.6.6 From Sticks to Grids 2.6.7 From Grids to Layouts Sticks & Stones 3.1 Introduction 3.2 Pictures 3.2.1 Forms 3.2.2 Restriction 3.2.3 Renaming 3.2.4 Composition 3.3 Bunching 3.4 Iteration 3.5 Paths and Geometric Renaming 3.6 Figures 3.7 Commands 3.8 Modules and Externals 3.9 Efficiency 3.10 Conclusions 3.11 Syntax Analog Processes 4.1 Introduction 4.2 Analog Processes 4.3 An Algebra of Analog Processes 4.3.1 Composition 4.3.2 Restriction 4.3.3 Renaming 4.4 A Denotational Model 4.5 Feasibility 4.6 Expressibility 4.7 Indeterminacy 4.8 Flip—Flops 4.9 Conclusions 5. Real Time Agents 5.1 Introduction 5.1.1 Methodology 5.1.2 The Action Monoid 5.1.3 Time 5.2 Deterministic Agents 5.2.1 Signature 5.2.2 Operational Semantics 5.2.3 Observation 5.2.4 Equivalence 5.2.5 Algebraic Laws 5.2.6 Determinacy 5.3 Nondete rministic Agents 5.3.1 Signature 5.3.2 Operational Semantics 5.3.3 Algebraic Laws 5.3.4 Combined Calculus 5.4 Communication 5.4.1 Restriction 5.4.2 Morphisms 5.4.3 Delays 5.5 Recursion 5.6 Indefinite Actions and Delays 5.7 Synchronising on Non—Synchronous Input 5.8 An Asynchronous Rising Edge Counter 5.9 Descriptive Operators 6. Conclusions 6.1 Achievements and Future Work 6.2 The Future 6.2.1 VLSI 6.2.2 Design Tools 6.2.3 Semantics Appendix I. Syntax Description Notation Appendix II. Table of Symbols References 1 0. Introduction 0.1 The Past We begin with a review of those recent developements in the fields of microelectronics, design tools and semantics which are relevant to this thesis. 0.1.1 Microelectronics During the past few years, the steady progress in microelectronics has reached a point where completely untrained people can be taught, in the span of few weeks, to conceive and design highly complex hardware systems. This fact may come as a great surprise to two categories of people. On the one side professional hardware designers have seen the complexity of systems growing beyond any control, to the point where the technology is clearly more powerful than the ability to use it. It seems then unlikely that untrained people might do better. On the other side the average (computer) scientist who has been trained to think that "the hardware is made by the engineers", suddenly discovers that in a couple of months he can design and receive., his pet architecture; one the big manufacturers had thoughtfully refused to consider. However, it may seem unlikely that he can really do it if those expert manufacturers would not. The fact is that, until recently, the problem of managing the complexity of VLSI (Very Large Scale Integration) systems was not adequately considered. Design methodologies were developed which encouraged circuit efficiency at a very low level, often at the expense of global optimisations and disregarding elegance and 2 structure. The work done by Carver Mead, Lynn Conway and their collaborators (Mead 801 has completely changed this picture. Structured methodologies have proven to be more reliable, to extend smoothly to big systems and in many cases to provide more efficient and totally unexpected solutions. The simplicity reintroduced by structured methodologies allows people to learn quickly and to quickly produce non—optimal but working devices. In many cases the achievements of these newcomers (Conway 801 sound astounding with respect to average industrial products (Steele 80, Rivest 80, Masumoto 801. Structured methodologies are now beginning to be systematically used by big manufacturers, and the results are equally encouraging (Lattin 81, Mudge 811. 0.1.2 Design Tools Another key contribution has been the definition of a clean interface between design and fabrication (Mead 801. While any such interface necessarily introduces some inefficiency, it allows the designer to ignore most of the inessential aspects of the fabrication process. Moreover it seems sensible to expect that in future fabrication processes will be designed to. match this kind of interface, so that many of the inefficiencies will disappear (Mikkelson 811. The coincidence of structured methodologies, clean interfaces and high level of integration, has inspired a 3udden and rapidly spreading interest outside the microelectronic environment. It is most fortunate that this sudden "discovery" of VLSI, comes at a moment where the traditional architectures and design techniques used in microelectronics are showing their limits, and where there is a great need for complexity management techniques. In fact, the management of complexity has always been the main 3 problem in software engineering and programming language design, and structured methodologies are now simply common sense in those areas. The hope is that as a result of the experience gained in software we shall not have to wait long before getting very effective high level tools for hardware design. A subordinate hope is that we shall be able to completely omit the "batch" and "FORTRAN" stages of design tools. An interesting parallel can be made between the state of hardware design today and the state of software design in the fifties and early sixties. Layouts (the end—product of any VLSI design activity) have many of the characteristics of machine language programs.