Early Verification and Validation in Model-Based Design
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® ® Early Verification and Validation in Model-Based Design Amory Wakefield Technical Marketing The MathWorks © 2008 TheMathWorks, Inc. ® ® Introductions I spend most of my time: A. Creating specifications and requirements (systems and software) B. Implementation based on specification and requirements created by somebody else (generating, writing, deploying, debugging code) C. Both D. None of the above 2 ® ® Address the Entire Development Process RequirementsRequirements Design System V&V Requirements Validation Environment Robustness Testing Modeling Standards Checking Physical Components Component V&V Algorithms Design Verification Model Testing G e H t e Coverage and Test Generation G a a n e nd r e n - e r Property Proving e n a ra t te e e G Code Verification Digital Embedded Code Correctness Electronics Software Processor-In-The Loop Testing VHDL, Verilog C, C++ FPGA ASIC MCU DSP Integration Testing Software Integration Testing Integration Hardware-in-the-Loop Testing Hardware Connectivity Implement 3 ® ® Methods for Verification and Validation Traceability Requirements to model and code Model to code Modeling and Coding Standards Modeling standards checking Coding standards checking Testing Model testing in simulation Processor-in-the-loop Proving Proving design properties Proving code correctness 4 ® ® Increasing Confidence in Your Designs Confidence Traceability Modeling and Coding Model and Code Proving Design Standards Checking Testing Properties and Code Correctness Verification Method 5 ® ® Traceability System V&V Comp. V&V Integration Functional Requirements Design Environment Physical Components Tracing RequirementsÙModel Simulink Verification and Validation Algorithms H G e Tracing ModelÙSource Code G an t e e d a n ne - r e ra e r t n a e t Real-Time Workshop Embedded Coder e e G Digital Embedded Electronics Software Tracing RequirementsÙSource Code VHDL, Verilog C, C++ Simulink Verification and Validation FPGA ASIC MCU DSP Integration Implement 6 ® ® Tracing RequirementsÙModel System V&V Comp. V&V Simulink Verification and Validation Integration Creating links between text documents and model objects 7 ® ® Tracing RequirementsÙSource Code System V&V Comp. V&V Simulink Verification and Validation Integration Real-Time Workshop Embedded Coder Including requirements in the generated source code 8 ® ® Requirements Traceability—Overview System V&V Comp. V&V Simulink Verification and Validation Integration Bidirectional linking with external documents For Simulink and Stateflow Extensibility API Report generation DOORS integration Linking with read-only requirement documents Real-Time Workshop Telelogic DOORS Microsoft Word Embedded Coder integration Microsoft Excel Embeds requirements as PDF comments in source code HTML Text Supported document formats 9 ® ® Modeling and Coding Standards System V&V Comp. V&V Coding Standards Integration Modeling Standards Design Environment Physical Components Modeling Standards Checking Simulink Verification and Validation Algorithms H G e G an t e e d a n ne - r e ra e r t n a e t e e G Digital Embedded Coding Standards Checking Electronics Software PolySpaceTM Client for C/C++ VHDL, Verilog C, C++ FPGA ASIC MCU DSP Integration Implement 10 ® ® Simulink Model Advisor Model Checking Enforce modeling best practices Detect and troubleshoot modeling and code generation issues Check models for (a subset of) known version upgrade issues Automated report is a useful process audit document: More detailed summary Valid check states: Pass, Fail, Warning, and Not Run 11 ® ® Modeling Standards Checking Simulink Verification and Validation Static analysis of models for Requirement consistency Custom checks for company- specific processes Standards MAAB Style Guidelines DO-178B IEC 61508 Custom – using extensibility API Benefits Prevent problems early in the design process Automate time consuming review work 12 ® ® MAAB Style Guide Checks MathWorks Automotive Advisory Board (MAAB) Consistency Interoperability Error prevention Knowledge sharing 13 ® ® IEC 61508 Modeling Standards Checks This Absolute Value This Relational Operator block is block is operating on not outputting a Boolean data type an unsigned value which may lead to unpredictable which could result in results in the generated code. unreachable code. 14 ® ® Coding Standards Checking System V&V Comp. V&V PolySpace Client for C/C++ Integration Configure rules and run as part of the static check of the C source code MISRA-C:2004 Covers 122/142 rules 102 fully supported 20 partially supported 15 ® ® Testing System V&V Comp. V&V Integration Functional Requirements Design Model Testing Environment SystemTest Simulink Verification and Validation Physical Components Simulink Design Verifier Algorithms Verify that design meets H G requirements e G an t e e d a n ne - r e ra e r t n a e t e e G Code Testing Digital Embedded Real-Time Workshop Electronics Software Embedded Coder VHDL, Verilog C, C++ Embedded IDE Link products FPGA ASIC MCU DSP Target Support Package products Integration Verify that the behavior of source code and object code Implement matches the model 16 ® ® Demo Model testing using test cases stored in Excel 17 ® ® Improving Test Suite System V&V Comp. V&V Simulink Design Verifier Integration Generating tests to reach coverage criteria Test Generation Test generation harness with the copy of the original model Test inputs that ensure complete coverage 18 ® ® Code Testing with Generated Signals Simulink Software-in-the-loop On the host Processor-in-the-loop On the target processor Independent code testing environment Generated signals and model outputs are saved as a .mat data file Exported input signals drive code tests Exported model outputs become expectation values for code testing 19 ® ® Proving System V&V Comp. V&V Integration RequirementsRequirements Design Environment Physical Components Proving Design Properties Simulink Design Verifier Algorithms Prove that design meets H G a e G n t e the key functional e d a n ne - r e ra e r t n a e t e e requirements G Digital Embedded Electronics Software Proving Code Correctness VHDL, Verilog C, C++ PolySpace Server for C/C++ FPGA ASIC MCU DSP Prove that code meets non-functional runtime Integration requirements Implement 20 ® ® Proving Properties – Workflows System V&V Comp. V&V Simulink Design Verifier Integration 1. Authoring Benefits Highly Iterative Leads to precise definition of low Leads to improvement in level functional requirements design and in specifications Once established, properties 2. Execution and Reporting represent a model of design behavior Automated Minimizes chance of implementing Part of the regression undesired behavior testing harness 21 ® ® Proving Code Correctness System V&V Comp. V&V Integration Requirements Requirements Design Verifying code integration Environment Certification requirements Physical Components Reliability concerns Algorithms G e t e a n r e e r - e n a d t e t a e n r G a e H n e Digital Embedded G Electronics Software Proving Code Correctness VHDL, Verilog C, C++ PolySpace Server for C/C++ FPGA ASIC MCU DSP Integration Implement 22 ® ® Code Correctness Formal method: Abstract Interpretation Green Green reliable reliable P r o Red Green v e faulty reliable n Grey dead Green Orange reliable unproven Results are proven for all possible executions of the code!! 24 ® ® Summary Model-Based Design enables early verification and validation Early verification and validation methods improve and optimize your existing development process Early problem detection significantly reduces time spent debugging – shorter time to resolution 25.