Tools in CMOS Design

Tools in CMOS design Alexander Aulin Niklas Claesson 21 februari 2012 Introduction Table of contents 1 Introduction 2 Hardware Description Languages 3 Synthesis 4 Place & route 5 Simulation Alexander Aulin Niklas Claesson Tools in CMOS design Introduction Why is it important? You have to know your tools Tools will not fix a bad design Alexander Aulin Niklas Claesson Tools in CMOS design Introduction Early days Calma Graphic Data System introduced 1970 GDSII introduced 1978 Became de facto standard Inefficient OASIS Introduction to VLSI Systems by Carver Mead and Lynn Conway in 1980 Programming language → silicon Easier to simulate and test Electronic Design Automation Daisy Systems (ultimately Mentor Graphics) 1981 Mentor Graphics 1981 Valid Logic Systems (Cadence) 1981 Synopsys 1986 Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route HDL and design methodology Before HDLs, Netlists VHDL/Verilog, Register-transfer level SystemC, Transaction-level modelling Matlab/Simulink, Graphical modelling Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route HDL and design methodology Netlists Writing netlists by hand Draw standard cells Placing with early cad-tools Gate level Example verilog-netlist, gds2 and edif Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route HDL and design methodology VHDL/Verilog, RT-level Behavioral models implemented in components Models implemented with register transfer Components connected in structural Time unit: clock cycles Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route HDL and design methodology SystemC transaction level modelling High level approach Modules communicate on channels Time unit: none to clock cycle. Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route HDL and design methodology Matlab/Simulink Wireless baseband processor Simulink Data flow Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route Synthesis Realizing HDL with logic cells Done on 3 levels RT-level Logic-level Technology-level Optimizations Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route Synthesis RT-level Synthesize behavioral description into components. Optimizing i.e. with resource allocation and scheduling Different implementation methods Synthesized to specific components Very code-dependent Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route Synthesis Module-generator RT-level netlist is divided Generates e.g. adder, multiplier and comparator to different levels Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route Synthesis Logic synthesis Generating gate-netlist from simple logic. Optimizing logic, two-level minimization compare K-maps. Espresso popular minimization tool. Multi-level minimization, more flexible. Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route Synthesis Technology Mapping Mapping gate-net list to standard cells Standard cells predesigned on transistor level A lot of standard cells, different sizes for more optimal realization Different standard cells due to area/delay trade-offs Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route Synthesis Timing and Area constraints Minimize area Fulfill speed constraint Alexander Aulin Niklas Claesson Tools in CMOS design Hardware Description Languages Synthesis Place & route Synthesis High-level synthesis Generating RTL from high level descriptions Behavioral model directly to silicon Following usual RT synthesis flow. Tools C to silicon - Cadence Synphony - Synopsys Alexander Aulin Niklas Claesson Tools in CMOS design Place & route example Placing IP cores Place & route example Placing standard cells and power grid Place & route example Routing clock tree Place & route example Routing other signals and placing fillers Place & route example Optimizing and final routing Simulation Time consuming simulations SPICE circuit simulator ISPICE HSPICE (synopsys) PSPICE (cadence) ... Alexander Aulin Niklas Claesson Tools in CMOS design Simulation Continuous signals Partition Linearize Lookup table Alexander Aulin Niklas Claesson Tools in CMOS design Simulation Discrete signals {0,1,X} {0,1,X,Z,R,F,U,W,L,H,–,. } event-driven – evaluate at interesting time points unit-delay – evaluate at integer multiplies of a time unit switch-level models gate-level models functional models Alexander Aulin Niklas Claesson Tools in CMOS design Simulation Abstract data models Enumerations, integers Behavioral code Loosing precision VHDL, Verilog Alexander Aulin Niklas Claesson Tools in CMOS design Simulation Digital simulations software ModelSim (Mentor graphics) ISim, ISE Simulator (Xilinx) GHDL (open source) ... Alexander Aulin Niklas Claesson Tools in CMOS design Conclusions The bibliography Conclusions How will the tools develop? Integrate more features High level languages Manages the flow from behavioral model to silicon Faster from idea to market IP-cores → even more complex solutions Alexander Aulin Niklas Claesson Tools in CMOS design Conclusions The bibliography Thank you Questions? Alexander Aulin Niklas Claesson Tools in CMOS design Conclusions The bibliography The bibliography Lukai Cai an’d Daniel Gajski. Transaction level modeling: an overview. In CODES+ISSS, pages 19–24, 2003. Dennis Brophy. Oasis is the format for data exchange. Electronics Weekly, (2139):12, 2004. P.P. Chu. RTL hardware design using VHDL: coding for efficiency, portability, and scalability. Wiley-Interscience, 2006. Richard Goering. 24-hour chip design cycle called possible. EETimes, 2001. C. Mead and L. Conway. Introduction to VLSI systems. Addison-Wesley series in computer science. Addison-Wesley, 1980. Laurence W. Nagel and D.O. Pederson. Spice (simulation program with integrated circuit emphasis). Technical Report UCB/ERL M382, EECS Department, University of California, Berkeley, Apr 1973. Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Digital integrated circuits- A design perspective. Prentice Hall, 2ed edition, 2004. Alexander Aulin Niklas Claesson Tools in CMOS design.

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