128-Bit and 256-Bit Media Instructions

AMD64 Technology AMD64 Architecture Programmer’s Manual Volume 4: 128-Bit and 256-Bit Media Instructions Publication No. Revision Date 26568 3.16 September 2012 Advanced Micro Devices AMD64 Technology 26568—Rev. 3.16—September 2012 © 2002 – 2012 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other appli- cations intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD arrow logo, AMD Athlon, and AMD Opteron, and combinations thereof, AMD Virtualization and 3DNow! are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 26568—Rev. 3.16—September 2012 AMD64 Technology Contents Contents . iii Figures. xix Tables . xxi Revision History. xxiii Preface. xxv About This Book. xxv Audience . xxv Organization . xxv Conventions and Definitions . xxvi Related Documents. xxxvii 1 Introduction . .1 1.1 Syntax and Notation . 2 1.2 Extended Instruction Encoding . 3 1.2.1 Immediate Byte Usage Unique to the SSE instructions . 4 1.2.2 Instruction Format Examples . 4 1.3 Enabling SSE Instruction Execution . 6 1.4 String Compare Instructions . 7 1.4.1 Source Data Format . 9 1.4.2 Comparison Type . .10 1.4.3 Comparison Summary Bit Vector. 12 1.4.4 Intermediate Result Post-processing. 14 1.4.5 Output Option Selection . 14 1.4.6 Affect on Flags . 15 2 Instruction Reference . .17 ADDPD VADDPD . 19 ADDPS VADDPS . 21 ADDSD VADDSD . 23 ADDSS VADDSS . 25 ADDSUBPD VADDSUBPD . 27 ADDSUBPS VADDSUBPS . 29 AESDEC VAESDEC . 31 AESDECLAST VAESDECLAST . .33 AESENC iii AMD64 Technology 26568—Rev. 3.16—September 2012 VAESENC . 35 AESENCLAST VAESENCLAST . .37 AESIMC VAESIMC . 39 AESKEYGENASSIST VAESKEYGENASSIST . 41 ANDNPD VANDNPD . 43 ANDNPS VANDNPS. 45 ANDPD VANDPD . 47 ANDPS VANDPS . 49 BLENDPD VBLENDPD . 51 BLENDPS VBLENDPS. 53 BLENDVPD VBLENDVPD . 55 BLENDVPS VBLENDVPS . 57 CMPPD VCMPPD. 59 CMPPS VCMPPS . 62 CMPSD VCMPSD. 65 CMPSS VCMPSS . 68 COMISD VCOMISD. 71 COMISS VCOMISS . 73 CVTDQ2PD VCVTDQ2PD . 75 CVTDQ2PS VCVTDQ2PS . ..

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