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Memory Management CSC501 Operating SystemsPrinciples Memory Management 1 Previous Lecture q Memory Management Q Logical address / physical address Q Segmentation CPU Logical Addresses MMU Physical Addresses Memory I/O Devices 2 Segmentation and Paging q Segmentation Q Each process divided into variable-sized segments Q All process segments loaded into dynamic partitions q Paging Q Memory divided into equal-sized frames Q All process pages loaded into frames that are not necessarily contiguous Paging q Processes see a contiguous virtual address space Q The virtual address space into equal sized pieces called pages q The memory unit sees a contiguous physical address space Q The physical address space into equal sized pieces called frames q sizeof(page) = sizeof(frame) Q size usually a power of 2 between 512 and 8192 bytes Paging q Page table Q Stores mappings from virtual to physical address Q Entries contain: v Physical frame number v State: valid/invalid, access permission, reference, modified, and caching bits q Paging is transparent to the programmer Question: Do we still have external fragmentation problem? How about internal fragmentation problem? Address Translation Scheme q Address generated by CPU virtual address is divided into: index offset Q Page number (index)(p) – used as an index into a page table which contains base address of each page in physical memory page Q Page offset(d) –combined table with base address to define the physical memory address that is sent to the memory unit frame offset physical address Address Translation Architecture Implementation of Page Table q Page table is kept in main memory q Page-tablebase register (PTBR) points to the page table q Page-table length register (PRLR) indicates size of the page table q In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. Translation Look-aside Buffers (TLBs) q Translation on every memory access ->must be fast q What to do? Q Cache for page table entries is called the Translation LookasideBuffer (TLB) v Typically fully associative v Typically around 256 entries q On every memory access, we look for the page à frame mapping in the TLB Associative Memory q Associative memory –parallel search Page # Frame # Address translation (A´, A´´) QIf A´is in associative register, get frame # out QOtherwise get frame # from page table in memory TLB Miss q What if the TLB does not contain the right page table entry (or TLB miss)? Q Find a free entry (if not, evict an existing entry) v Replacement policy? Q Bring in the missing entry from the PT q TLB misses can be handled in hardware or software Q Software allows application to assist in replacement decisions Paging Hardware With TLB Memory Protection q Memory protection implemented by associating protection bit with each frame q Valid-invalid bit attached to each entry in the page table: Q “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page Q “invalid” indicates that the page is not in the process’ logical address space q Read/Write/Execute permissions also associated with each page table entry Memory Protection Page Number Page Offset 00010001101000100 Page Frame Protection 11011001101000100 000000 X RW 000001 X R 000010 100101 RW 000011 X RW 000100 110110 R 000101 X R 000110 X RW 000111 X RW 001000 001011 RW Page Table Physical Memory Page Table Structure q Hierarchical Page Tables q Hashed Page Tables q Inverted Page Tables Hierarchical Page Tables q Break up the logical address space into multiple page tables q A simple technique is a two-level page table Q A logical address (on 32-bit machine with 4K page size) is divided into: va page number consisting of 20 bits va page offset consisting of 12 bits Q Since the page table is paged, the page number is further divided into: va 10-bit page number va 10-bit page offset Two-Level Paging Example q Thus, a logical address is as follows: page number page offset pi p2 d 10 10 12 where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table Two-Level Paging Example q Address-translation scheme for a two-level 32- bit paging architecture Hashed Page Tables q The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. q Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted. q Common in address spaces > 32 bits Hashed Page Tables Inverted Page Tables q One entry for each real page of memory q Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page q Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs q Use hash table to limit the search to one —or at most a few —page-table entries Inverted Page Tables Memory Hierarchy Memory Cache Registers Question: What if we want to support programs that require more memory than what’s available in the system? Memory Hierarchy Virtual Memory Memory Cache Registers Answer: Pretend we had something bigger => Virtual Memory Background q Virtual memory –separation of user logical memory from physical memory. Q Only part of the program needs to be in memory for execution Q Logical address space can therefore be much larger than physical address space. v Gives the programmer the illusion of a virtual address space that may be larger than the physical address space Background q Motivated by Q Convenience: the programmer does not have to deal with the fact that individual machines may have very different amounts of physical memory Q Higher degree of multiprogramming: processes are not loaded as a whole. Rather they are loaded on demand. q Virtual memory can be implemented via: Q Demand segmentation Q Demand paging (most common) Demand Paging q Bring a page into memory only when it is needed Q Less I/O needed Q Less memory needed Q Faster response Q More users q Page is needed Þ reference to it Q invalid reference Þ abort Q not-in-memory Þ bring to memory Page Fault q If there is ever a reference to a page, first reference will trap to OS Þ page fault q Page fault handler looks at the cause and decide: Q Invalid reference Þ abort Q Just not in memory v Get empty frame v Swap page into frame v Reset tables, valid bit = 1 v Restart instruction Steps in Handling a Page Fault 0 Focus I: Page table 0 A 1 1 B 1 1 off 2 C 2 C 3 Focus II: Restart 3 D TLB 8 Process 4 Page replacement 4 E 5 E TLB miss 6 Bring in page Logical Update PTE 7 Memory 2 0 9 V 7 1 i 8 6 Find Frame 2 2 V 9 A Page fault 3 i 4 10 A B C 4 5 V 3 Physical Memory D E Question: Page Table Where is the Page fault 5 page table? handler Get page from CR3 backing store Next Lecture q Lab3 q Page Replacement Algorithms 30.
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