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Instituto Politecnico Nacional Centro De INSTITUTO POLITECNICO NACIONAL CENTRO DE INVESTIGACIÓN EN COMPUTACIÓN DISEÑO DE UN CIRCUITO PARA LA EVALUACIÓN DE LA TRANSFORMADA RÁPIDA DE FOURIER UTILIZANDO LÓGICA PROGRAMABLE TESIS QUE PARA OBTENER EL GRADO DE MAESTRO EN CIENCIAS EN INGENIERIA DE CÓMPUTO CON OPCIÓN EN SISTEMAS DIGITALES PRESENTA NAYELI VEGA GARCÍA DIRECTORES DE TESIS M. en C. OSVALDO ESPINOSA SOSA M. en C. VICTOR HUGO GARCÍA ORTEGA México D. F., Julio de 2013 II III Diseño de un circuito para la evaluación de la Transformada rápida de Fourier utilizando lógica programable Agradecimientos Agradecimientos Al Consejo Nacional de Ciencia y Tecnología, CONACYT, por su apoyo durante mis estudios de maestría. A mi alma mater: El Instituto Politécnico Nacional y al Centro de Investigación en Computación por darme la oportunidad de ser parte de una comunidad en donde comencé mi formación como profesionista desarrollando mis estudios de maestría. A mis asesores de tesis M. en C. Osvaldo Espinosa Sosa y M. en C. Victor Hugo García Ortega por sus acertadas sugerencias, consejos, tiempo y su invaluable ayuda durante el desarrollo de esta tesis y no con menos importancia a todos los profesores investigadores con los que tuve la oportunidad de trabajar por las enseñanzas impartidas. IV Diseño de un circuito para la evaluación de la Transformada rápida de Fourier utilizando lógica programable Dedicatorias Dedicatorias A mis padres Jaime Vega Pérez y Blanca García … Con profundo respeto por el gran ejemplo de vida que dan. A mis hermanos Sarai, Jaime y Paulina … Por todas las experiencias que hemos vivido, esperando dar un buen ejemplo y porque sigamos trabajando y creciendo juntos como hasta ahora. A mis amigos… Por el apoyo y palabras de aliento brindadas durante la realización de este trabajo. V Diseño de un circuito para la evaluación de la Transformada rápida de Fourier utilizando lógica programable Resumen Resumen La Transformada discreta de Fourier es una herramienta muy importante para el procesamiento digital de señales puesto que permite obtener el espectro de frecuencias de una señal discreta en el tiempo, esto permite realizar tareas como compresión de datos, convoluciones, filtrado de señales entre otras, sin embargo, obtener el espectro de frecuencias utilizando este método requiere de una gran cantidad de recursos por lo que se utiliza el algoritmo de la transformada rápida de Fourier que permite realizar el mismo trabajo reduciendo tiempo y recursos requeridos. Contar con hardware dedicado a la evaluación de la FFT da pie a la generación de diversas aplicaciones del procesamiento digital de señales, como las ya mencionadas. Opciones para la implementación hardware de este algoritmo existen muchas, sin embargo, en años recientes el hardware reconfigurable ha mostrado tener grandes ventajas sobre otras existentes puesto que el esfuerzo de implementación es de nivel medio obteniendo buenos resultados. Por las características del algoritmo de la FFT, la implementación hardware puede hacerse de diversas formas teniendo como ventaja el uso de hardware reconfigurable, en este trabajo se utilizó la técnica de implementación en cascada que permitió la reutilización de hardware por cada etapa del algoritmo combinado con un esquema de memoria non-inplace que facilitó la eliminación de dependencias de datos entre cada etapa de la arquitectura. Esta propuesta tiene la característica de ser fácilmente reconfigurable permitiendo así variar el número de puntos a evaluar haciendo pequeños cambios en las unidades de control sin modificar la ruta de datos de la arquitectura. Finalmente se obtuvo una arquitectura que evalúa el algoritmo de la FFT para 512 puntos en un tiempo de 5.16 s a una frecuencia máxima de operación de 49.41 MHz, permitiendo un ancho de banda de 49.41 MHz con un error absoluto de 7.02 unidades en el peor de los casos, evaluando hasta 9 productos complejos por ciclo de reloj una vez que el pipeline se encuentra lleno. Los resultados obtenidos fueron comparados con los resultados de la evaluación realizada por Matlab y por un programa codificado en C para finalmente concluir que la arquitectura propuesta se desempeña de manera adecuada. VI Diseño de un circuito para la evaluación de la Transformada rápida de Fourier utilizando lógica programable Abstract Abstract The Discrete Fourier transform is a very important tool in digital signal processing since it allows to obtain the frequency spectrum of a discrete signal in time, allowing to perform tasks such as data compression, convolutions, signal filtering and many others, but the frequency spectrum obtained using this method requires a lot of computing resources, so the Fast Fourier Transform algorithm is used. The same amount of work is done with reduced time and resources. Having hardware dedicated to evaluate the Fast Fourier Transform leads to the generation of applications in digital signal processing. Options for hardware implementation of this algorithm are many and varied, as, in recent years, reconfigurable hardware has shown to have great advantages over other existing methods since the implementation effort is of medium difficulty with very good results. Given the properties of the FFT algorithm, its hardware implementation can be done in various ways, and taking advantage of using reconfigurable hardware, the cascade implementation technique was used, that allowed the reuse of hardware for each stage of the algorithm, combined with a pattern of non-inplace memory which facilitated the removal of data dependencies between each stage of the architecture. This proposal allows the system to be readily reconfigurable, thereby enabling to vary the number of items to be evaluated by making small changes in the control units without changing the data path architecture. An architecture was designed that evaluates FFT algorithm for 512 points in a 5.16μs time at a maximum frequency rate of 49.41 MHz, allowing bandwidth of 49.41 MHz with an absolute error of 7.02 units in the worst case, evaluating up to 9 complex products per clock cycle once the pipeline is full. The results were compared with those evaluated by programs written in Matlab and C. We conclude that the proposed architecture performs adequately. VII Diseño de un circuito para la evaluación de la Transformada rápida de Fourier utilizando lógica programable Glosario Glosario ASIC: Por sus siglas en inglés, Aplicattion-specific integrated circuit. Es un circuito integrado diseñado a la medida para realizar una función en particular. Por ejemplo, un circuito amplificador operacional es un ASIC. DFT: Por sus siglas en inglés, Discrete Fourier transform. Es un tipo de transformada discreta utilizada en el análisis de Fourier. Permite la obtención del espectro de frecuencias de una señal discreta en el tiempo. DSP: Por sus siglas en inglés, Digital Signal Processor. Es un sistema con base en un procesador o microprocesador que posee un conjunto de instrucciones, hardware y software optimizados para aplicaciones que requieran operaciones numéricas en tiempo real, específicamente para aplicaciones de procesamiento digital de señales. FFT: Por sus siglas en inglés, Fast Fourier Transform. Es un algoritmo que permite calcular la transformada de discreta de Fourier, propuesto por Coley y Tukey en 1965 que tiene gran importancia pues permitió el ahorro de tiempo y recursos para la obtención del espectro de frecuencias de una señal. FPGA: Por sus siglas en inglés, Field Programable Gate Array. Es un dispositivo lógico programable que contiene bloques de lógica cuya interconexión y funcionalidad puede ser configurada mediante un lenguaje de descripción especializado. LE: Por sus siglas en inglés, Logic Element. Es la unidad lógica más pequeña en la arquitectura del FPGA (Altera). Como principal característica contiene una tabla de búsqueda (LUT, look-up table) de cuatro entradas, que es un generador de funciones, por lo que puede implementar cualquier función de cuatro variables. VHDL: Por sus siglas en inglés, Very High Speed Integrated Circuit Hardware Description Lenguage, lenguaje creado a partir de un proyecto promovido por el gobierno de Estados Unidos en 1981 y fue homologado por el IEEE en 1987 en el estándar 1076-87. VHDL utiliza una metodología de diseño de arriba hacia abajo (top-bottom) que permite describir el circuito de forma estructural (señales y sus VIII Diseño de un circuito para la evaluación de la Transformada rápida de Fourier utilizando lógica programable Glosario conexiones) y funcional (qué hace). Cada bloque se puede definir empleando sub-circuitos definidos en el mismo proyecto o disponibles en bibliotecas propias o de terceros. FIFO: Tipo de memoria de rápido acceso el cual funciona bajo un esquema first in – first out (primero en entrar - primero en salir). IPC: Número de instrucciones ejecutadas en un procesador por ciclo de reloj CPI: Ciclos de reloj necesarios por cada instrucción ejecutada en un procesador IX Diseño de un circuito para la evaluación de la Transformada rápida de Fourier utilizando lógica programable Índice de contenido Índice de contenido Resumen ................................................................................................................. VI Abstract .................................................................................................................VII Glosario ............................................................................................................... VIII Índice de contenido ................................................................................................
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