Fullyyp Depleted SOI Technolo gies

Bich-Yen Nguyen Acknowledgements SOITEC Team: IBM Team: • Jean-Michel Bidault • Kangguo Cheng • Nicolas Daval • Ali Khakifirooz • Frederic Allibert • Bruce Doris • Ludovic Ecarnot • Ghavam Shahidi • Konstantin Bourdelle • Walter Schwarzenbach STM Team: • Mariam Sadaka • Qing Liu • Phuong Nguyen • Franck Arnaud • Carlos Mazure • Nicolas Planes • Olivier Bonnin • Giorgio Cesana • Christophe Malevillle • Justin Wang Global Foundries : CEA/Leti Team: • Scott Luning • Olivier Weber • Francois Andrieu • Maul Vinet • Olivier Faynot

MOS-AK/GSA Workshop, April 11-12, 2013 2 • CMOS Landscape Beyond 28nm Node

• Value propositions of the Planar Fully Depletet SOI Technology

• Performance and Power Benchmarking

• FDSOI Device and Substrate Roadmap

• Summary

MOS-AK/GSA Workshop, April 11-12, 2013 CMOS Landscape Beyond 28nm

MOS-AK/GSA Workshop, April 11-12, 2013 4 Challenges of Continued CMOS Scaling

Source: IBM, T.C. Chen, ISSCC 2006 • Increased standby power dissipation

• Amplified Vth variability

⇒Impact Yield ⇒Limit Vdd scaling 5 MOS-AK/GSA Workshop, April 11-12, 2013 Leakage Power is still a Major Issue Despite the Use of Hi-K Dielectric

High-K/Metal Gate Stack

SiON/Poly Gate Stack

Source: IBS

MOS-AK/GSA Workshop, April 11-12, 2013 6 New Device Architectures

2003 2005 2007 2009 2011

90nm 45 nm 22nm

65nm 32nm

Strained Silicon

Introduction of New High-K / Metal Gate Materials

Introdu ction of New FllFully Dep ltdleted Device Architecture Devices

MOS-AK/GSA Workshop, April 11-12 2013 7 Fully Depleted Technology Landscape

Intel IBM STM

Foundries – Foundries Foundries 16/14 nm

MOS-AK/GSA Workshop, April 11-12, 2013 Value Propositions of the Planar Fully Depleted SOI Technology

MOS-AK/GSA Workshop, April 11-12, 2013 9 Alternate FD Device Architectures: Planar FDSOI or Vertical Multi-Gate FinFET-SOI

Minimum Design Max G Disruption G D scalabilit y SD S Buried OX S G D

Bulk Si Bulk Si Buried oxide

Conventional Planar Planar Single-or Vertical Multiple-Gate Bulk Transistor double Gate FDSOI FinFET SOI

MOS-AK/GSA Workshop, April 11-12, 2013 The End of Conventional MOSFET- The Era of FD Device Architecture

22nm Planar

MOS-AK/GSA Workshop, April 11-12, 2013 11 Planar ETSOI Structure and Advantages

Gate Material

Film & BOX Junctions Isolation Body Bias

Thin Silicon Channel

‐‐Ground Plane Hybrid‐ Bulk

• Total dielectric isolation • No channel doping, no pocket implant

– Lower S/D capacitances – Improved VT variation – Lower S/D leakages • Ultra thin BOX option – Latch-up immunity – Back bias control • Ultra thin Body (TSi~1/3LG) • Ground plane implantation – Excellent short channel immunity – VT adjustment – =>Low SCE, small SS & DIBL Source: STM J. Hartmann,, GSA Apr. 2012

MOS-AK/GSA Workshop, April 11-12, 2013 Threshold Voltage Mismatch

Measurement Benchmarking 3 Bulk platform ST 65nm FDSOI MOSFETs 8 2.5 ST 45nm ) IBM 90nm

mm 60% Red ucti on 2 IBM alliance Intel 65nm µ 6 32nm Hitachi FDSOI 4 Intel 45nm (mV.um) ST FDSOI Vt

(mV. 1.5

2 A t

vv IMEC FinFET

A 0 50% Reduction 1 This work 1 FDSOI ST GAA lk 2 u k 3 B ul lk 4 p B Bu lk MO Bu S 0.5 OI n DS I MO P SO S 10 20 30 40 50 60 FD Gate length L (nm) A = q √ 2 N W / C Square Vd=1V circle Vd=50mV vt ch dep ox Source: O. Weber et al, Source: Thean et al, Leti CEA, IEDM2007 Freesca le, IEDM2003 • Device matching important to SRAM/Analog circuits (eg. Current mirrors) • FDSOI (undoped channel) features 50 -60% mismatch improvement over bulk CMOS and PDSOI (doped channel)

MOS-AK/GSA Workshop, April 11-12, 2013 13 Scaling rules down to 8nm node TCAD with Electrostatic considerations 10 TSOI (thick BOX=145nm)

TBOX= 25nm )) TSOI (UTBOX case) 8 25nm

(nm 10nm

SOI 6

T 5nm Tsi dd NanoWire 757.5nm 4

TBOX= 145nm

Require 2

DIBL=100mV/V 0 2 6 10 14 18 22 LG (nm)

• Scalability possible down to LG~10nm, thanks to UTBOX Courtesy of CEA -LETI, O. Faynot et. al. IEDM 2010;

14 MOS-AK/GSA Workshop, April 11-12, 2013 Multi-VT Solution with Dual Metal Gate/GP

Logic SRAM nMOS pMOS nMOS pMOS HVT 0,8 TiN LVT TaAlN TaAlN TiN LVT RVT HVT SHVT BOX BOX BOX BOX 0,6 N-GP P-GP Metal N-GP P-GP nMO S change

) 0,4 nMOS pMOS nMOS pMOS GP-N GP-P TiN RVT TaAlN TaAlN SHVT TiN 0,2 GP-N GP-P BOX BOX GP BOX BOX N-GP 0 P-GP N-GP change P-GP d voltage (V ll GP-P -0,2 GP-N GP-P GP-N

Thresho -0,4 GP pMOS -0,6 change metal chan ge -0,8 TiN TaAlN/TaN O. Webber et al., IEDM’10

•Multi Vt requirement for SoC can be achieved for FDSOI device using dual WF metal-gate and ground-plane approach without back-bias MOS-AK/GSA Workshop,, April 11-12, 2013 FDSOI Workshop Body Bias: Speed & Power Control San Francisco, Feb. 2012

1.FDSOI

MOS-AK/GSA Workshop, April 11-12,, 2013 1616 Multi-VT Modulation for ETSOI with Back Bias

Leti- VLSI 2010 Q. Liu, ST, VLSI 2010

• VT tuning with BOX = 10nm and VBB , GP • N and PMOS: VT modulation of ≤200mV for 10nm BOX • No degradation of Ion-Ioff trade-off with back-bias up to +/-2V

MOS-AK/GSA Workshop, April 11-12, 2013 17 C2 - Confidential 18 C2 - Confidential 19 ETSOI Structure by IBM

Lg= 25nm Tsi= 6nm

B - SiGe

K. Cheng et al, IBM, VLSI 2009

In-situ boron doped SiGe S/D: ⇒Lower S/D resistance ⇒Reduces parasitic capacitance

MOS-AK/GSA Workshop, April 11-12, 2013 20 20nm FDSOI Performance Improvement VLSI 2011

20nm FDSOI on Thick BOX K. Cheng et al, IBM, VLSI 2011

• Ion for both N- and PMOS improved by optimizing S/D resistant and Tinv. • 20nm FDSOI RO delay at 0.9v improved by 20% as compared to those of 28nm Bulk ROC2 -at Confidential 1v 21

MOS-AK/GSA Workshop, April 11-12, 2013 Boosting FDSOI Performance with subtrate & strain engineering – IBM, A. Khalifizoor-VLSI 2012

More perf gain

• DC performance of FDSOI is comparable to state of the art planar-bulk devices • Smaller Lg and junction area => better AC performance

MOS-AK/GSA Workshop, April 11-12, 2013 22 C2 - Confidential 23 C2 - Confidential 24 FDSOI in a Nutshell

• FD SOI solves most of the CMOS scaling challenges

• FD SOI is SoC friendly

• FD SOI design is equivalent to Bulk

• FD SOI process cost equivalent to Bulk LP (28nm)

• FD SOI is a scalable technology

• FD SOI is risk-free alternative to FinFET for LP/G products

MOS-AK/GSA Workshop, April 11-12, 2013 25 Planar FD SOI Value Proposition

• FD SOI br ings a easy manu factur ing pat h to deve lop hig h per formance and low power CMOS process derivatives – Simple planar technology and transistor architecture – High performance at low supply voltage – Easy way to build different VTs for SoC design – On top of poly biasing, body biasing bring tremendous flexibility to the SoC design

• FD SOI enables time effective technology and design solutions – Re-use of most of the Bulk process FEOL modules, BEOL is fully identical – Migra ting dig ita l Bu lk librar ies an d des igns to FD SOI is a re-chtitiharacterization and signoff – FD SOI wafer easily etched to implement bulk structures and IPs – EDA flow and desiggqn techniques remain identical as Bulk

• FD SOI delivers a same performance as those 28nm HP technologies, without back bias (BB) or higher performance with BB at the cost of a 28nm LP process

MOS-AK/GSA Workshop, April 11-12, 2013 26 Planar FDSOI vs. Bu lk Performance/Power Benchmark

MOS-AK/GSA Workshop, April 11-12, 2013 27 CONFIDENTIAL CONFIDENTIAL CONFIDENTIAL IBM Research RO Comparison (ETSOI vs. FinFET) -6 10 I = 200nA/µm ETSOI off m) FinFET µ VDD RO Delay Delay // 10-7 0.7V (ps/stage)

(A ETSOI finFET* FP

OF 0.9V 8.5 10-8

+ I 0.7V 11.2 13.5 V = 0.9V 0.7V DD 0.8V

OFFN -9 I 10 7 9 11 13 15 17 *C. Auth, et al. Presented Delay (ps/stage) at Symp. VLSI Tech., 2012 ETSOI RO RO is is faster faster than than state state-of-the-art finFET finFET Courtesy of Bruce Doris, IBM K. Cheng et al. IEDM 2012

26 MOS-AK/GSA Workshop, April 11-12, 2013 31 Yield Learning Equivalent to Bulk Process

MOS-AK/GSA Workshop, April 11-12, 2013 Planar FDSOI Ad opti on and Roadmap

MOS-AK/GSA Workshop, April 11-12, 2013 33 CONFIDENTIAL CONFIDENTIAL FD SOI Migration Path

28nm FDSOI 14nm FDSOI

28nm SLP 20nm LPM 113CPP 90CPP 90Mx 64Mx

113CPP 90CPP 90Mx 64Mx

2011 2012 2013 2014

Courtesy of ST

• Low risk and effective TTM strategy to migrate Bulk platforms to FD SOI • Straightforward path to re-characterize 20nm LPM design environment to 14nm FD SOI

MOS-AK/GSA Workshop, April 11-12, 2013 36 Soitec FD-2D Substrate Options

Ultra‐ThinTop SiliconLayer Ultra‐ThinBuriedOxide

Base Silicon

Ultra‐Thin Top Silicon Layer SDG Ultra‐Thin Buried Oxide

Base Silicon Base Silicon

SDG Ultra‐Thin Top Silicon Layer Soitec FD-2D Ultra‐Thin Buried Oxide Evo14 with sSOI Base Silicon Base Silicon Sampling now: SOI + strain Soitec FD-2D SDG Evo20 Base Silicon Sampling now now Soitec FD-2D E28Evo28

In prod now

28 nm 22 nm / 20 nm 15 nm / 14 nm

MOS-AK/GSA Workshop, April 11-12, 2013 37 FD-2D Substrate Uniformity: Thin SOI & Thin Box

12nm SOI Thickness Range @ 3.13 A SOI +4Å BOX Base +2Å wafer 120Å 6sigma6 sigma -2Å BOX Mean @ 250 ±6 A W2W Range < 7 A -4Å

60 Wafer-to-wafer thickness (Å)

BOX Thickness Mean W2W hi 120t k hickness 120 ±5A5 A

40 Min 244.5 A Mean 247.2 A Max 252.1 A 20 Percentage

0 ol (Å) ints SOI 225 230 235 240 245 250 255 260 265 270 275 rr BOX Thick ne s s M e an Within wafer thickness (Å) 60

BOX Thickness Range 40 Min 2.7 A thickness cont ll wafers, all po ll wafers, entage

cc Mean 44A4.4 A AA 20

Per Max 6.8 A

0

012345678910 1 year production at prime spec BOX Thickness Range MOS-AK/GSA Workshop, April 11-12, 2013 12 April 2013 38 Summary

MOS-AK/GSA Workshop, April 11-12, 2013 39 Planar FD SOI Summary 1. FD SOI provides outstanding benefits for high performance, battery powered devices

– Leading edge performance across the full Vdd range – Good speed vs leakage trade-off – Record Vdd min for logic and SRAM – Full flexibilityygyggg in IP design with dynamic voltage scaling and biasing – Better performances than a G process at the cost of an LP technology 2. FD SOI offers a low risk design and manufacturing path for CMOS process derivatives at 28, 20 and 14nm

– No major disruption from current Bulk CMOS process manufacturing – Same EDA flow and design techniques as planar Bulk – Digital designs easy to re-characterize on FD SOI 3. Industry first Fully-Depleted SOC using 28nm FDSOI technology was demonstrated by STM/STE with 3GHz performance

4. 28nm and 14nm FD SOI will be available in foundries in 2013 and 2014, respectively

MOS-AK/GSA Workshop, April 11-12, 2013 FD-SOI provides unique value

Faster Transistors run at higher frequencies up than bulk CMOS enabling faster processors Æ This puts more powerful devices in the hands of the end user

Cooler Transistors are more power efficient than bulk CMOS with lower leakage and much wider range of operation points down to lower voltages Æ End user devices run cooler and last longer.

Simpler The manufacturing process for FD-SOI is much simpler than alternatives and making extensive use of existing fab infrastructure Design porting from bulk is simple and fast Æ Chip archit ect ure and const ructi on are simpl er and soft ware is simp ler for dev ices manufacturers

41 (10) MOS-AK/GSA Workshop, April 11-12, 2013 Thank You