A 90nm Variable Frequency Clock System for a Power- Managed ® Architecture

Tim Fischer, Ferd Anderson, Ben Patella, Sam Naffziger Intel, Fort Collins, CO Presentation Overview

• Montecito Clock System Architecture • Montecito Voltage to Frequency Converter (VFC) Architecture – Digital Frequency Divider (DFD) – Regional Voltage Detector (RVD) • Results • Summary and Acknowledgements Clock System Variable CVD Gater Architecture Supply SLCB

RVD Balanced Pins RAD Frequency Divisors Tree Clock Fuses Translation Distribution Table DFD SLCB Fixed Core0 DFD CVD Gater 1/N Supply RAD DFD Core1 Clock PLL Foxton CVD Gater 1/M DFD SLCB I/Os DFD SLCB CVD Gater 1/1 Bus Logic DFD SLCB CVD Gater 1/N

Phase Aligner Montecito Clock Generation Overview

• PLL generates master clock: Fmax = M*Fbus_clock • DFDs lock on Fmax using local DLLs – Synthesize core / uncore frequencies in 1.6% Fmax steps (ticks) – DFD range is Fmax*1.0 to Fmax*0.504 – Translation table sets DFD frequency at startup • Supply / Clock Domains – 2 Cores : variable V, F – Uncore (bus logic): fixed V, F = N * bus clock – Foxton controller : fixed V, F = 1 GHZ, DSP algorithms – Master PLL : fixed V, F, within clock system only Montecito Clock System Floorplan RVDs

FSB DFDs Core PLL / DFDs translation CORE 0 table / clock control

Foxton Controller DFD

Bus Logic DFD FSB DFDs CORE 1 Clock System Modes • Fixed Frequency (FFM) – Cores/Uncore are frequency and phase aligned – Cores/Uncore interfaces synchronous • Variable Frequency (VFM) – Core supply modulated by Foxton Controller to manage power envelope – Core frequencies track Vcore via Regional Voltage Detector (RVD) V-F curves • Respond to Foxton modulation and local transients • V-F curves match worst-scaling paths on chip – Core/Uncore interfaces asynchronous Voltage-to-Frequency Conversion (VFC)

Foxton-managed VDD from VR Per Core ~2400um Utility Clocks VDD 2 + RVD8 RVD9 RVD10 RVD11 di/dt noise 8 4 Local Blocks DFD2 L1 Clock , DOWN[11:8], HOLD[11:8] Temp Route To SLCBS RVD8 local environment 2 2 2 Utility Clocks

RVD4 RVD5 RVD6 RVD7 8 4 DOWN[7:4], HOLD[7:4] DFD1 L1 Clock Route To L0 Clock 2 Route 2 SLCBS from PLL Utility Clocks 2 RVD0 RVD1 RVD2 RVD3 8 4 DOWN[3:0], HOLD[3:0] DFD0 L1 Clock Route To SLCBS Example VFC Supply Droop Response Clock period increased No Adjust needed this cycle DFD Output Clock 1 2 3 4 5

Vcore

Droop increases RVD delay line delay RVD Delay Line Clock Increased delay asserts period “UP” for two cycles

Period “UP” to DFD Digital Frequency Divider (DFD) Block Diagram ½ FREQUENCY QUADRATURE PLL CLOCK DIFFERENTIAL INPUT DIFFERENTIAL CLOCK ROUTES TO SLCBS DIVIDE 16-PHASE DLL 64 DIVIDE BY 2 AND PHASES BY 2 INTERPOLATION STATE PERIOD MACHINE RVD UP / ADJUST FULL +2 TO -1 FREQUENCY DOWN PCSM REQUESTS DIFFERENTIAL “UTILITY” STARTUP CLOCK CONTROL ROUTES TO CLOCK SYSTEM TO / FROM SAME-CORE ODCS PCSMS CONTROL

SCAN AND TRIGGERS DFD Phase Selection

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VDD _ K 0 VDD C _ 5 O 1

VDD VDD L _ C VDD GND k pd FROM l O

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GND 6

FROM _ 2 1 8

pd1 3 _

S/M 4 _

sel8 sel9 sel15 1 _ 7 3 3 4 _ 6 _ phs8 phs9 phs15 k I l _ k l c k l c FROM GND c DLL

4:1 PHASE 16:1 PHASE SELECTION 4:1 PHASE OR ADJUST & CLOCK DRIVE VFC/RVD Voltage Tracking and CMOS Critical Path Scaling

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o 1.3 circuit4 n ( circuit5 y 1.1 a l e 0.9 D 0.7 0.5 600 800 1000 1200 Supply Voltage (mV) RVD Block Diagram

Delay Line 0A dly0in dly0out HOLD

Delay Line 0B M S

F eval0 eval0

D eval1

V eval1

R additional delay CVDs create deadzone

Delay Line 1A DOWN dly1in dly1out

Delay Line 1B eval0 eval1 clk RVD Delay Line

FINE F F COARSE F F F F F F F in R R R R R R R R R

odd 0 1 2 3 4 5 6 7 Dynamic Mux coarse_sel delay line out Coarse Delay Incremental Curves Fine Delay Incremental Curves

1.60E-09 1.30E-09

1.40E-09 1.20E-09 1.10E-09 4 Coarse Elements 1.20E-09 1.00E-09 1.00E-09 9.00E-10

8.00E-10 8.00E-10

7.00E-10 6.00E-10 6.00E-10 4.00E-10 5.00E-10 3 Coarse Elements 2.00E-10 4.00E-10 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 RVD Coarse Delay Element

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VDD VDD fbp nrun out O nfet

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run fbp RVD Phase Comparator

VDD I rck noh out O I in0 I in1

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F a) V 0 0 20 40 60 80 100 120 Supply Noise (mV) 50% Activity Power Virus -3 -10 x 10 16 -15 1.07 1.07 14 -20 1.06 1.06 12 -25

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-35 c 1.04 c 1.04 D V V

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P -40 1.03 1.03 6 -45 1.02 1.02 -50 4 1.01 1.01 -55 2 0 500 1000 0-60 500 1000 -1 0 1 b) Time (ps ) T1i0me (ps ) 10 10 c) Frequency (GHz) VFM Performance vs. Supply Noise FFM/VFM Core/Bus Clock Oscilloscope Traces

FFM, 1.2V Core clock 1.6GHz

Bus Logic clock 1.6GHz

VFM, 1.2V Core clock 2.14GHz

Bus Logic clock 1.6GHz Core Clock Spectral Content

FFM Fmax=2GHz, Ffixed=1.6GHz, 1.2Vcore

VFM Fmax=2GHz, 1.2 Vcore +/- 100mV, slow RVD curve Summary • Clock system enables a dynamic voltage-scaling system (Foxton) – Generates low-skew fixed- and variable- frequency clocks • High-BW Voltage-to-Frequency conversion (VFC) – Regional Voltage Detectors – Synchronized Digital Frequency Dividers – VFC follows programmed V/F response – VFC lock onto and tracks local supply voltage • Tracks high-BW switching transients:1 cycle VFC loop response • Tracks low-BW Foxton-based supply modulation • Performance benefits through reduced guardband: – Fast response to switching transients (3-8%, path dependent) – Tracks process, temperature (3%) • VFM operation demonstrated above 2GHz Acknowledgements E. Fetzer, S. Ghahremani, B. Doyle, A. Barton, M. Peters, S. Hall, J. Desai, E. Lee, F. Verdico, C. Pie, C. Bendele, A. Allen, R. Alley, P. Wyatt, B. Johnson, S. Undy, G. Benjamin, R. McGowen, R. Sandoval, C. Zhu, C. Young, A. Shoning, J. McBride, K. Kerr, D. Newsome, D. Sherlock, B. Haskin, J. Platenak, A. Gouldey, V. Freytag, R. Sims, G. Kumar, J. Pettsinger, R. Weidner, P. Liu, S. Wells, D. Clifford, S. Liepe, J. Ignowski, G. Ranson, P. Kummrow, C. Keen, W. Kever