DYNAMIC ENGINEERING 435 Park Dr., Ben Lomond, Calif

DYNAMIC ENGINEERING 435 Park Dr., Ben Lomond, Calif. 95005 831-336-8891 Fax 831-336-3840 [email protected] www.dyneng.com Est. 1988 Dynamic Engineering Product List 10/5/05

Please note that most Dynamic Engineering products have manuals available, and complete product data on our website. Links to each page are provided within this catalog. Table of Contents: IndustryPack®...... 4 PCI3IP...... 4 PCI5IP...... 4 cPCI2IP...... 5 cPCI4IP...... 5 PC/104p-4IP...... 6 IP-OctalSerial...... 6 IP_OptoISO_16...... 7 IP-QuadUART...... 7 IP-QuadUART-485...... 7 IP-BiSerial-IO...... 7 IP-Xilinx...... 8 IP-BiSerial-BA1...... 8 IP-BiSerial-BA2...... 8 IP-BiSerial-BA3...... 9 IP-BiSerial-BA4...... 10 IP-BiSerial-BA5...... 10 IP-BiSerial-RTN1...... 11 IP-BiSerial-RTN2...... 11 IP-BiSerial-LS1...... 12 IP-BiSerial-PA1...... 12 IP-BiSerial-HDP...... 12 IP-BiSerial-NG4...... 12 IP-BiSerial-Q1...... 13 IP-BiSerial-LM1...... 13 IP-BiSerial-Miller...... 14 IP-CompactFLASH...... 14 IP-Pulse...... 14 IP-Parallel-TTL...... 15 IP-Parallel-1...... 15 IP-Parallel-2...... 15 IP-Parallel-3...... 15 IP-Parallel-4...... 15 IP-Parallel-5...... 16 IP-Parallel-485...... 16 IP-Tape...... 16 IP-Parallel-HV...... 16 IP-Crypto...... 17 IP-ARINC 429...... 17

Embedded Hardware and Software Solutions Page 1 IP-Debug-Bus...... 18 IP-Debug-IO II...... 18 HDRterm50...... 19 IP-Mounting Kit...... 19 HDRribn50...... 19 PMC...... 20 PMC2PCI...... 20 PMC-Parallel-485...... 20 PMC-Parallel-485-NG1...... 21 PMC-Parallel-485-NRC1...... 21 PMC-BiSerial-IO...... 21 PMC-BiSerial-II...... 22 PMC-BiSerial-II-NG1...... 23 PMC-BiSerial-II-NVY1...... 24 PMC-BiSerial-BAE1...... 24 PMC-BiSerial-BA1...... 24 PMC-BiSerial-PS1...... 24 PMC-BiSerial-s311...... 25 PMC-BiFIFO...... 25 PMC-Serial...... 26 HDEterm68...... 26 PCI2PMC...... 26 Updated Features! PCIBPMC...... 27 cPCI2PMC...... 27 cPCIBPMC3U64...... 27 HDEcabl68...... 28 PMC-Extendio...... 28 PCI...... 29 PCI3IP...... 29 PCI5IP...... 29 PCI2PMC...... 30 Updated Features! PCIBPMC...... 30 PMC2PCI...... 31 LVDS_Cable...... 31 New! PCI_ECL...... 31 PCI_LVDS_8R...... 32 PCI_LVDS_8T...... 33 PCI_Altera...... 34 HDEterm100...... 35 HDEcabl100...... 35 PCI2cPCI-32...... 35 PCI2cPCI-64...... 35 CPCI...... 36 PIM-Carrier-Dual...... 36 PIM-Parallel-IO...... 36 PIM-Universal-IO...... 37 cPCI2IP...... 37 cPCI4IP...... 38 cPCI2PMC...... 38 cPCIBPMC3U64...... 38

Embedded Hardware and Software Solutions Page 2 PCI2cPCI-32...... 39 PCI2cPCI-64...... 39 PC/104p...... 40 PC/104p-4IP...... 40 PC/104p-IP...... 41 PC/104p-BiSerial...... 41 PCI2PC/104p...... 43 Other...... 43 S-A-Relay...... 43 IEEE Extender...... 44 NuBus Extender...... 44

Embedded Hardware and Software Solutions Page 3 IndustryPack® http://www.dyneng.com/pci_3_ip.html http://www.dyneng.com/pci3ip_xp.html

PCI3IP Why pay for slots you are not using? Use the PCI3IP for embedded control and your favorite IP modules. The PCI3IP is a half size PCI card with 3 IP module slots. The IP modules have independent clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. Two of the slots can be used for a double wide IP. FAST® technology provides an integrated PCI to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 6 under user control. An 8 position dip-switch is provided for board identification and other user purposes such as configuration control and facilitating debugging. Fused filtered power for each IP module. The PCI3IP is easy to use and has an engineering kit available to speed your integration to success. The PCI3IP XP/2000 drivers are available to support your hardware with a software to software interface. The drivers come with a generic IP driver to use with IPs that do not have an IP level driver available. IP level drivers written for the PCI3IP will also work with other Dynamic Engineering carriers including the PCI5IP, cPCI2IP, PC/104p-4IP and our other planned carriers. http://www.dyneng.com/pci5ip.html http://www.dyneng.com/pci5ip_xp.html

PCI5IP Use the PCI5IP for embedded control and your favorite IP modules when you need more than 3 in a slot. The PCI5IP is a full size PCI card with 5 IP module slots. The IP modules have independent clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. Two pairs of two slots can be used for a doublewide and 32 bit IPs. FAST® technology provides an integrated PCI to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 8 under user control. An 8 position dip-switch is provided for board identification and

Embedded Hardware and Software Solutions Page 4 other user purposes. Fused filtered power for each IP module. The PCI5IP is easy to use and has an engineering kit available to speed your integration to success. WindowsXP/2000 and Linux drivers are available to support your hardware with a software to software interface. The drivers come with a generic IP driver to use with IPs that do not have an IP level driver available. IP level drivers written for the PCI5IP will also work with other Dynamic Engineering carriers including the PCI3IP, cPCI2IP, PC/104p- 4IP and our other planned carriers. http://www.dyneng.com/cpci2ip.html cPCI2IP Use the cPCI2IP for embedded control and your favorite IP modules when you need 2 in a slot or have a 3U chassis. The cPCI2IP is a 3U 4HP size cPCI card with 2 IP module slots. The IP modules have independent clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. Each slot has “self- heating” fused filters. The slots can be used for a double wide IP. FAST® technology provides an integrated cPCI to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 8 under user control. An 8 position dip- switch is provided for board identification and other user purposes. Fused filtered power for each IP module. The 50 pin header connectors provide IO through the bezel and cable options for discrete or ribbon cable wiring. Optional J2 connectivity is available for users with a 32 bit PCI bus. –J2 The cPCI2IP is easy to use and has an engineering kit available to speed your integration to success. http://www.dyneng.com/cpci4ip.html cPCI4IP The cPCI4IP provides four IndustryPack¨ slots in one 6U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in each slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. Windows® driver available.

http://www.dyneng.com/pc104p4ip.html

Embedded Hardware and Software Solutions Page 5 PC/104p-4IP Use the PC/104p-4IP for embedded control and your favorite IP modules when you need 4 in a PC/104p stack. The PC/104p-4IP is a special mechanical card with 4 IP module slots. The PC/104p connector placement is standard. The overall dimensions are larger than standard PC/104p. The IP modules have independent clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. The slots can be used for a double wide IP. FAST® technology provides an integrated PC/104p to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 8 under user control. An 8 position dip- switch is provided for board identification and other user purposes. Fused filtered power for each IP module. The 50 pin header connectors provide IO and cable options for discrete or ribbon cable wiring. The PC/104p-4IP is easy to use and has an engineering kit available to speed your integration to success. http://www.dyneng.com/ip-octalserial.html

IP-OctalSerial The OctalSerial is a high density multi-channel IndustryPack® with the equivalent of 4 IP-BiSerial cards in one. Perfect for situations where IP slots are in short supply and precision IO is required. The eight channels are arranged with 4 TX and 4 RX. Each channel can have the same or different protocols supported. The 24 high speed differential IO can be programmed for use as transmitters or receivers and have programmable termination. The FIFOs can be up to 128K words deep and feature programmable interrupts on the FIFO level. Each state-machine has independent interrupts, control registers and status. Please send us your requirements.

Embedded Hardware and Software Solutions Page 6 http://www.dyneng.com/ip_optoiso_16.html

IP_OptoISO_16 Optically Isolated Output control. 0-60V, 1.5A. IP- OptoISO-16 is an IndustryPack® Module with 16 optically isolated FET switches. Each FET acts as a single pole normally open photo-voltaic relay rated at 1.5A and 0- 60V. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. Each optical switch operates independently. Additional features include: 8 and 32 MHz operations, two counter-timers with programmable waveform output, glitch-free DIODE protected outputs, customizable FPGA. http://www.dyneng.com/ip-quaduart.html

IP-QuadUART Four UART ports with independent programmable baud rate, RS-232 [230K] and RS-422 [1.5M] operation, 8/32 IP bus compatible, write through and pre-read functionality coupled with 128 byte FIFOs for optimum performance. Byte and word oriented data transfer. Use with Dynamic Engineering Carrier to create a 32 bit [4 byte] data transfer. All options are software selectable. Full MODEM signaling with ‘232 modes, TX/RX/RTS/CTS with 485 mode. http://www.dyneng.com/ ip-quaduart-485.html

IP-QuadUART-485 IP-QuadUART-485 design integrates a quad UART onto an IndustryPack module. With full and half duplex operation through RS-485 transceivers. UART (16C854), 8/32 IP bus compatible, write through and pre-read functionality coupled with 128 byte FIFOs for optimum performance. 1.5 M top programmable data rate. Byte and word oriented data transfer. Use with Dynamic Engineering Carrier to create a 32 bit [4 byte] data transfer. All options are software selectable. RX/TX/RTS/CTS/DTR/DSR supported for each channel. http://www.dyneng.com/ipbis.html

IP-BiSerial-IO Now with more than 16 versions. Our customers have the IP-Biserial in use for a wide variety of applications including: Simulation of expensive system components for test and control, robotics, telemetry, data capture and transfer, communications, translation between incompatible equipment types, signal generation, and control. What will you

Embedded Hardware and Software Solutions Page 7 use the BiSerial for? Send us your timing and we will send you the interface. Please refer to the following products for other customized versions. The serial RX and TX channels are highly programmable and fully independent. The standard interface offers Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. RS422/485 and TTL compatibility will interface to a variety of systems.

IP-BiSerial-BA1 Transmit Timing Diagram

request discrete transmit discrete acknowledge discrete clock data out D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 P

IP-BiSerial-BA1 Receive Timing Diagram

request discrete

transmit discrete

acknowledge discrete

clock

data in D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 P http://www.dyneng.com/ipbis.html#ip-xilinx

IP-Xilinx Order IP-Xilinx if you want to do your own development. A stock IP-Biserial board will be shipped with a blank PROM for the Xilinx. Purchase the IP-Xilinx-Kit to support your efforts. The standard Xilinx device is a spartan30-4 - plenty of room for your custom project. The engineering kit has a reference design for the IP interface, plus the UCF and other system files to get you started. http://www.dyneng.com/ipbis_ba1.html

IP-BiSerial-BA1 Integrated TX and RX channels. Odd or Even Parity generation and checking. Frame, Parity and overrun error checking on RX channel. Transitions on the falling edge, valid data on the rising edge. Can be programmed to use an internal reference clock at multiple frequencies or the external reference clock. Customized IP-BiSerial-IO design. http://www.dyneng.com/ipbis_ba2.html

IP-BiSerial-BA2 Symmetrical Transmit and Receive channels. Data, Clk, and Strobe. Odd or Even Parity generation and checking. Frame, Parity and overrun error checking on RX channel. Transitions on the rising edge, valid data on the falling edge. Can be programmed to use an internal reference clock at multiple frequencies or the external reference clock. Input clock detection circuitry automatically switches to an internal reference when the clock is lost. Status is provided. Customized IP-BiSerial-IO design.

Embedded Hardware and Software Solutions Page 8 http://www.dyneng.com/ipbis_ba3.html

IP-BiSerial-BA3 Asymmetrical transmitter and receiver functions. The transmitter sends data MSB first and uses a strobe the same width as the transmitter data. Data transitions on the rising edge and can be captured on the falling edge of the free-running clock. The transmit timing can be synchronized to the synchronization pulse that is provided. The

sync pulse has a period of 2500 uS and a width of 4 uS. The Receiver expects LSB first data. The data is read in on the falling edge of the clock after Strobe is detected. The strobe is a pulse valid only for the first data bit. The receiver uses a counter to load a user specified number of words of data [1-255]. Input clock detection circuitry automatically switches to an internal reference when the clock is lost. Status is provided.

Embedded Hardware and Software Solutions Page 9 http://www.dyneng.com/ipbis_ba4.html

IP-BiSerial-BA4 Capture Manchester encoded data and re-transmit that data in UART compatible form. Unusual design with only the IDPROM implemented on the IP Bus. Manchester data is tested to find the first word of a block then stored into an internal FIFO. The stored data is re-ordered to be lst first and modified with start and stop bits to create a data stream suitable for UART reception at a baud rate of 38400. Manchester data is also re-driven to external device. The Manchester serial protocol is implemented as a 1 MHz Manchester II (Bi- phase) serial link, with 0/1 as the idle pattern and 0/1/1 or 0/0/0 recognized as the synchronization pattern. http://www.dyneng.com/ipbis_ba5.html

IP-BiSerial-BA5 Simulate the missile serial data link interface to the Brimstone missile launcher. Receive data in UART form 1 start, 1 stop, 8 data, 1 parity. The received data is checked for parity, checksum, number of bytes, valid ID, valid count. Transmission of stored message in response to received message with status added from received message. 1 MHz clock reference input, bi-directional data. Customized IP-BiSerial-IO design.

CLOCK (1MHz)

___ nS Possible Data Inter-gap time- Data stable on Data High clock rising edge DATA (Bidirectional 1 2 3 4 5 6 7 8 9 P S 1 2 3 4 5 6 7 8 9 P S )

Data Stop bit - Always One Start bit - Always Zero Parity bit (Odd) Data Word

Embedded Hardware and Software Solutions Page 10 3.0 mS max .660 mS typ .660 mS typ STB 1 mS max 1 mS max CLK LAUNCHER TO MISSILE BLOCK MISSILE TO LAUNCHER BLOCK 60 BYTES PORT TURN AROUND 60 BYTES 5 µS min DATA D0 D1 D2

2 mSec max

Bus goes to high impedance (50 µSec max after last byte)

START BIT

BYTE n BYTE (N+1)

0 7 MESSAGE BYTE n

PARITY BIT

STOP BIT

http://www.dyneng.com/ipbis_rtn1.html

IP-BiSerial-RTN1 10 MHz serial data rate with programmable clock and special handshaking features. Three different programmable protocols.

10 Mhz

CLOCK

“select ext” 0

“TR pulsetrain” 1

“TR” X

TRINPUT

TRGATE . . . http://www.dyneng.com/ipbis_rtn2.html

IP-BiSerial-RTN2 Update to BA2 version with an expanded word counter, 16 Mb FIFO, programmable parity odd/even and on/off, programmable almost empty and programmable almost full interrupt capabilities added. IP, oscillator or user clock reference with 12 bit programmable divider for transmit frequencies.

Embedded Hardware and Software Solutions Page 11 http://www.dyneng.com/ipbis_ls1.html

IP-BiSerial-LS1 4 MHz serial data rate with data, clock and strobe interface. Full Transmit and Receive Channels. 16K FIFOs both channels. TX/RX complete interrupts plus PAE and PAF. http://www.dyneng.com/ipbis_pa1.html

IP-BiSerial-PA1 Complex state machine with programmable delays for Frame to Word, Word to Data, data to Word, Inter-Word gap and Word to Frame. Odd or Even Parity generation and checking. FRAME, WORD, DATA and CLOCK interface signals. PAE and PAF interrupts. Three and Four wire modes. Frame, Parity and overrun error checking on input channel. Transitions on the rising edge, valid data on the falling edge. Can be programmed to use an internal reference clock at multiple frequencies or the external reference clock. http://www.dyneng.com/ipbis_hdp.html

IP-BiSerial-HDP The HDP features half-duplex operation with data transfer and status modes. LSB first, 16 bits plus parity. Used by USN to simulate ship-board mission critical systems for test purposes.

STROBE

CLOCK

DATA OUT D0 par D0 par http://www.dyneng.com/ipbis_ng4.html

IP-BiSerial-NG4 Features include: Software programmable 3/4 wire modes, parity, transmit frequency, the width of the synchronization pulse, the time delay after the sync and the start of data, and the time between data words. The word transfer has an associated Word Sync signal to provide for framing and error checking. The Frame sync signal provides for message level synchronization. The NG4 has programmable receive word count and receive all mode. The IP BiSerial NG4 has a 50 MHz reference oscillator.

Embedded Hardware and Software Solutions Page 12 http://www.dyneng.com/ipbis_q1.html

IP-BiSerial-Q1 The Q1 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP Clock is used to derive the reference clocks for serial operation. A range of frequencies is available; 62.5 KHz. is the base design frequency. Bursted clock and data. signals control data flow. 16 bit data with parity. LSB first, parity last. Single or double word transmissions. Parity and Over-run checked on the receive channel. Parity generated on the transmit channel. Programmable 16/32 bit operation and continuous mode. Multiple interrupt options. 1K x 16 FIFO buffers. Windows® XP and Linux Drivers available.

http://www.dyneng.com/ipbis_lm1.html

IP-BiSerial-LM1 Programmable message length 1-65K bytes. Data, clock and Strobe interface. MSB first, Active high strobe. Byte count on reception. 10, 8, 4, 2, 1 MHz and other programmable frequencies. TX, RX, Programmable Almost Full and Programmable Almost Empty interrupts. Use to interface with Receivers, Antenna Control Units and other serial interface equipment.

Embedded Hardware and Software Solutions Page 13 http://www.dyneng.com/ipbis_miller.html

IP-BiSerial-Miller The Miller version of the BiSerial board implements the "Miller" encoding and decoding scheme. The Miller method uses transitions and spacing to encode/decode data. The result is a 50% [overall] duty cycle waveform with clock and data in the same data stream. The Miller version supports both transmit and receive operation, TTL and 485 IO [software selectable] plus the usual IP-BiSerial features. 8K x 16 FIFO buffers. Windows® XP Driver available.

http://www.dyneng.com/ip_cf.html

IP-CompactFLASH Add solid state data storage to your system with IP-CF. The IndustryPack compatible IP-CF design converts between the IP Module bus and the IDE bus used for FLASH memory modules and other PC Card compatible designs. The IP-CF acts as a bridge between the IP bus and your PC Card hardware. The IP-CF comes standard with a 64 Mb CompactFLASH ™ card. http://www.dyneng.com/ip_pulse.html

IP-Pulse The IndustryPack compatible IP-Pulse features 4 independent programmable pulse generators. The outputs can be configured to be TTL /CMOS or RS422/485 compatible in several combinations. A real space saver for systems with both types of IO. Perfect for your embedded control applications.

Embedded Hardware and Software Solutions Page 14 http://www.dyneng.com/ip_parallel_io.html

IP-Parallel-TTL IP with 48 digital parallel IO lines. Each channel is programmable to be an input or an output on a channel-by-channel basis via software. All 48 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. Outputs in TTL mode are driven with 64 mA open-drain devices to allow multi-drop applications. 470 ohm pull-up resistors are provided. Counter-timer function provided. http://www.dyneng.com/ip_parallel_io.html

IP-Parallel-1 40 TTL IO and 4 differential pairs. Each channel is programmable to be an input or an output on a channel-by-channel basis via software. All 44 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. http://www.dyneng.com/ip_parallel_io.html

IP-Parallel-2 32 TTL IO and 8 differential pairs. Each channel is programmable to be an input or an output on a channel-by-channel basis via software. All 40 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. Counter-timer function provided. http://www.dyneng.com/ip_parallel_io.html

IP-Parallel-3 24 TTL IO and 12 differential pairs. Each channel is programmable to be an input or an output on a channel-by-channel basis via software. All 36 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. Counter-timer function provided. http://www.dyneng.com/ip_parallel_io.html

IP-Parallel-4 16 TTL IO and 16 differential pairs. Each channel is programmable to be an input or an output on a channel-by-channel basis via software. All 32 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. Counter-timer function provided. Our most popular version.

Embedded Hardware and Software Solutions Page 15 http://www.dyneng.com/ip_parallel_io.html

IP-Parallel-5 8 TTL IO and 20 differential pairs. Each channel is programmable to be an input or an output on a channel-by-channel basis via software. All 28 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. Counter-timer function provided. http://www.dyneng.com/ip_parallel_io.html

IP-Parallel-485 24 differential pairs. Each channel is programmable to be an input or an output on a channel-by-channel basis via software. All 24 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. Counter-timer function provided. http://www.dyneng.com/ip_par_tape.html

IP-Tape IP-Parallel-IO-BA1 Data Tape Controller interface version. The DTC IP-TAPE interface has 22 Address, 16 Data plus Parity, 4 control and 5 status lines. Parity is automatically generated in write mode and checked in read mode. Parity is programmable to be odd or even. Outputs in "tape" mode are driven with 64 mA open-drain devices. 470 ohm pull-up resistors are provided. The registers are mapped as 16 bit words and are read-writeable. Customized IP-Parallel-IO design. http://www.dyneng.com/ip_parallel_hv.shtml

IP-Parallel-HV High Voltage IP compatible card with 48 programmable IO. 40 mA sink. Low side switch. Open collector interface. Interrupt generator on each input channel. Filtered or direct input. Up to 30V external signals. The standard configuration is a 6.5V reference and the ability to supply an external reference. Other voltages are available. Use the IP Parallel HV for your control, avionics and robotics applications. Perfect for your embedded control applications.

Embedded Hardware and Software Solutions Page 16 http://www.dyneng.com/ip_crypto.shtml

IP-Crypto The IP-Crypto is a special version of the IP-Parallel- HV. The basic design features are retained and an interface to a KYK-13 is provided. The KYK-13 interface uses the 6.5V reference output, a transfer request output, and 3 inputs for clock, data and switch. The outputs for the general purpose section are reduced to 23 in number. The inputs are all available through the filter or after processing by the KYK-13 interface. Alternate interface voltages are available; for example 5.85V. http://www.dyneng.com/ip429.html

IP-ARINC 429 P-429-1 2 RX and 1 TX channel IP-429-2 4 RX and 2 TX channels IP-429-3 6 RX and 3 TX channels IP-429-4 8 RX and 4 TX channels Each receiver channel is programmable to the high and low 429 operating frequencies [12-14.5 KHz., or 100 KHz.], data length of 25 or 32 bits, data filter address, and parity. Interrupt or polled operation.

Each transmitter features an 8x32 bit word FIFO to offload the CPU with set and forget operation. The transmit rate is programmable to allow inter-operation with many equipment types. The data word length is programmable to be 25 or 32 bits. Interrupt or polled operation.

An additional parallel port: 8 bits input, and 4 bits output allow for custom interfacing requirements. The drive side is supported with BCT125's [64 mA sink] and receive side is through a 33 ohm resistors.

The many programmable features allow the IP-429 interface to be used with ARINC 429 and other standards. In addition to ARINC-429 the interface can be used for ARINC standards 571, 575, 706. The other standards are handled with different software selections.

The IP-429 has undergone flight and full chamber testing by one of our customers.

Embedded Hardware and Software Solutions Page 17 http://www.dyneng.com/ipdbgbus.html

IP-Debug-Bus Specialized extender card which is optimized for testing IP Modules. The bus signals are accessible via test points. The test points include multiple ground locations and .025 sq. posts for ease of connection to your logic analyzer or scope. The test points are labeled for easy identification.

Power is controlled with an on-board switch to allow the IP Module to be powered down without turning off the host system. The logic signals are automatically isolated with 'quick switch' technology when the power is disabled. LEDs indicate when power is applied. A remote connector position is supplied to allow a remote switch to control the power switching for production environments. 'Self healing' fuses are provided for power protection. A

reset switch is provided to allow resetting the IP without affecting the system. http://www.dyneng.com/ipdbgio.html

IP-Debug-IO II Do you need to connect your system to an IndustryPack while debugging? You can connect the IP IO connector to the rest of your system and have access to the component side of the IP. The IP-DEBUG-IO terminal is designed to allow test circuits to be added to simulate part of the system that may not be available. For example: terminations or loop-back connections.

Test points are provided on each of the 50 IO lines. The test points allow wire wrap connections and scope or analyzer probes to be used. High quality ejecting ribbon cable connectors [2] are supplied to make isolation and connection to the system a snap. The IP-Debug-IO card can be installed as a bridge between cable segments to provide test points. PC power connector and matching 4 pin header for easy connection to a power supply. 28 position PLCC , SO8, and Oscillator footprints with power and headers provided to allow circuits to be added to the board. PLCC_28 is set-up for 22V10 installation. Room for socket installation if desired.

Embedded Hardware and Software Solutions Page 18 http://www.dyneng.com/HDRterm50.html

HDRterm50 Ribbon cable headers are commonly used with IP compatible hardware. Ribbon cable is difficult to connect to other hardware, especially if multiple destinations are involved. The HDRterm50 terminal converts from 50 pin ribbon cable to a 50 pin terminal strip. Discrete wires are easily connected with the screw locks on the terminal strip. HDRterm50 comes with DIN rail mounts for ease of use in VME and other environments.

http://www.dyneng.com/IPHardware.html

IP-Mounting Kit The hardware kit provides the necessary fasteners to mount an IP to a carrier. Each kit includes stainless steel hardware: IP Mounting screws (4 flat head screws), Carrier board mounting screws (4 pan head screws), Standoffs. Dynamic Engineering IndustryPack modules are supplied with 1 IP-Mounting-Kit per board. If you loose your screws or if a third party board did not come with the hardware we have them in stock for you. http://www.dyneng.com/HDRribn50.html

HDRribn50 50 pin Ribbon cable with pull tabs and strain relief. Ribbon cable shown has strain relief, pull tabs and is 24" in length. Ribbon cable is available in various lengths and configurations. The ribbon cable is compatible with most IP carriers and the HDRterm50.

Embedded Hardware and Software Solutions Page 19 PMC http://www.dyneng.com/pmc2pci.html

PMC2PCI Save development time by using a PCI card in a PMC slot. The PMC2PCI (PMC to PCI) adapter / carrier converter card provides the ability to install a PCI card into a standard PMC slot. The PMC2PCI has two PCI card slots mounted to a PMC card. One slot can be used at a time with the choice of 3V or 5V IO and 32/33 or 64/66 MHz PCI clocks. Local 10A 3.3V power supply with bipass. http://www.dyneng.com/pmc_parallel_IO.htm

PMC-Parallel-IO Add 64 digital IO lines plus clock and clock enable to one PMC site. High density 68 pin SCSI III front panel connector and back-plane IO provide system wiring options. Each channel is programmable to be an input or output on a channel-by-channel basis. Two IO channels can be used as interrupt generators. Interrupts are programmable to be based on level or edge and active high or low. An external clock and clock enable can be used or the internal clock selected for capturing the Input channels. The registers are mapped as 32 bit words and support byte, word and 32 bit access. All registers are read-writeable. Header for user re-programing of Altera FPGA. The upper12 IO are routed through the FPGA for user applications. http://www.dyneng.com/pmc_parallel_485.html

PMC-Parallel-485 Add 32 [RS-485 /RS-422] differential IO lines to one PMC site. 2 additional differential pairs are available for a clock & clock enable. The signals can be used to capture data with an external reference or programmed to be references for the rest of the system.

Each channel is programmable to be an input or an output. The lower four bits are independent. The rest are programmed on a nibble basis. Programmable termination.

High density 68 pin SCSI III front panel connector and backplane IO provide system wiring options.

The IO channels can be used as interrupt generators. Interrupts are programmable to be based on level or edge and active high or low. The registers are mapped as 32 bit words and support byte, word and 32 bit access. All registers are read-writeable.

An 8 bit user switch is provided to allow custom configurations to be easily and automatically configured with a common software driver. For example; the switch can

Embedded Hardware and Software Solutions Page 20 be read through the status port and used to determine what the RX/TX configuration should be and any special characteristics for that implementation.

All of the data bits pass through the FPGA used to implement the PCI interface. Any or all bits can be used for custom state machine and IO functions. Custom termination options are also available. http://www.dyneng.com/pmc_parallel_485ng1.html

PMC-Parallel-485-NG1 Customized version of PMC-Parallel-485. Design used for system timing synchronization. One card acted as a master and distributed the clock and counter synchronization pulses to the rest of the ‘485s in the system. Each card independently tracked the “time” and stayed in sync with the master card. Master and slave cards selected with software. Two timers with maskable interrupts per card. Interrupt on counter bits changing state for multiple system timers. http://www.dyneng.com/pmc_parallel_485.html

PMC-Parallel-485-NRC1 Customized version of PMC-Parallel-485 with interrupt on change of state capability, upper bits muxed to allow input buffering or discrete outputs, and upper nibble predefined as output. Engineering kit available. Please download the manual for details. http://www.dyneng.com/pmcbis.html

PMC-BiSerial-IO The serial input and output channels are highly programmable and fully independent. The standard interface offers Data, Clock and Strobe. The 20 RS485 channels are programmable as input or output. The programmable output rates and RS422/485 compatibility will interface to a multitude of systems. 16K FIFO per channel Standard. Up to 128 K is available per RX and TX channel. External reference clock input standard. Multiple customerized versions in addition to the standard design. Please see the PMC BiSerial II/III for new designs.

Embedded Hardware and Software Solutions Page 21 http://www.dyneng.com/pmc_biserial_II.html

PMC-BiSerial-II The BiSerial II features completely isolated FIFOs with 32 bit ports for increased adaptability and performance. 32 - 40 MHz 485 buffers with programmable termination and direction can be configured to your systems requirements. An expanded faster FPGA will implement the most complex state-machines. The connector pinouts are the same for the first 20 channels to help with migration of older designs from the original BiSerial to the BiSerial II. Recommended for new designs. Optional Transformers available on 4 channels.

Embedded Hardware and Software Solutions Page 22 http://www.dyneng.com/pmcbis2_ng1.html

PMC-BiSerial-II-NG1 The PMC BiSerial-II NG1 is part of the PMC Module family of modular I/O components by Dynamic Engineering. The PMC BiSerial-II is capable of providing multiple serial protocols. The NG1 protocol implemented provides two full- duplex RS-422 UART interfaces with error detection, two half-duplex RS-485 custom "index" interfaces, external clock input, two clock outputs, and various discrete signal inputs and outputs, all using RS- 485 transceivers.

The transmit data rate is derived from the 31.25 MHz on-board oscillator or external reference clock. The 31.25 MHz clock is divided by 2, 3, 4, 5, 6, 7, or 8 to generate the external clock outputs as well as the Tx clock for the UART and index interfaces.

The receive side of these interfaces uses a doubled (62.5 MHz) clock to sample the input data stream. The receiver uses the clock divisor to determine how many clock periods constitute a received bit period. Windows driver available.

Embedded Hardware and Software Solutions Page 23 http://www.dyneng.com/pmcbis_nvy1.html

PMC-BiSerial-II-NVY1 Updated from original version to use the new BiSerial II board. Uart funtion added and additional processing within the state-machine. Larger FIFOs [128K x32]. Manchester encoded data inputs and outputs. Two output and 4 input channels with software selection of the active channels. Inputs are selectable two at a time. Data is captured and sync patterns tested for alignment as part of a redundant data path for system integrity.

http://www.dyneng.com/pmcbis_bae1.html

PMC-BiSerial-BAE1 The PMC-BiSerial-BAE1 is a customized version used to provide a master system clock or to provide a local RTC with an update from the master. When in target mode a local counter is used to track the time. When serial updates are received from the master unit the local timer is updated to match the master. Counters are 40 bits. Count rate is 2 MHz. Software selection of Master/Target mode. http://www.dyneng.com/pmcbis_ba1.html

PMC-BiSerial-BA1 The PMC-BiSerial-BA1 is a customized version used to provide a bus snoop capability. The GSG/Seeker  launcher/missile traffic. Two protocols are utilized – “UART” and 32 bit data. The received data is time stamped and stored. Auto block detection and programmable interrupts. Transmit capability provided for self-test. http://www.dyneng.com/pmcbis_ps1.html

PMC-BiSerial-PS1 Customized version with four transmit and no receive channels. 5 MHz transmit rate. 16K FIFO channel 0, 4 x 32 FIFO channels 1-3. Reference clock out. Reference strobe on channel 0. LSB first. Fixed sync pattern on channels 1-3. FIFO based sync pattern on channel 0.

Embedded Hardware and Software Solutions Page 24 http://www.dyneng.com/pmcbis_s311.html

PMC-BiSerial-s311 The PMC-BiSerial-S311 implements the Northrop Grumman S-311 interface protocol. This protocol uses a burst clock to shift 18 bits of data. The data changes on the rising edge of the clock and is valid on the falling edge. The first bit is the sync bit, which is always high and the next 8 bits are the upper byte of the data shifted out MSB first. The next bit is the mode bit, which is zero for a data word and one for a command word. The final 8 bits are the lower byte of data shifted out MSB first.

Two additional signals are used in this protocol, request and ready. The request signal is asserted high by the transmitter at least two clock periods before the first clock. The request signal also remains asserted at least two clock periods after the falling edge of the last clock. After request goes low, at least four clock periods must elapse before it is reasserted. The ready signal is asserted high by the receiver when it is ready to receive data i.e. it has been started and the Rx FIFO is not full. The ready signal can remain high between words as long as the receiver is able to receive data.

WindowsNT driver available.

http://www.dyneng.com/pmcbififo.html

PMC-BiFIFO The parallel Input and Output channels are highly programmable and fully independent. The standard interface offers Data, Clock and Strobe. The 32 RS485 channels are programmable as input or output allowing for a variety of implementations. The programmable output rates and RS422/485 compatibility will interface to a multitude of systems. If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface

Embedded Hardware and Software Solutions Page 25 http://www.dyneng.com/pmc_serial.html

PMC-Serial The PMC-Serial features: Exar 854 quad UART and Zilog 85X30 Serial Communications Controller. The Xilinx FPGA provides a 33/32 PCI interface and control for the UART and SCC. The IO from the Quad UART and Serial Communications Controller are routed through the FPGA to provide multiple IO options. The PMC-Serial supports RS232, RS485, RS423 and RS188. The PMC-Serial has options for the UART and SCC reference frequencies, and the capability of adding a reference oscillator to the Xilinx for custom state machine requirements.

http://www.dyneng.com/HDEterm68.html

HDEterm68 Two SCSI II compatible connectors interconnected with a 68 position terminal block. The SCSI connectors are connected to the screw terminals and to each other 1:1. The "in" SCSI connector is connected to the screw terminals and then to the "out" connector. Test point positions and land patterns are provided to support loop-back testing and special termination requirements.

http://www.dyneng.com/pci2pmc.html

PCI2PMC PCI to PMC adapter / converter card provides the ability to install a PMC card into a standard PCI slot. The PCI2PMC has a PMC card slot mounted to a universal 1/2 length PCI card. Suitable for 32 bit or 64 bit bus operation. The PMC user IO connector Pn4 is brought out to two connectors for access (DIN IDC and SCSI II). The PMC front panel connector is mounted though the PCI mountings bracket.

Embedded Hardware and Software Solutions Page 26 http://www.dyneng.com/pciBpmc.html

Updated Features! PCIBPMC PCI to PMC adapter/carrier card with optional Ethernet and/or Serial Ports and an optional Fan. The PCIBPMC adapter card provides the ability to install a PMC card into a standard PCI slot, featuring independent signal levels on each side of the bridge, built in 3.3V supply 32/33 or 64/66 MHz PCI clocks, The bridge insures that multiple PCIBPMC cards can be installed onto the same PCI bus stub.

http://www.dyneng.com/cpci2pmc.html cPCI2PMC The cPCI2PMC has a PMC card slot mounted to a universal 3U 4HP cPCI card. Suitable for 32/33 or 64/ 66 MHz bus operation. The PMC user IO connector Pn4 is optionally connected to J2 for rear panel IO. The PMC bezel connector is mounted though the cPCI-mounting bracket. Individual pins on the JN4 (PN4) connector are accessible when the IO option is specified. cPCI J2 has two definitions - in a 64 bit PCI implementation J2 has the upper A/D & control signals & in a 32 bit PCI implementation J2 has the rear panel IO. With resistor jumpers the IO or the PCI signals can be connected to J2. Please specify -IO, -64, or blank [neither]. http://www.dyneng.com/cpcibpmc.html cPCIBPMC3U64 The cPCIBPMC has a PMC card slot mounted to a 3U cPCI card. Suitable for 32/33 or 64/66 MHz bus operations. Part of User IO [Pn4] is connected to J2 for rear panel Ethernet and serial connections with PrPMC devices. The PMC bezel connector is mounted though the cPCI- mounting bracket. The Bridge isolates the cPCI backplane from the PMC allowing mixed voltage mode cards and to be used and for clock and data width matching.

Embedded Hardware and Software Solutions Page 27 http://www.dyneng.com/HDEcabl68.html

HDEcabl68 SCSI compliant cable with either latch block or screw terminal retention. Cables are stocked in the 3 and 6-foot lengths. Custom lengths and connectors available.

http://www.dyneng.com/pmcextendio.html

PMC-Extendio A two card set with flex cable interconnection. The PMC is available for test or debugging with the component side up. The Flex cables allow for the PMC to be moved. 64 bit PCI bus interconnection. Rated at 33 MHz. With 12” cables. 66 MHz cable length will depend on your system.

Embedded Hardware and Software Solutions Page 28 PCI http://www.dyneng.com/pci_3_ip.html http://www.dyneng.com/pci3ip_xp.html

PCI3IP Why pay for slots you are not using? Use the PCI3IP for embedded control and your favorite IP modules. The PCI3IP is a half size PCI card with 3 IP module slots. The IP modules have independent clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. Two of the slots can be used for a double wide IP. FAST® technology provides an integrated PCI to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 6 under user control. An 8 position dip-switch is provided for board identification and other user purposes. Fused filtered power for each IP module. The PCI3IP is easy to use and has an engineering kit available to speed your integration to success. The PCI3IP XP/2000 drivers are available to support your hardware with a software to software interface. The drivers come with a generic IP driver to use with IPs that do not have an IP level driver available. IP level drivers written for the PCI3IP will also work with other Dynamic Engineering carriers including the PCI5IP, cPCI2IP, PC/104p-4IP and our other planned carriers. http://www.dyneng.com/pci5ip.html http://www.dyneng.com/pci5ip_xp.html

Embedded Hardware and Software Solutions Page 29 other user purposes. Fused filtered power for each IP module. The PCI5IP is easy to use and has an engineering kit available to speed your integration to success. WindowsXP/2000 and Linux drivers are available to support your hardware with a software to software interface. The drivers come with a generic IP driver to use with IPs that do not have an IP level driver available. IP level drivers written for the PCI3IP will also work with other Dynamic Engineering carriers including the PCI5IP, cPCI2IP, PC/104p-4IP and our other planned carriers. http://www.dyneng.com/pci2pmc.html

http://www.dyneng.com/pciBpmc.html

Embedded Hardware and Software Solutions Page 30 http://www.dyneng.com/pmc2pci.html

LVDS_Cable 100 position, .050 MDR/MDR for high speed digital data transmission systems. Matches LVDS 8R and 8T connector.

http://www.dyneng.com/ pci_serial_ecl.html

New! PCI_ECL High speed DMA supported ECL IO Do you feel the need for speed? Differential ECL / NECL is still the interface of choice for high speed in noisy environments. PCI--ECL is a general purpose design with ECL IO and a high speed Xilinx Virtex II Pro to control it. The ECL IO is carefully routed to provide 100 ohm differential impedance and matched length from the pin edge on the D100 connector to the Xilinx [BGA] Ball. All of the TX and RX are matched to allow for high speed designs with tight timing requirements. The top ECL input bit is tied to a clock capable input pin on the Xilinx to allow for an external reference clock. Some of the ECL features include: Xilinx is supported by a programmable PLL, a customer selected oscillator position is supplied, 20 inputs and 20 outputs, the state-machine can be programmed to use any number of the IO, an external FIFO is used to store data from reception or for transmission, the Internal FIFO is to support DMA. The PCI ECL also supports Multi-board operation The reprogrammable FLASH memory stores the Xilinx design file. The JTAG header is used to load the FLASH using the Xilinx standard IMPACT¨ software and parallel download cable. Customizable for NECL and/or PECL Windows 2000/XP driver available.

Embedded Hardware and Software Solutions Page 31 http://www.dyneng.com/pci_lvds.html

PCI_LVDS_8R Capture 8 channels of serialized LVDS [TIA/EIA-644] input into 512 Mb of SDRAM. The channels are grouped two per Receive Xilinx, and 4 per bank of SDRAM. The input data is filtered, then written to the Input FIFOs. The data is read from the Input FIFO by the Latch Xilinx and either written to the SDRAM or the Output FIFO. The Address Generator controls the Latch Xilinx and the SDRAM. The data from the output FIFO can be read with standard target accesses or as a DMA stream. The memory is programmable for size per channel and location. The data to capture is programmable for pattern and quantity. Any number of channels can be active at the same time. The 8R is tested after a 24 hr burn-in at 120F with 250 loops of full memory all channel data transfer [64 M per channel] and then again at 40F. Two power configurations are available – on-board regulator or backplane supplied 3.3V. The default configuration is 3.3V. Please specify 5V operation when required.

WindowsNT and 2000/XP drivers available.

Embedded Hardware and Software Solutions Page 32 http://www.dyneng.com/pci_lvds_8T.html

PCI_LVDS_8T Transmit 8 channels of serialized LVDS [TIA/EIA-644] . 9 Xilinx devices, FIFOs, and 512 Mb of SDRAM support transmitting data to the outputs. DMA transfers support storing of the data to the SDRAM memory. A direct output channel from host memory mode is supported. Multiple looping capabilities are supported including continuous, looped, and expanded. The memory is programmable for size per channel and location. The data to transmit is programmable for location, quantity, and loop count. Several built in loop options including initial pattern, looped pattern followed by ending pattern. Any number of channels can be active at the same time. Each channel can be programmed independently. The 8T is tested after a 24 hr burn-in at 120F with 250 loops of full memory all channel data transfer [64 M per channel] and then again at 40F. Two power configurations are available – on-board regulator or backplane supplied 3.3V. The default configuration is 3.3V. Please specify 5V operation when required. WindowsNT and 2000/XP drivers available.

Embedded Hardware and Software Solutions Page 33 http://www.dyneng.com/pci_altera_485.html

PCI_Altera The PCI-Altera design is for the advanced user who wants to implement their Altera design. PCI_Altera_485 comes with everything you need to load your Altera program into the 20K400E. Fantastic for development, simulation, special purpose interfaces, multiple serial and / or parallel channels. The PCI-Altera makes the implementation and use of the 20K400E easy. Larger Altera parts are available with the same footprint allowing an upgrade path should one be necessary. The design comes with the basic features built in and the specific features ready for you. The PLX 9054 and Xilinx take care of the PCI interface for initial loading of the Altera, and DMA transfer of data into and out of the FIFOs. The Altera controls 40 programmable RS- 485 or LVDS and 12 TTL IO. Each of the RS-485/LVDS channels is programmable for direction, termination and function. The 12 TTL IO can be inputs or outputs. Eight Cypress 22393 PLLs support the Altera providing the ability to synthesize multiple reference rates. The only thing missing is your input in the form of a state- machine, simulated system, asynchronous or synchronous data processing etc. The engineering kit comes complete with the Altera pin definitions, Windows2000/XP® Driver, reference Altera design, front panel break-out and cable. The driver comes with a generic Altera driver which can be used to control your specific implementation. Custom Altera level drivers are available. The driver also comes with a reference user application which runs the Dynamic Engineering ATP for the PCI-Altera. The user application can be used as a reference for your software effort, and gaining confidence that your hardware and software are properly installed.

Embedded Hardware and Software Solutions Page 34 http://www.dyneng.com/ HDEterm100.html

HDEterm100 The terminal provides an easy way to get from a high density SCSI connector to discrete wires. For example with the PCI-Altera-485 design a standard D100 cable can be used to connect the PCI-Altera-485 to the HDEterm100 and then to the system wiring via the terminal strips provided. The HDEterm100 provides a space efficient, low cost method of interconnecting the control electronics to the rest of the sensors, IO, machinery etc. http://www.dyneng.com/ HDEcabl100.html

HDEcabl100 The high density 100 pin LVDS SCSI II/III connector is being used for purposes in addition to SCSI interfaces because of board and front panel space limitations. The HDEcabl100 provides a SCSI compliant cable with either latch block or screw terminal retention. The cables are stocked in the 3 and 6 foot lengths and are available in custom lengths to OEM customers. HDEcabl100 matches the HDEterm100 and PCI-Altera-485. http://www.dyneng.com/ pci.html#PCI2cPCI-32

PCI2cPCI-32 Install a cPCI board into a PCI slot. This adapter supports 32-bit cPCI cards.

http://www.dyneng.com/ pci.html#PCI2cPCI-64

PCI2cPCI-64 Install a cPCI board into a PCI slot. This adapter supports 64bit cPCI cards.

Embedded Hardware and Software Solutions Page 35 CPCI

http://www.dyneng.com/pim_carrier.shtml

PIM-Carrier-Dual The PIM Carrier facilitates rear panel IO in cPCI systems using PMC's. The PIM- Carrier has 2 PIM sites. PIMs provide PMC front panel IO at the rear panel. Signals routed from P14 through J3 to PIM and P24 through J5 to PIM.

http://www.dyneng.com/pim_parallel_io.shtml

PIM-Parallel-IO Route the Pn4 “user IO “ PMC IO to the backplane with a PIM-Carrier and PIM. Re-create the PMC-Parallel-IO bezel. The Bezel, Connector and connections are the same as the PMC- Parallel-IO to allow the same cables to be used on the front panel bezel or the PIM bezel. Clock and Clock enable not routed due to Pn4 limitations. 4 extra pins are connected to +5V and Ground. +5V is fused with a "self healing" fuse.

Embedded Hardware and Software Solutions Page 36 http://www.dyneng.com/pim_universal_io.html

PIM-Universal-IO All 64 IO are routed 1:1 [matched length] to the PIM bezel connector. The extra 4 pins are used for +5V and ground reference. The +5V is fused with a "self healing" fuse. Two signal grounds are provided. The connector is a 68 pin SCSI II with latch-blocks. Requires a PIM Carrier.

http://www.dyneng.com/cpci2ip.html cPCI2IP Use the cPCI2IP for embedded control and your favorite IP modules when you need 2 in a slot or have a 3U chassis. The cPCI2IP is a 3U 4HP size cPCI card with 2 IP module slots. The IP modules have independent clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. The slots can be used for a double wide IP. FAST® technology provides an integrated cPCI to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 8 under user control. An 8 position dip-switch is provided for board identification and other user purposes. Fused filtered power for each IP module. The 50 pin header connectors provide IO through the bezel and cable options for discrete or ribbon cable wiring. Optional J2 connectivity is available for users with a 32 bit PCI bus. –J2 The cPCI2IP is easy to use and has an engineering kit available to speed your integration to success.

Embedded Hardware and Software Solutions Page 37 http://www.dyneng.com/cpci4ip.html cPCI4IP The cPCI4IP provides four IndustryPack¨ slots in one 6U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in each slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. Windows® driver available

http://www.dyneng.com/cpci2pmc.html cPCI2PMC The cPCI2PMC has a PMC card slot mounted to a universal 3U 4HP cPCI card. Suitable for 32/33 or 64/ 66 MHz bus operation. The PMC user IO connector Pn4 is optionally connected to J2 for rear panel IO. The PMC bezel connector is mounted though the cPCI-mounting bracket. Individual pins on the JN4 (PN4) connector are accessible when the IO option is specified. cPCI J2 has two definitions - in a 64 bit PCI implementation J2 has the upper A/D & control signals & in a 32 bit PCI implementation J2 has the rear panel IO. With resistor jumpers the IO or the PCI signals can be connected to J2. Please specify -IO, -64, or blank [neither]. http://www.dyneng.com/cpcibpmc.html cPCIBPMC3U64 The cPCIBPMC has a PMC card slot mounted to a 3U cPCI card. Suitable for 32/33 or 64/66 MHz bus operations. Part of User IO [Pn4] is connected to J2 for rear panel Ethernet and serial connections with PrPMC devices. The PMC bezel connector is mounted though the cPCI-mounting bracket. The Bridge isolates the cPCI backplane from the PMC allowing mixed voltage mode cards

Embedded Hardware and Software Solutions Page 38 and to be used and for clock and data width matching.

PCI2cPCI-32 Install a cPCI board into a PCI slot. This adapter supports 32-bit cPCI boards

http://www.dyneng.com/ pci.html#PCI2cPCI-64

PCI2cPCI-64 Install a cPCI board into a PCI slot. This adapter supports 64bit cPCI cards.

Embedded Hardware and Software Solutions Page 39 PC/104p http://www.dyneng.com/pc104p4ip.html

PC/104p-4IP Use the PC/104p-4IP for embedded control and your favorite IP modules when you need 4 in a PC/104p stack. The PC/104p- 4IP is a special mechanical card with 4 IP module slots. The PC/104p connector placement is standard. The overall dimensions are larger than standard PC/104p. The IP modules have independent clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. The slots can be used for a double wide IP. FAST® technology provides an integrated PC/104p to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 8 under user control. An 8 position dip-switch is provided for board identification and other user purposes. Fused filtered power for each IP module. The 50 pin header connectors provide IO and cable options for discrete or ribbon cable wiring. The PC/104p-4IP is easy to use and has an engineering kit available to speed your integration to success. Windows® driver available.

Embedded Hardware and Software Solutions Page 40 PC/104p-IP Single slot IP carrier for PC/104p. The IP module has clock selection (8/32 MHz), interrupt, bus error timer, and full support for IO, ID, Mem and Int accesses. FAST® technology provides an integrated PC/104p to IP bus interface. The integrated interface features automatic 32 bit PCI conversion to 16 bit IP module. LEDs are provided on the IP power levels, IP acknowledge, and an additional 8 under user control. An 8 position dip- switch is provided for board identification and other user purposes. Fused filtered power for the IP module. The 50 pin header connector provides IO and cable options for discrete or ribbon cable wiring. The PC/104p-4IP is easy to use and has an engineering kit available to speed your integration to success. Windows® driver available.

http://www.dyneng.com/pc104p_biserial.html

PC/104p-BiSerial 32 bit PC104p Module support * Increased adaptability and performance * Expanded faster FPGA will implement the most complex state-machines * The PC/104p-BiSerial is easy to use and has an engineering kit available to speed your integration to success. Ported from the PMC BiSerial II, & adding in the latest technology has created the PC/104p- -BiSerial. The PC/104p-Biserial features: completely isolated FIFOs with 32 bit ports for increased adaptability and performance. 16 - 40 MHz 485 buffers with programmable termination and larger, faster FPGA to implement the most complex state- machines. Many of the designs implemented for the PMC and IP versions can be ported to the PC/104p. The Biserial family is an ideal application solution for: telemetry, Manchester encoding/decoding, command & control, interface simulation, "glue" between incompatible systems, radar systems, industrial interfaces, inventory, optical recognition, airborne, ground based, and ship based. The BiSerial can be used to simulate a target system like an airplane, missile or other vehicle to interact with the equipment that would be connected to the target systems. Many times having a computer-based interface is more convenient than having the actual target application. Test, debugging, diagnostics etc. can be computer driven using the BiSerial much more easily than the "real" system in many cases. Consider the BiSerial family for your interfacing and support requirements.

Embedded Hardware and Software Solutions Page 41 The Biserial features include: 2 fully independent and highly programmable RS-485 / RS-422 IO channels The two channels can have the same or different protocols. Manchester encoding and decoding, standard serial [UART], control, command, instrumentation, and custom protocols can be implemented, Each channel has a separate FIFO with 16Kbytes standard up to 512Kbytes as an option. 16 transceivers, Eight TTL IO, programmable PLL, oscillator position, and PCI clocks to choose from for a variety of clocking options The driver supports programming the PLL. Board options also include: LVDS, DAC and ADC channels. There are 4 DAC, and 4 ADC channels, which can be populated with 200 KHz. 16 bit devices. The analog and TTL IO can use the external FIFOs or the internal Block RAM when smaller FIFOs are needed. The 50 pin header connectors provide IO & cable options for discrete or ribbon cable wiring.

Embedded Hardware and Software Solutions Page 42 Available Now http://www.dyneng.com/pci2pc104p.html

PCI2PC/104p Two slots to choose from. Mount a PC/104p card in a PCI slot with component side up for debugging or down for production. PCI2PC/104p shown in production mode.

Other http://www.dyneng.com/s_a_relay.html

S-A-Relay Allows undetectable active monitoring and data altering of two Ethernet (RJ-45) lines. The Stand Alone Relay accepts a regular PC style power connector that powers two relays. Upon power failure, the relays disengage the 2 Ethernet lines so as to not interrupt communication on the Ethernet lines. A CPLD allows for pass through and bypass of Ethernet signals. 10/100 Ethernet compatible. The CPLD comes pre- programmed with the standard program for controlling the relays with pass- through and bypass modes. The CPLD can be re-programmed via the JTAG header to have custom operation. The CPLD has many unused pins which are brought to headers for system wiring. The CPLD is a Xilinx 9536.

Embedded Hardware and Software Solutions Page 43 http://www.dyneng.com/extender.htmll

IEEE Extender The IEEE extender card, referred to as board PWB1000281-03. Extender card to allow for testing and debugging of the chassis assembly. This board was originally an Intel design that Dynamic Engineering was authorized by Intel to re-create. Our design upgraded the board, added test points and improved functionality features such as a silkscreen, improved traces and gold fingers. Each test point is also numbered. The board was redesigned for use in a Lockeed system for motherboard insertion to the NASA-NOAA (Tiros) command generator which allows testing and debugging of the chassis assembly. Please contact Dynamic Engineering for your custom extender cards, and other “unusual” product requirements. http://www.dyneng.com/me.html

NuBus Extender Software testing and hardware debugging are easier and faster with MacExtender! This unique product will raise your card above the logic board, allowing you access to both sides of your hardware. Now you can have testpoints on all of the active NuBus signals. MacExtender includes power and ground planes, high- quality panduit connectors, a front panel for additional support, .025" square posts for scope and logic analyzer, and trouble-free insertions. Clean power won't add to your system noise.

Embedded Hardware and Software Solutions Page 44