Designing a Reconfigurable Embedded Processor
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AN ABSTRACT OF THE THESIS OF John Mark Matson for the degree of Master of Science in Electrical and Computer Engineering presented on May 2. 2003. Title: Designing a Reconfigurable Embedded Processor. Abstract Redacted for Privacy Ben Lee The growth of applications for embedded processors has spawned a need for highly configurable devices. Custom microprocessors have long life cycles for a fast paced market, where as off-the-shelf designs often do not provide the level of configuration, nor the ability to allow system-on-chip designs. This paper presents a description for a software environment that allows designers to provide configuration options for a design, and responds by dynamically reconfiguring the environment to provide a ready to test design. A background survey is provided on current embedded RISC architectures, along with a proposed new embedded ISA and a cycle-level simulator. Justification is presented for a new instruction format to reduce code size with little loss to performance. A manual is also provided for the new ISA. Designing a Reconfigurable Embedded Processor By John Mark Matson ru:I submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science Presented May 2, 2003 Commencement June 2003 Master of Science thesis of John Mark Matson presented on May 2, 2003. APPROVED: Redacted for Privacy Major Professor, representing Electrical and Computer Engineering Redacted for Privacy Director of Schoobef1ectrica1 Engineering and Computer Science Redacted for Privacy Dean of the"dradtate School I understand that my thesis will become part of the permanent collection of Oregon State University libraries My signature below authorizs release of my thesis to any reader upon Redacted for Privacy John Mark Matson, Author TABLE OF CONTENTS Page 1. Introduction............................................................................................ 1 2. Background............................................................................................ 2 3. Profiling................................................................................................. 3 RegisterFile Size................................................................................. 4 Instruction Length...............................................................................5 Instruction Profiling: The ARM-PISA Comparison...........................7 4. Definition of the X32V ISA.................................................................11 DefaultMode..................................................................................... 12 LightMode........................................................................................ 12 UltraLight Mode............................................................................... 12 Word Boundary Study.......................................................................15 5.Creation of the X32V Cycle Accurate Simulator................................19 InstructionFetch................................................................................ 19 Instruction Decode............................................................................ 20 Execute, Memory Access, Write Back..............................................21 Forwarding........................................................................................ 21 Memory............................................................................................. 21 SystemCalls...................................................................................... 21 TABLE OF CONTENTS (Continued) Page Statistics.............................................................................................22 6. Future Work.........................................................................................23 7. Conclusion...........................................................................................24 Bibliography............................................................................................. 25 Appendices................................................................................................26 Appendix A: X32V ISA Manual.......................................................27 Appendix B: ARM SS and PISA SS Configuration Table...............92 Appendix C: ARM SS and PISA SS MPEG 4 Benchmark Results.. 93 LIST OF FIGURES Figure Page 1. 32-bit Instruction Format..................................................................13 2. 24-bit Instruction Format..................................................................13 3. 16-bit Instruction Format..................................................................13 4. Default Mode....................................................................................14 5. Light Mode........................................................................................14 6. Ultra Light Mode..............................................................................15 7. Code Size for each X32V Mode.......................................................16 8. Code Size Reduction.........................................................................17 9. Cycle Overhead.................................................................................18 10. Instruction Fetch Example..............................................................20 11. The X32V Simulator and Compiler................................................22 LIST OF TABLES Table Page 1. Various Embedded Processor Instruction Lengths.............................5 2. ARM and PISA MPEG 4 Benchmark Results....................................8 3. ARM Statistics Profile......................................................................10 4. PISA Statistics Profile.......................................................................10 Designing a Reconfigurable Embedded Processor 1. Introduction Designers of embedded products are presented with two options for a microprocessor: design their own, or purchase an off-the-shelf model. Designing a microprocessor from scratch is not very cost effective for a product that may have a shelf life of only a year. It can also push the design cycle out a few extra quarters, which will make or break a product in a highly competitive market. Off- the-shelf solutions come in a variety of different formstypical microprocessor, FPGA, CPLD, etc. The designer can choose from options such as memory size, I/O size, physical size, speed and more. However, with the advent of Systemon Chip, it is becoming tough to meet designer's requirements with an off-the-shelf solution. Power, speed, area, and architectural requirements cannot meet every design need with a 'flavor of the month' approach. Ideally, a designer would have an immediate turnaround between when design requirements are made and when first silicon arrives for testing.Those goals, however, are unreasonable. What is reasonable is a software environment that could take the same design requirements and produce a ready-to-simulate design immediately. Simulations could then give the designer foresight into how the design will perform, where potential bottlenecks are, and the ability to experiment with new ideas that would otherwise be cost ineffective. 2. Background The goal of this project is to design a software environment where a designer can provide design requirements, and the environment will dynamically change (reconfigure) to provide a ready-to-test design.Examples of design requirements are caches, floating-point units, digital signal processing units, multiply and accumulate units, and more. User definable instructionsare also available for controlling the additional hardware and for creating specialized operations such as multimedia instructions. The software environment is comprised of three major components:a core Instruction Set Architecture (ISA), a compiler, and a simulator. Each of these components is an integral part of the environment and deserves discussion. The designer should have the basic building blocks of a microprocessor available to expand upon; otherwise too much time is spent on recreating functionality that does not change from one design to another. Therefore,a core set of instructions and pipeline definition are the framework for the environment. The core ISA allows for the completion of virtually any design, while the additional hardware, instructions, and other parameters allow for enhanced performance. A compiler is also required to transform high-level code into machine executable instructions, and should handle the creation of new instructions to control additional hardware.The compiler is not presently completed and is 3 beyond the scope of this paper. However, it will be referred to and the reader should be aware of its purpose. Lastly, a simulator is needed to test and collect statistics on the design. The simulator should provide cycle-level accurate data on precisely how information moved through the machine during execution.The designer then uses this data to verify functionality and performance. This paper describes the development of the core ISA and simulator, and is broken down as follows: Section 3: Profiling; Section 4: Defmition of the X32V ISA; Section 5: Creation of the X32V Cycle Accurate Simulator; Section 6: Future Work; Section 7: Conclusion; Section 8: References; and Section 9: Appendix: AX32V ISA Manual, BARM and PISA SimpleScalar Configuration Table, and CARM and PISA SimpleScalar MPEG 4 Benchmark Results. 3. Profiling Before justifying the creation of an embedded