NaturalNatural EvolutionEvolution inin TheThe EmbeddedEmbedded WorldWorld

Tom Wang Manager, ARM Marketing Jan., 2008

Confidential 1 Our Vision ARM designs technology that lies at the heart of advanced digital products

222 ARM’s Activities

Connected Community Development Tools Software IP

Processors memorymemory System Level IP: Data Engines SoCSoC Fabric 3D Graphics

Physical IP

333 The ARM Strategy The SoC must enable the device manufacturer to produce highly desirable products

Software to bring the The CPU is at system alive and to the heart of a maximise the System on Chip performance of the system Software O E Ms EMs Processors O

System on Chips Software tools, ESL Systems require high tools and models to Tools and Physical IP performance Fabric target software onto OEMs along with high the processors in the quality Physical IP system

444 ARM Cortex Family of Processors Bringing the benefits of architectural innovation across the spectrum

ARM Cortex- Series: ƒ A Cortex-A8 ƒ Applications processors for complex OS and user applications

ƒ ARM Cortex-R Series: Cortex-R4F ƒ Embedded processors for real-time systems Cortex-R4

ƒ ARM Cortex-M Series: Cortex-M3 ƒ Deeply embedded processors optimized for Cortex-M1 microcontroller and low-power applications

555 ARM Processor Portfolio

Leading the industry in ARM Cortex performance and low power “Intelligent Computing”

2000 Cortex-A8

1500

1000

DMIPS x4

ARM1176JZF-S Cortex-R4F 750 Cortex-R4 ARM11 MPCore

500 ARM1026EJ-S ARM926EJ-S 250 ARM7TDMI ARM968E-S SC100 Cortex-M3 Cortex-M1

2007

666 ARM Processor Public Licensees

Processor Total # Public licensees Family/Core Licenses Cortex Family 23 Cortex-A8 7 Freescale, Matsushita, Samsung, ST, TI Cortex-R4/R4F 8 Broadcom, TI Cortex-M3 7 Actel, Broadcom, Luminary, ST, TI ARM11 Family 53 LSI, NEC, Qualcomm, Sunplus, Toshiba ...... ARM11 MPCore 10 NEC, Nvidia, Renesas, Sarnoff CoreSight 22 Broadcom, Philips, Samsung ……. ARM9 Family 223 ADI, Fujitsu, Infineon, Sharp, Sony, TSMC ……. ARM7 Family 148 Atmel, Cnxnt, Intel, Mediatek, National, SiRF ….

777 Investing in R&D ƒMajor challenges can only be met by significant, ongoing investments ƒNeed integrated solutions ƒ ARM continues to invest over a vast spectrum ƒ From 1GHz+ processors to 8-bit MCU replacement ƒ Optimized 90, 65 and 45nm low power libraries ƒ Software, tools, Fabric, Audio & Graphics processors ƒARM’s model allows this to be shared across the Partnership

888 Market Driven Roadmaps

Central Product Definition R&D Project Approval

Roadmap Investment ~ $117m p.a.

Roadmaps created by divisions from market input and innovation

999 Processors for All Applications

H Cortex-A9 MPCore 2000+ DMIPS Multi-Proc

Applications Cortex-A8 2000+ DMIPS Uni-proc

Processor ARM11 MPCore 600+ DMIPS Multi-Proc Market ARM1176J(F)-S 600+ DMIPS Uni-Proc

L ARM926EJ-S 250+DMIPS Uni-Proc

ARM1156T2(F)-S 600+ DMIPS Uni-Proc H Real-Time ARM946E-S Cortex R4(F) 600+ DMIPS Uni-Proc Embedded ARM968E-S Market L 150+ DMIPS Uni-Proc ARM7TDMI 100+ DMIPS Uni-Proc

Microcontroller H ARM7TDMI Cortex-M3 & FPGA Market L Cortex-M1

101010 Cumulative Processor Licenses

ARMv7 Cortex-A9 4

ARMv6 Cortex-A8 ARM11TM 9* Family 58

ARMv5 Cortex-R4 10 233 ARM9TM ARMv4 Family Increasing Performance Cortex-M3 11* ARM7TM Family

151 Note: A further 26 licenses have been signed for ARM10TM and SecurCoreTM family processors, and Xscale/StrongARM.

* One additional partner has access to Cortex-A8 and Cortex- M3 under a subscription license

111111 ARM Physical IP Products ƒ Library platforms Standard cells ƒ Pervasive SoC IP ƒ Embedded memory ƒ I/O functionality MemoryMemory High-speed interfaces ••ClassicClassic ƒ ••MetroMetro MemoryMemory ƒ DDR ••AdvantageAdvantage DDRDDR ƒ Serial PHYs SerialSerial PHYsPHYs

StandardStandard CellsCells ••SageSage ••MetroMetro MemoryMemory ••AdvantageAdvantage

I/OI/O CellsCells

121212 Cumulative Physical IP Licenses 1* 6 45 nm 3

5 65 nm 3 20

24 90 nm 4 31 9 18 26 130 nm 47 18 24 2 Increasing Complexity 180 nm 62 Metro Advantage Classic Velocity 27 SOI 250 nm * 45nm SOI License signed early in Q4

131313 Performance/Power Flexibility

Performance ARM1176JZ-S Performance Platform

ARM1176JZ-S

ƒAdvantage-HS Mainstream Platform ƒ90G Worst case ƒ90G Worst Performance ƒ620MHz ƒ320MHz Boost ƒ0.45mW/MHz ƒ0.25mW/MHz ƒ2.65sq mm ƒ1.55sq mm Power/Area Reduction

Density Optimized Platform

All data estimated for full implementations Power

141414 RealView® Tools for Entire Design Flow

IP Creation Core Generator Architectural Exploration SoC Designer

Microcontroller Software Development µVision IDE and ULINK Pre-silicon Software Development Development Suite and SoC Designer Applications Development Hardware/Software Development Suite and Integration System Generator Software Optimization Development Suite and Profiler, ICE & Trace and System Generator ICE & Trace

151515 Applications Processor Roadmap

ARM Cortex “Intelligent Computing”

2000 Cortex-A8

1500

1000

DMIPS x4

ARM1176JZF-S 750 ARM11 MPCore

500 ARM1026EJ-S ARM926EJ-S 250 ARM7TDMI ARM968E-S SC100

2007

161616 ARM1176JZ(F)-S

ƒ 620 MHz ARM11 Applications processor ƒ Fast, 8-stage pipeline ƒ Dynamic Branch Prediction & Return stack ƒ Optional Vector Floating Point ƒ ARMv6Z Architecture ƒ SIMD Media extensions, Jazelle for Java ƒ Enhanced Real-time performance (Fast Interrupt Mode / VIC support) ƒ IEM Enabled ƒ Supports multiple voltage domains (Dormant Mode) and Voltage Scaling ƒ ARM TrustZone™ ƒ Architecture extensions for CPU and system security ƒ High Performance AXI Memory System ƒ Configurable I & D Caches and TCMs with dedicated 64-bit DMA

0.13um process 90nm process 90nm GT process

PPA Speed Opt Area Opt Speed Opt Area Opt Speed Opt

Standard Cells SAGE-HS Artisan Advantage-HS Metro Advantage

Memories - HSHD Optimised Metro Advantage

Frequency ( MHz ) 364 317 610 320 750

Area with cache (mm2) 6.46 5.51 2.54 1.42 2.1

Area without cache (mm2) 4.77 3.61 1.89 0.82 1.46

Cache size 16K/16K 16K/16K 16K/16K 16K/16K 16K/16K

Power with cache (mW/MHz) 1.29 1.24 0.36 0.25 0.568

Power w/o cache (mW/MHz) 0.58 0.50 0.29 0.18 0.465

** The above numbers are either quoted from fully floorplanned layouts/synthesis trials or scaled with respect to process and library performance

171717 ARM11MPCore

ƒ Configurable multiprocessor with 1 to 4 processors ƒ 16K to 64K caches across each processor ƒ Dual or single 64-bit AMBA 3 AXI bus ƒ Configurable VFP unit for each processor ƒ ARMv6K Architecture ƒ Thumb, Jazelle, DSP extensions and SIMD ƒ Energy management ƒ Standby, dormant and power off states for each processor ƒ Intelligent Energy Manager (IEM) ƒ High performance memory system ƒ Cache coherence, L1 sharing, cork-screw cache memory design ƒ Reduced software complexity, standard OS view ƒ Asymmetric (AMP) and Symmetric (SMP) multiprocessing

90nm process

PPA Speed Opt Area Opt

Standard Cells Advantage-HS Metro

Memories Optimised Metro

Frequency (MHz) 608 320

Area with cache (mm2) 2.22 1.46

Area without cache (mm2) 1.56 0.90

Cache size 16K/16K 16K/16K

Power with cache (mW/MHz) 0.32 0.23

Power w/o cache (mW/MHz) 0.27 0.18

** The above numbers are either quoted from fully floorplanned layouts/synthesis trials or scaled with respect to process and library performance

181818 Cortex-A8

ƒ High Performance Applications processor ƒ Superscalar pipeline offers 2,000+ DMIPS ƒ Integrated L2 Cache with configurable size (0K-1MB), ECC ƒ High performance with excellent code density ƒ Thumb-2 hybrid 16-32-bit instruction set ƒ Architecture extensions for CPU and system security ƒ TrustZone™ Secure transactions & Digital Rights Management (DRM) ƒ Multimedia and Signal Processing Architecture ƒ NEON™ provides over 2x Performance of ARMv6 SIMD ƒ OpenMAX library and API’s for fast software development ƒ Efficient Run Time Compilation Target ƒ Jazelle-RCT: Target for Java. Memory footprint reduced up to 3x ƒ Can also target languages such as Microsoft .NET MSIL, Python

65nm LP process 65nm G+ process

PPA Optimized Synthesized Optimized Synthesized

Standard Cells Advantage-CE Advantage-HS Advantage-CE Advantage-HS

Memories Custom Advantage** Custom Advantage**

Frequency (MHz) 660-700 500-550 1.1 GHz+ 800+

Area with cache (mm2) 3.86 4.2 3.86 4.2

Area without cache (mm2) 2.79 3.1 2.79 3.1

Cache size 32K/32K 32K/32K 32K/32K 32K/32K

Power with cache (mW/MHz) 0.58 0.75 0.43 0.55

Power w/o cache (mW/MHz) - - - -

** Optimized instances of Advantage RAMS Optimized data scaled from 90G Area includes L1 RAMS, L2 control. Excludes NEON, ETM, L2 RAMS 65 GP synthesized data scaled from 65LP

191919 Embedded Processor Roadmap

ARM Cortex “Intelligent Computing”

Cortex-R4 Cortex-R4F

MIPS) ARM1156T2F-S

ARM1026EJ-S

ARM966E-S Performance (D ARM946E-S ARM968E-S ARM7TDMI ARM7EJ-S Cortex-M3 ARM996HS Cortex-M1 ARM7TDMI-S

2006 2007

Worst case conditions 202020 Cortex-M3

ƒ Cortex-M3 for cost-sensitive, low-power 32-Bit devices ƒ Complete processor for microcontroller and low cost applications ƒ Thumb-2 technology for greater performance and code density ƒ Hardware divide instructions for control applications ƒCortex-M3 includes configuration options for application fit ƒ Integrated NVIC for industry leading interrupt handling ƒ Extensive debug architecture with up to 8 hardware breakpoints ƒ Optional Memory Protection Unit (MPU) ƒFlexible bus interfaces for easy system integration

0.13um process 90nm process

CM3 Core Speed Opt Perf Opt Area Opt Speed Opt Perf Opt Area Opt

Standard Cells SAGE-X SAGE-X Metro Advantage Advantage Advantage

Frequency (MHz) 135 100 50 191 100 50

Area without cache (mm2) 0.43 0.24 0.21 0.21 0.14 0.13

Power w/o cache (mW/MHz) 0.14 0.079 0.07 0.07 0.044 0.04

Cortex-M3 Processor 0.13um process 90nm process Minimum configuration Speed Opt Perf Opt Area Opt Speed Opt Perf Opt Area Opt

Standard Cells SAGE-X SAGE-X Metro Advantage Advantage Advantage

Frequency (MHz) 135 100 50 191 100 50

Area without cache (mm2) 0.74 0.46 0.38 0.37 0.27 0.25

Power w/o cache (mW/MHz) 0.165 0.094 0.084 0.083 0.051 0.047

** The above numbers are quoted from fully floorplanned layouts/synthesis trials

212121 Cortex-M3 Performance

Comparative EEMBC Performance (per MHz)

180% ƒCortex-M3 offers substantial performance and 160% Larger is better code size benefits over the ARM7TDMI-S 140% 120% without the need for complex interworking of 100% Thumb & ARM modes 80% 60% 40% ƒDhrystone Benchmarks 20% Cortex-M3 1.25 DMIPS/MHz 0% ƒ AutoIndy Consumer Networking Office Telecom ƒ7TDMI-S 0.93 DMIPS/MHz (ARM) ARM7TDMI-S ARM966E-S Cortex-M3 0.74 DMIPS/MHz (Thumb) ƒ966E-S 1.11 DMIPS/MHz (ARM) Comparative EEMBC Code Size 0.96 DMIPS/MHz (Thumb) 130% 120% Smaller is better ƒARM7TDMI-S & ARM966-S 110% 100% ƒResults are based on ARM 32-Bit Code. 90% Thumb 16-Bit code would result in similar 80% ƒ 70% code size to Cortex-M3 but performance 60% would fall substantially 50% 40% 30% ƒARM966E-S is a five-stage pipeline and can AutoIndy Consumer Networking Office Telecom achieve a higher maximum frequency than the ARM7TDMI-S ARM966E-S Cortex-M3 Cortex-M3.

EEMBC Benchmark Data is Uncertified

222222 Cortex-R4(F)

ƒ Highly efficient mid-range embedded processor ƒ Selective superscalar pipeline ƒ Thumb-2 for high performance with excellent code density ƒ FPU optimised for SP (Cortex-R4F) ƒ Class-leading 1.60 DMIPS/MHz ƒ Highly configurable for optimum fit to application ƒ Configurable caches, TCMs and MPU ƒ Flexible TCM architecture ƒ Up to three, 64-bit interfaces ƒ No need to split instruction/data ƒ Parity and ECC support ƒ Designed for ease of integration ƒ Single 64-bit AMBA-3 AXI master interface ƒ Integrated AMBA-3 AXI DMA port 0.13um process 90nm process

PPA Speed Opt Speed Opt Area Opt

Standard Cells Sage-HS Advantage-HS Advantage Advantage Metro

Memories HS Advantage Advantage Advantage Metro

Frequency (MHz) 300 500 400 304 210

Area with cache (mm2) 3.35 2.31 1.72 1.17 1.3

Area without cache (mm2) 1.99 1.66 1.14 0.81 0.7

Cache size 16K/16K 16K/16K 16K/16K 8K/8K 16K/16K

Power with cache (mW/MHz) - 0.41 0.3 0.244 0.22

Power w/o cache (mW/MHz) - 0.31 0.22 0.185 0.16

** The above numbers are either quoted from fully floorplanned layouts/synthesis trials or scaled with respect to process and library performance

232323 Cortex-R4F Integrated FP details ƒ Automotive and control applications ƒ Dual-issue of FP operations with integer pipeline ƒ Optimised for single precision ƒ Delivering near integer level performance ƒ Full hardware support for ƒ Single and Double Precision (IEEE 754-compliant) ƒ Subnormals, and ‘run fast’ mode ƒ Divide and square root

242424 ARM on FPGA ƒ FPGA market trends ƒ Decreasing costs - 25% year on year* ƒ Increasing capacity – 90nm, 65nm… ƒ 40k CPU-based design starts in 2009**

ƒ ARM7TDMI® Core on FPGA via Actel ƒ 2005 Product of the Year from Electronic Products; EDN Hot 100

ƒ Benefits to ARM and its partners ƒ Dramatically increase ARM based design starts ƒ Migration path from FPGA to ARM based ASIC/ASSP/MCU ƒ Strengthen ARM ecosystem

* Source: Altera, 2004 ** Source: Gartner, 2005

252525 ARM Cortex-M1 ƒ The first ARM processor designed for FPGA • ARM compatibility and ecosystem across FPGA, ASIC/ASSP/MCU • Object code upwards compatible with Cortex-M3 in ASIC • 32-bit processor, 3-stage pipeline at 0.8 DMIP/MHz • Up to 185MHz depending on FPGA device

ƒ Actel lead partner and first licensee • Available at no license fee from Actel

ƒ ARM will also license RTL directly to end users • Vendor independent Synplicity or Mentor synthesis • Beta availability to lead partners now • Optimised release due Q307

262626 SC100

ƒ Fully synthesizable core for smartcard and secure products ƒ Randomized processor layout based on customer design specifications ƒ Advanced, secure debugging and test methodology ƒ One-way development process to ensure security during development ƒ Controlled access to design stages via flexible software and emulation solutions ƒ Memory Protection Unit performs memory management type functions securely ƒ Specific counter-measures help prevent analysis of current flows ƒ Energy and space-saving features, including ARM Thumb® compression ƒ Rapid ASIC or ASSP integration with reduced time-to-market

0.18um process 0.13um process

PPA Area Opt Area Opt

Frequency (MHz) 50-80 80

Area without cache (mm2) 0.50 0.25

Power w/o cache (mW/MHz) 0.21 0.12

272727 ARM Core Business Model

Business Development / Segment Marketing

ARM Partner licence

OEM royalty Customer

ARM Partner licenses Partner develops SoC Licence fee covers proportion of development costs Royalty shares by rewarding success.

282828 Embedded Software Business Model

292929 ARM Core Foundry Business Model royalty

ARM licences SUDL Partner Design licence

SUDL Designer develops SoC & has manufactured ARM licence Partner (Foundry inserts core) ARM licences Foundry Partner Manufacturing OEM licence licence Customer

Foundry

Licence fee covers proportion of development costs Royalty shares by rewarding success.

303030 Physical IP Foundry Business Model

Designer downloads library from ARM shrinkwrap licence

Designer develops SoC ARM Designer & has manufactured

OEM Customer

ARM licences licence Foundry Foundry Manufacturing licence royalty

Licence fee covers proportion of development costs Royalty shares by rewarding success.

313131 Licensing Options

• Higher license value • Higher IP value • Greater commercial / technical interaction • Increasing internal investment Arch. by partner • Increasing ARM / Partner Platform business knowledge Subscription licenses • Greater flexibility • Greater commercial / Implementation End User License technical interaction

Term

Single Use Design Foundry Program Free Library Program DesignStart

Academic / Research

Processors Physical IP

323232 Driving Momentum: 4.5bn Units by 2010

4.5Bn / year

Mobile

Non-Mobile

68% YoY growth in Non-Mobile

600 550 2bn / year 500 450 400 350 300 250 200 150 100 10X Growth 50 in Embedded 0 2006 2010 Q101 Q201 Q301 Q401 Q102 Q202 Q302 Q402 Q103 Q203 Q303 Q403 Q104 Q204 Q304 Q404 Q105 Q205 Q305 Q405 Q106

Confidential 333333 Vast Base of Applications

INDUSTRIAL CONSUMER AUTOMOTIVE

Industrial Power Medical Motor Motor White Control Control Goods

343434 Microcontroller Market ($M) Source: Semico

Potential TAM available to ARM based Families of MCU Products

8b

16b

32b

Confidential 35 Next-Generation Microcontrollers ƒ Base MCU platform becoming a commodity ƒ Differentiation through integration ƒ Speed-to-market is the key to obtaining a competitive edge ƒ Example: Metro™ enabling ultra low power UWB microcontrollers $M

363636 ARM Cortex™-M3 is Now Shipping ƒ ARM processors now range from $1 to 1 GHz ƒ ARM Cortex-M3 production release available December 2005 ƒ First MCU’s released on March 27th 2006 ƒ All supported by a single compiler suite

373737 How Does 32-bit Cost Compare ?

ƒ Costing Example ƒ Performance Requirement: 5 DMIPS ƒ Code Size: 256KB equivalent code ƒ Process: TSMC 0.18µ Generic

Cortex-M3 8051 Frequency Requirement 4MHz (5DMIPS / 1.25DMIPS/MHz) 63MHz (5DMIPS / 0.08DMIPS/MHz) Power Consumption 0.8mW (0.19mW/MHz x 4MHz) 32mW (0.5mW/MHz x 63MHz) Core Silicon Area 0.36mm2 0.10mm2 (approx.) Flash Memory Area 0.13mm2 (4x Code Density = 64KB) 0.52mm2 (256KB) Total Area (Core+Flash) 0.49mm2 0.62mm2 Basic Cost of Silicon* 19c per die 20c per die

ƒKey question: where’s the break even point between 8 and 32bit? ƒSmall and efficient CPU such as Cortex-M3 lowers break even point

*Costs calculated by IC Knowledge 2005

383838 Market Trends : Intelligence Driving Change

1913 Model T Ford No electronics

2015 - Pervasive Circa 1980 BMW 733i but hidden electronics Introduction of ABS 2005 BMW 7 Series iDrive Control system

393939 Market Trends: Growth of Embedded Software

Automotive electronics From a mechanical industry to an industry driven by electronics

50 45 Touareg

40 Phaeton D1 Golf A5 35 Up to 90Mb Memory 30 25 Passat B5GP 20 15 Passat B5 Golf A4 10 Golf A4, Polo A04 5 Golf A4

Number of ECU in the Network (CAN, Sub-CAN,LIN) 0 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

Elektrik-/Elektronik-Entwicklung Seite 3 Elektronikstrategie E E

404040 Compiler Compatibility Improves Reliability

Reliability Growth through Software Carry Over

RealView® MDK-ARM Microcontroller Development Kit ROCOF, Rate of Occurence of Failures

observed ARM7TDMI ARM9

Modifications and ports ADuC7000

AT91SAM7x AT91SAM9x

MAC7xxx

MLQ2xx ML69xx

LPC2xx LPC3xx theoretical LH7A404

STR7/ST30 STR9

67% of Software Maintenance Costs are t TMS470 Proportional to number of architectures MP7 (FPGA) supported: Source VDA

414141 ARM in MCUs Today

ƒ Significant success to date "In North America, we have seen a 30% increase in ARM based design ƒ ~70M units shipped in 2005 activity over the last 18 months" - David Doherty, Vice President - Arrow North ƒ More than 100 ARM technology- American Components based MCUs in market today MCU Families ƒ ARM7 family-based MCUs ARM7TDMI ARM9 are selling for below $2 ADuC7000 ƒ More than 30,000 members of ARM processor-based MCU AT91SAM7x AT91SAM9x user groups MAC7xxx ƒ ARM7 family forms the basis MLQ2xx ML69xx of a great microcontroller LPC2xx LPC3xx LH7A404 ™ ƒ ARM9 family used for STR7 STR9

performance or Embedded TMS470 Linux designs MP7 (FPGA)

424242 CortexTM Addressing Software Standards

ƒ Software Integration ƒ ARM Cortex Memory Protection scheme allows secure integration of independent software modules ƒ Based on Feedback from OSEK TIME vendors involved in the AUTOSAR OS specification to provide optimal task separation and RTOS visibility

ƒ Scalable platform for Software ƒ Automotive Examples: ƒ Intelligent Sensor/Lighting ƒ Wired/Wireless Gateway ƒ Convenience and Safety 32-byte Resolution Hardware Memory ƒ Thru to Centralized Body Control Protection Scheme to ‘Sandbox’ Tasks

Confidential 43 ARM Cortex-M1: Completes the SW Story Rationalize IT Costs and Improve Software Reuse

Tool chain MCU SYSTEM DESIGN Software

AMBA system Xilinx Altera Actel

ƒ Allows customers to use code base on either MCU, FPGA or SoC • Cortex-M1 can run at over 70MHz in FPGA • Designs can benefit from efficient, low-power MCU optimised Cortex-M3 • Cortex-M1 ISA is a compatible sub-set of the Cortex-M3 • Software compatibility allows code reuse

Confidential 44 Leverage the ARM Ecosystem

User Groups: Over 30,000 members on ARM Based MCUs Silicon available through online distributors

Major franchise distributors have teams of FAEs familiar with the ARM Architecture

Quality as well as Quantity: Many of these 3rd parties identify ARM related business as ‘largest growth driver’, which means robust, supported solutions

TOOLCHAINS PLATFORMS DEBUGGERS OPERATING SYSTEMS

Confidential 45 ARM Connected Community – 450+

Confidential 46 Growth Rates of Top 10 32-bit CPU’s

ƒ 32-bit Market growth significantly Top 10 32-bit Growth Rate outpaces that of both 8 and 16-bit (over 5Mu) 20004->05 MCU’s ARM 45% ƒ ARM architecture has the fastest H8S 31% rate of adoption and outpaces the 68k/Coldfire 29% market PowerPC 29% ƒ Many new MCU products and families were introduced during FR 28% 2006 which will extend the range MN103 27% and diversity of solutions V850 21% ƒ In turn, this drives the ecosystem ƒ Toolchains M32R 19% ƒ RTOS SuperH 2% ƒ Middleware TriCore -3%

ƒ Forums Based on SemiCo Research Figs. Dec 2006

Confidential 47 Enabling Better Embedded Software

ƒ Innovation through Standardization of Open Core ƒ Software Reuse through an Open standard ƒ Improved Software Reliability and Quality ƒ Broad portfolio of compatible devices ƒ From many semiconductor partners ƒ Take advantage of larger pool of qualified engineers ƒ Reduced risk from architecture ‘End-Of-Life’ ƒ Wide selection of well supported 3rd party tools

ƒ Don’t Paint Yourself in a Corner Tomorrow ƒ Consider Open, 32-bit Architectures today

Confidential 48 RealView Compilation Tools MDK v3.1x

Confidential 49 MicroLib – Optimized C Libraries

MicroLib significantly reduces library size in embedded applications

ƒ Superset of standard RealView C Library ƒ Developed for embedded and memory constrained applications ƒ Optimized for embedded applications ƒ Minimal overhead for un-used OS functionality ƒ Un-used functions removed from memory footprint ƒ Faster system bring –up ƒ Most functions initialized at point of use ƒ Up to 92% Reduction in Library Code size ƒ ‘empty main’ ƒ Even more for ‘Hello World’ using Print f

Confidential 50 MicroLib – Optimized C Libraries

Easily selected before compilation

ƒ Target options dialog ƒ Select MicroLib ƒ Compile/ build as normal

Confidential 51 MicroLib – Significant Savings

Library Totals RO Totals

25000 30000 61% 51% 20000 25000

20000 15000 15000 10000 10000

5000 5000

0 0 ARM Thumb Thumb2 ARM Thumb Thumb2

Processor Object Standard MicroLib % saving ARM7TDMI ARM Library Total 21,352 8,980 61% RO Total 25,608 12,816 51% ARM7TDMI Thumb Library Total 17,156 6,244 57% RO Total 20,129 9,348 50% Cortex-M3 Thumb-2 Library Total 15,018 5,796 63% RO Total 18,616 8,976 54%

Based on Dhrystone 2.1 Benchmark

Confidential 52 RealView Compilation Improvement

Code Size Reduction Performance Increase

100% 135% +34% 16% 130%

125% 95% 120%

115% 90% 110%

105% 85% 100%

95%

80% 90% 1999 2000 2001 2002 2003 2004 2005 2006 2007 1999 2000 2001 2002 2003 2004 2005 2006 2007 SDT 2.5 RVCT 3.1 SDT 2.5 RVCT 3.1

9MB ROM Size ADS v1.2 „ 46 Benchmarks, 48 Applications RealView 2.0 RealView 3.0

Confidential 53 Compilation Code Size ƒ Displays code size after compilation ƒ Easily seen in Output window ƒ Quick and easy test to see effect of MicroLib.

Confidential 54 Code Density (RVDS, arm gcc, MXXX SED)

codesize Toolchain Compile options Target text (%)

gcc-4.2.1 "-Os -I/usr/include" mips 141852 100.0

gcc-4.2.1 "-Os -mips16 -I/usr/include" mips16 97256 68.6 gcc-4.2.1- "-Os -I/usr/include" arm 123380 87.0 codesourcery gcc-4.2.1- "-Os -mcpu=cortex-r4 -mthumb - thumb-2 88816 62.6 codesourcery I/usr/include"

ARM RVDS 3.1 "--cpu cortex-r4" arm 101465 71.5

ARM RVDS 3.1 "--cpu cortex-r4 --thumb" thumb-2 72603 51.2 ARM RVDS 3.1 "--cpu cortex-m3 --thumb" thumb-2 72603 51.2

MIPS SDE-Lite "-Os -I/usr/include" mips 132932 93.7

MIPS SDE-Lite "-Os -mips16 -I/usr/include" mips16 87700 61.8

MIPS SDE-Lite "-Os" mips 129108 91.0

MIPS SDE-Lite "-Os -mips16" mips16 84308 59.4

Î “-I/usr/include” :debian Linux includes

Confidential 55 µVision MDK v3.1x

Confidential 56 File Structure

Project and examples file structure simplified

ƒ RV30 Folder removed ƒ All subfolders held in ‘ARM’ ƒ../Keil/ARM/Boards…. ƒ../Keil/ARM/Examples… ƒ More straight forward and less confusing ƒ Fewer user questions

Confidential 57 Installation Project

Choice of default project at installation

ƒ Efficient user installation ƒ Choose specific board project ƒIf they have an eval board ƒIf they have a vendor in mind ƒ Choose generic project

Confidential 58 Real-Time Agent

Enables target debugging on-the-fly that requires no system halts

ƒ Small C Module ƒ Adds little overhead to user application ~1,500Bytes R/O ƒ Communicates using standard JTAG channel via ULINK2 ƒ On-the-fly Debugging ƒ Read and Write memory and variable access during program execution ƒ Set breakpoints while program is running ƒ Serial I/O (printf) via debug channel

JTAG Application + Real-Time Agent

CPU Peripherals

Confidential 59 Real-Time Agent RTX Event Viewer

Visualization of Real-Time Kernel execution and performance.

ƒ Extends RTX Window ƒ Time line for active events ƒ Visually displays timing of events ƒ Optimization and verification ƒ Communicates via ULINK2 and Real-Time Agent

Confidential 60 Device Support MDK v3.1x

Confidential 61 Device Support

Support for the new STM32 devices

ƒ STMicroelectronics ƒ STM32 – Cortex-M3 based devices ƒ ‘Classic’ device support (Compile/debug) ƒ Device Simulation due Sept ƒ MCBSTM32 Eval Board – Now ƒ STM32 Starter Kit - ASAP ƒ Simulation support for STR750

Confidential 62 Device Support

Support is added for the TI HET

ƒ TI ƒ HET support for TMS470 ƒ NXP ƒ Full simulation for LPC2300 and LPC2400 devices ƒ Luminary ƒ New Stellaris LM3S2xx and LM3S6xx families added ƒ Simulation of all devices now supported

Confidential 63 ARM Cortex-M1 Processor

ƒ High frequency, low area microcontroller processor for FPGA • Between 70MHz – 170MHz (depending on FPGA device) • Occupies less than 15% area on the most popular FPGA device sizes • Cortex-M1 upwards compatible with Cortex family on ASIC/ASSP/MCU • Performance will continue to increase as FPGA technology progresses

ƒ Optimised for synthesis on multiple FPGA types • Xilinx (e.g. Spartan-3, Virtex-5) • Altera (e.g. Cyclone-II, Stratix-III) • Actel (M1 ProASIC3 and M1 Fusion)

Confidential 64 Cortex-M1 Support

MDK 3.1 offers Compiler and Debug support for Cortex-M1

ƒ RealView Microcontroller Development Kit v3.1 ƒ Support for Cortex-M1 core ƒ Compiler, Debugger and core simulation ƒ No peripheral simulation ƒ RTX support ƒ FPGA Bundle Kits ƒ May be offered when FPGA vendors promote Cortex-M1

Confidential 65 MDK on the Web

New 3.1 landing page with important features http://www.keil.com/arm/mdk310.asp

Confidential 66