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Title of Presentation NaturalNatural EvolutionEvolution inin TheThe EmbeddedEmbedded WorldWorld Tom Wang Manager, ARM Marketing Jan., 2008 Confidential 1 Our Vision ARM designs technology that lies at the heart of advanced digital products 222 ARM’s Activities Connected Community Development Tools Software IP Processors memorymemory System Level IP: Data Engines SoCSoC Fabric 3D Graphics Physical IP 333 The ARM Strategy The SoC must enable the device manufacturer to produce highly desirable products Software to bring the The CPU is at system alive and to the heart of a maximise the System on Chip performance of the system Software O E Ms EMs Processors O System on Chips Software tools, ESL Systems require high tools and models to Tools and Physical IP performance Fabric target software onto OEMs along with high the processors in the quality Physical IP system 444 ARM Cortex Family of Processors Bringing the benefits of architectural innovation across the spectrum ARM Cortex- Series: A Cortex-A8 Applications processors for complex OS and user applications ARM Cortex-R Series: Cortex-R4F Embedded processors for real-time systems Cortex-R4 ARM Cortex-M Series: Cortex-M3 Deeply embedded processors optimized for Cortex-M1 microcontroller and low-power applications 555 ARM Processor Portfolio Leading the industry in ARM Cortex performance and low power “Intelligent Computing” 2000 Cortex-A8 1500 1000 DMIPS x4 ARM1176JZF-S Cortex-R4F 750 Cortex-R4 ARM11 MPCore 500 ARM1026EJ-S ARM926EJ-S 250 ARM7TDMI ARM968E-S SC100 Cortex-M3 Cortex-M1 2007 666 ARM Processor Public Licensees Processor Total # Public licensees Family/Core Licenses Cortex Family 23 Cortex-A8 7 Freescale, Matsushita, Samsung, ST, TI Cortex-R4/R4F 8 Broadcom, TI Cortex-M3 7 Actel, Broadcom, Luminary, ST, TI ARM11 Family 53 LSI, NEC, Qualcomm, Sunplus, Toshiba ....... ARM11 MPCore 10 NEC, Nvidia, Renesas, Sarnoff CoreSight 22 Broadcom, Philips, Samsung ……. ARM9 Family 223 ADI, Fujitsu, Infineon, Sharp, Sony, TSMC ……. ARM7 Family 148 Atmel, Cnxnt, Intel, Mediatek, National, SiRF …. 777 Investing in R&D Major challenges can only be met by significant, ongoing investments Need integrated solutions ARM continues to invest over a vast spectrum From 1GHz+ processors to 8-bit MCU replacement Optimized 90, 65 and 45nm low power libraries Software, tools, Fabric, Audio & Graphics processors ARM’s model allows this to be shared across the Partnership 888 Market Driven Roadmaps Central Product Definition R&D Project Approval Roadmap Investment ~ $117m p.a. Roadmaps created by divisions from market input and innovation 999 Processors for All Applications H Cortex-A9 MPCore 2000+ DMIPS Multi-Proc Applications Cortex-A8 2000+ DMIPS Uni-proc Processor ARM11 MPCore 600+ DMIPS Multi-Proc Market ARM1176J(F)-S 600+ DMIPS Uni-Proc L ARM926EJ-S 250+DMIPS Uni-Proc ARM1156T2(F)-S 600+ DMIPS Uni-Proc H Real-Time ARM946E-S Cortex R4(F) 600+ DMIPS Uni-Proc Embedded ARM968E-S Market L 150+ DMIPS Uni-Proc ARM7TDMI 100+ DMIPS Uni-Proc Microcontroller H ARM7TDMI Cortex-M3 & FPGA Market L Cortex-M1 1010 10 Cumulative Processor Licenses ARMv7 Cortex-A9 4 ARMv6 Cortex-A8 ARM11TM 9* Family 58 ARMv5 Cortex-R4 10 233 ARM9TM ARMv4 Family Increasing Performance Cortex-M3 11* ARM7TM Family 151 Note: A further 26 licenses have been signed for ARM10TM and SecurCoreTM family processors, and Xscale/StrongARM. * One additional partner has access to Cortex-A8 and Cortex- M3 under a subscription license 111111 ARM Physical IP Products Library platforms Standard cells Pervasive SoC IP Embedded memory I/O functionality MemoryMemory High-speed interfaces ••ClassicClassic ••MetroMetro MemoryMemory DDR ••AdvantageAdvantage DDRDDR Serial PHYs SerialSerial PHYsPHYs StandardStandard CellsCells ••SageSage ••MetroMetro MemoryMemory ••AdvantageAdvantage I/OI/O CellsCells 1212 12 Cumulative Physical IP Licenses 1* 6 45 nm 3 5 65 nm 3 20 24 90 nm 4 31 9 18 26 130 nm 47 18 24 2 Increasing Complexity 180 nm 62 Metro Advantage Classic Velocity 27 SOI 250 nm * 45nm SOI License signed early in Q4 1313 13 Performance/Power Flexibility Performance ARM1176JZ-S Performance Platform ARM1176JZ-S Advantage-HS Mainstream Platform 90G Worst case 90G Worst Performance 620MHz 320MHz Boost 0.45mW/MHz 0.25mW/MHz 2.65sq mm 1.55sq mm Power/Area Reduction Density Optimized Platform All data estimated for full implementations Power 141414 RealView® Tools for Entire Design Flow IP Creation Core Generator Architectural Exploration SoC Designer Microcontroller Software Development µVision IDE and ULINK Pre-silicon Software Development Development Suite and SoC Designer Applications Development Hardware/Software Development Suite and Integration System Generator Software Optimization Development Suite and Profiler, ICE & Trace and System Generator ICE & Trace 1515 15 Applications Processor Roadmap ARM Cortex “Intelligent Computing” 2000 Cortex-A8 1500 1000 DMIPS x4 ARM1176JZF-S 750 ARM11 MPCore 500 ARM1026EJ-S ARM926EJ-S 250 ARM7TDMI ARM968E-S SC100 2007 1616 16 ARM1176JZ(F)-S 620 MHz ARM11 Applications processor Fast, 8-stage pipeline Dynamic Branch Prediction & Return stack Optional Vector Floating Point ARMv6Z Architecture SIMD Media extensions, Jazelle for Java Enhanced Real-time performance (Fast Interrupt Mode / VIC support) IEM Enabled Supports multiple voltage domains (Dormant Mode) and Voltage Scaling ARM TrustZone™ Architecture extensions for CPU and system security High Performance AXI Memory System Configurable I & D Caches and TCMs with dedicated 64-bit DMA 0.13um process 90nm process 90nm GT process PPA Speed Opt Area Opt Speed Opt Area Opt Speed Opt Standard Cells SAGE-HS Artisan Advantage-HS Metro Advantage Memories - HSHD Optimised Metro Advantage Frequency ( MHz ) 364 317 610 320 750 Area with cache (mm2) 6.46 5.51 2.54 1.42 2.1 Area without cache (mm2) 4.77 3.61 1.89 0.82 1.46 Cache size 16K/16K 16K/16K 16K/16K 16K/16K 16K/16K Power with cache (mW/MHz) 1.29 1.24 0.36 0.25 0.568 Power w/o cache (mW/MHz) 0.58 0.50 0.29 0.18 0.465 ** The above numbers are either quoted from fully floorplanned layouts/synthesis trials or scaled with respect to process and library performance 171717 ARM11MPCore Configurable multiprocessor with 1 to 4 processors 16K to 64K caches across each processor Dual or single 64-bit AMBA 3 AXI bus Configurable VFP unit for each processor ARMv6K Architecture Thumb, Jazelle, DSP extensions and SIMD Energy management Standby, dormant and power off states for each processor Intelligent Energy Manager (IEM) High performance memory system Cache coherence, L1 sharing, cork-screw cache memory design Reduced software complexity, standard OS view Asymmetric (AMP) and Symmetric (SMP) multiprocessing 90nm process PPA Speed Opt Area Opt Standard Cells Advantage-HS Metro Memories Optimised Metro Frequency (MHz) 608 320 Area with cache (mm2) 2.22 1.46 Area without cache (mm2) 1.56 0.90 Cache size 16K/16K 16K/16K Power with cache (mW/MHz) 0.32 0.23 Power w/o cache (mW/MHz) 0.27 0.18 ** The above numbers are either quoted from fully floorplanned layouts/synthesis trials or scaled with respect to process and library performance 181818 Cortex-A8 High Performance Applications processor Superscalar pipeline offers 2,000+ DMIPS Integrated L2 Cache with configurable size (0K-1MB), ECC High performance with excellent code density Thumb-2 hybrid 16-32-bit instruction set Architecture extensions for CPU and system security TrustZone™ Secure transactions & Digital Rights Management (DRM) Multimedia and Signal Processing Architecture NEON™ provides over 2x Performance of ARMv6 SIMD OpenMAX library and API’s for fast software development Efficient Run Time Compilation Target Jazelle-RCT: Target for Java. Memory footprint reduced up to 3x Can also target languages such as Microsoft .NET MSIL, Python 65nm LP process 65nm G+ process PPA Optimized Synthesized Optimized Synthesized Standard Cells Advantage-CE Advantage-HS Advantage-CE Advantage-HS Memories Custom Advantage** Custom Advantage** Frequency (MHz) 660-700 500-550 1.1 GHz+ 800+ Area with cache (mm2) 3.86 4.2 3.86 4.2 Area without cache (mm2) 2.79 3.1 2.79 3.1 Cache size 32K/32K 32K/32K 32K/32K 32K/32K Power with cache (mW/MHz) 0.58 0.75 0.43 0.55 Power w/o cache (mW/MHz) - - - - ** Optimized instances of Advantage RAMS Optimized data scaled from 90G Area includes L1 RAMS, L2 control. Excludes NEON, ETM, L2 RAMS 65 GP synthesized data scaled from 65LP 191919 Embedded Processor Roadmap ARM Cortex “Intelligent Computing” Cortex-R4 Cortex-R4F MIPS) ARM1156T2F-S ARM1026EJ-S ARM966E-S Performance (D ARM946E-S ARM968E-S ARM7TDMI ARM7EJ-S Cortex-M3 ARM996HS Cortex-M1 ARM7TDMI-S 2006 2007 Worst case conditions 2020 20 Cortex-M3 Cortex-M3 for cost-sensitive, low-power 32-Bit devices Complete processor for microcontroller and low cost applications Thumb-2 technology for greater performance and code density Hardware divide instructions for control applications Cortex-M3 includes configuration options for application fit Integrated NVIC for industry leading interrupt handling Extensive debug architecture with up to 8 hardware breakpoints Optional Memory Protection Unit (MPU) Flexible bus interfaces for easy system integration 0.13um process 90nm process CM3 Core Speed Opt Perf Opt Area Opt Speed Opt Perf Opt Area Opt Standard Cells SAGE-X SAGE-X Metro Advantage Advantage Advantage Frequency (MHz) 135 100 50 191 100 50 Area without cache (mm2) 0.43 0.24 0.21 0.21 0.14 0.13 Power w/o cache (mW/MHz) 0.14 0.079 0.07 0.07 0.044 0.04 Cortex-M3 Processor 0.13um
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