Design, Assembly, Integration, and Testing of a Power Processing Unit

Design, assembly, integration, and testing of a power processing unit for a cylindrical Hall thruster, the NORSAT-2 flatsat, and the Vector Gravimeter for Asteroids instrument computer

Adam Ladislav Svatos

A thesis submitted in conformity with the requirements for the degree of Master of Applied Science University of Toronto Institute for Aerospace Studies University of Toronto

Design, assembly, integration, and testing of a power processing unit for a cylindrical Hall thruster, the NORSAT-2 ﬂatsat, and the Vector Gravimeter for Asteroids instrument computer

Adam Ladislav Svatos Master of Applied Science Graduate Department of University of Toronto Institute for Aerospace Studies University of Toronto 2017

This thesis describes the author’s contributions to three separate projects.

The bus of the NORSAT-2 satellite was developed by the Space Flight Laboratory (SFL) for the

Norwegian Space Centre (NSC) and Space Norway. The author’s contributions to the mission were performing unit tests for the components of all the spacecraft subsystems as well as designing and assembling the ﬂatsat from ﬂight spares.

Gedex’s Vector Gravimeter for Asteroids (VEGA) is an accelerometer for spacecraft. The author’s contributions to this payload were modifying the instrument computer board schematic, designing the printed circuit board, developing and applying test software, and performing thermal acceptance testing of two instrument computer boards.

The SFL’s cylindrical Hall eﬀect thruster combines the cylindrical conﬁguration for a Hall thruster and uses permanent magnets to achieve miniaturization and low power consumption, respectively. The author’s contributions were to design, build, and test an engineering model power processing unit.

ii Acknowledgements

I would like to extend my thanks to Dr. Robert Zee, Director of the Space Flight Laboratory (SFL) at the University of Toronto, for bringing me into that organization and for allowing me to ﬂourish as an independent researcher. Students at the SFL carry exceptional responsibility in developing space hardware, and I am grateful for the opportunity to carry on in that tradition. Also, I would like to thank Bryan Johnston-Lemke, Payam Mehradnia, Rodrigo Cornejo, Jakob Lifshits, and Dr. Simon Grocott for advising me on the design of the Cylindrical Hall thruster power system. I would be remiss if I did not make special mention of the SFL class of 2017: Damon, Mehdi, Mike, Rob, and Simon. Our year-long project of designing the impossible spacecraft is over, but our bonds still remain. I am proud of what we accomplished and maybe someday we will see our design take shape and explore an asteroid. It was an honour to work with all of you and I look forward to crossing paths again. Throughout my time at the SFL, my family has supported me unwaveringly. I would like to thank my parents, my brother Nicholas, and my grandparents. I would also like to thank Alison, for her kindness, for her love, and for her willingness to listen to and to discuss my research challenges. This work was ﬁnancially supported by the Ontario Graduate Scholarship.

iii Contents

Acknowledgements iii

Contents iv

List of Tables vii

List of Figures viii

1 Introduction 1 1.1 NORSAT-2 ...... 1 1.2 Vector Gravimeter for Asteroids ...... 2 1.3 Electric propulsion for microsatellites ...... 2

2 NORSAT-2 FlatSat design, manufacturing, and unit testing 4 2.1 Introduction ...... 4 2.2 Structure ...... 4 2.3 Power ...... 5 2.4 Command and Data Handling ...... 7 2.5 Very High Frequency Data Exchange payload ...... 7 2.6 Cameras ...... 13 2.7 High speed radio receiver ...... 14 2.8 Command radio downlink ...... 14 2.9 Command uplink ...... 15 2.10 Attitude determination and control system ...... 16 2.11 Global positioning system ...... 16

3 Design and layout of the VEGA instrument on-board computer 18 3.1 Introduction ...... 18 3.1.1 Electronics architecture ...... 18 3.1.2 Data architecture ...... 19 3.2 Objective ...... 20 3.3 Requirements ...... 20 3.4 Methodology ...... 22 3.5 Results ...... 23

iv 4 Unit testing of the VEGA instrument on-board computer 24 4.1 Introduction ...... 24 4.2 Objective ...... 24 4.3 Requirements ...... 24 4.4 Software development ...... 25 4.4.1 I2C ...... 25 4.4.2 SPI ...... 26 4.4.3 GPIO ...... 26 4.5 Thermal acceptance ...... 27 4.6 Results ...... 28

5 Power processing unit for a cylindrical Hall thruster 29 5.1 Introduction ...... 29 5.1.1 Abbreviations ...... 29 5.1.2 Motivation ...... 29 5.1.3 Mechanism of operation of an annular Hall thruster ...... 30 5.1.4 Development of cylindrical Hall thrusters ...... 31 5.1.5 Comparison between cylindrical and annular Hall thrusters ...... 32 5.1.6 Plasmadynamics of a Hall thruster modelled using the predator-prey model . . . . 33 5.1.7 Insights from the model ...... 35 5.1.8 Realizing performance improvements in a Hall thruster ...... 36 5.2 Requirements ...... 37 5.2.1 Difference between an engineering model and a flight model ...... 37 5.2.2 Customer requirements ...... 38 5.2.3 Functional requirements ...... 38 5.3 Methodology ...... 39 5.3.1 Electrical ...... 39 5.3.2 Derating parts for space ...... 40 5.3.3 Thermal ...... 40 5.4 Electrical design ...... 42 5.4.1 Architecture ...... 42 5.4.2 Selecting an isolated switching-mode power supply topology ...... 43 5.4.3 Current- and voltage-fed push-pull converters ...... 45 5.4.4 Boost chopper ...... 50 5.4.5 Circuit simulation using numerical methods ...... 50 5.4.6 Supporting components ...... 54 5.4.7 Effect of layout on electromagnetic interference ...... 55 5.4.8 Printed circuit board layers ...... 56 5.4.9 Power stage component layout ...... 56 5.5 Controller design ...... 57 5.6 Thermal design ...... 57 5.6.1 Evaluating the junction temperature of critical components ...... 57 5.6.2 Evaluating the steady-state temperature of critical traces on the push-pull converter 58 5.6.3 Effect of layout on component thermal stress ...... 59

v 5.7 Results ...... 60 5.7.1 Power ...... 61 5.7.2 Control and data ...... 63 5.7.3 Thermal ...... 63 5.8 Testing ...... 63 5.8.1 Anode driving ...... 63 5.8.2 Load bank ...... 64 5.9 Future Work ...... 65

6 Hall thruster power processing unit control 66 6.1 Introduction ...... 66 6.1.1 Overview of basic control theory ...... 66 6.1.2 Overview of feedback loop stability ...... 68 6.2 Requirements ...... 70 6.3 Design Methodology ...... 71 6.3.1 Controlling the current-fed push-pull converter ...... 71 6.3.2 Boost chopper ...... 71 6.3.3 Low voltage rails ...... 72 6.4 Design ...... 72 6.4.1 Transfer function of output voltage variation with respect to duty cycle variation . 72 6.4.2 Pulse-width modulation gain ...... 73 6.4.3 Optocoupler transfer function ...... 74 6.4.4 Delay transfer function ...... 75 6.4.5 Compensator transfer function ...... 75 6.5 Results ...... 76 6.6 Future work ...... 77

7 Conclusion 78

vi List of Tables

2.1 NORSAT-2 flatsat power requirements ...... 6 2.2 NORSAT-2 flatsat power results ...... 7 2.3 NORSAT-2 flatsat command and data handling requirements ...... 7 2.4 NORSAT-2 flatsat VDES requirements ...... 8 2.5 NORSAT-2 flatsat miniature visual inspection camera payload requirements ...... 13 2.6 NORSAT-2 flatsat HS-RX payload requirements ...... 14 2.7 NORSAT-2 flatsat command radio downlink requirements ...... 14 2.8 NORSAT-2 flatsat command radio uplink requirements ...... 15 2.9 NORSAT-2 flatsat ADCS requirements ...... 16 2.10 NORSAT-2 flatsat GPS requirements ...... 17

3.1 VEGA IOBC requirements ...... 21

4.1 VEGA IOBC autotester requirements ...... 25

5.1 Requirements of the Cylindrical Hall thruster engineering model power processing unit . . 39 5.2 Electrical requirements of the ﬁve power supplies needed by the thruster ...... 39 5.3 A trade study of isolated DC-DC converter topologies ...... 44 5.4 Voltage rails requirements check ...... 55 5.5 Thermal design requirements check for critical components ...... 58 5.6 Thermal design requirements check for traces ...... 59 5.7 Requirements check for the Cylindrical Hall thruster engineering model power processing unit ...... 61 5.8 Calculated losses in each component of the PPU and the expected eﬃciency ...... 62 5.9 PPU load bank requirements ...... 64

vii List of Figures

1.1 SFL’s cylindrical hall thruster using Argon propellant ...... 3

2.1 Flatsat with components added ...... 5 2.2 Power measurement for carrier wave ...... 10 2.3 Difference between power measurement for carrier wave ...... 10 2.4 Power measurement for QPSK ...... 11 2.5 Difference between power measurements for QPSK ...... 11 2.6 Power measurement for BPSK ...... 12 2.7 Difference between power measurements for BPSK ...... 12

3.1 VEGA power architecture [6] ...... 19 3.2 VEGA data architecture [6] ...... 20 3.3 Complete VEGA IOBC ...... 23

4.1 I2C protocol ...... 26 4.2 SPI protocol ...... 26 4.3 Location of the temperature sensor that measures board temperature ...... 28 4.4 Location of the temperature sensor that measures processor temperature ...... 28

5.1 Cross-sectional diagram of a Hall thruster [10] ...... 30 5.2 Annular Hall thruster with electrical components labelled [12] ...... 31 5.3 Annular Hall thruster with electrical components labelled ...... 32 5.4 Cylindrical Hall thruster with electrical components labelled ...... 32 5.5 Typical driving voltage and resulting current [4] ...... 33 5.6 SFL CHT displaying a 10 kHz breating mode ...... 34 5.7 Canonical solution of predator-prey equations ...... 34 5.8 An oscillating voltage on the anode drives a oscillating current ...... 36 5.9 The canonical boost converter ...... 37 5.10 Understanding MOSFET switching losses [24] ...... 41 5.11 Power processing unit block diagram ...... 43 5.12 Circuit diagram of voltage-fed push-pull converter [26] ...... 45 5.13 Circuit diagram of current-fed push-pull converter [26] ...... 46 5.14 Gate drive pulse-width modulation of current-fed push-pull converter ...... 47 5.15 Circuit diagram of pulsating boost chopper[4] ...... 51 5.16 Anode voltage simulated using LT Spice. The target voltage is 300V...... 51

viii 5.17 100V rail voltage simulated using LT Spice. The target voltage is 100V ...... 51 5.18 Anode current simulated using LT Spice. The target current is 1A ...... 52 5.19 Anode voltage simulated using LT Spice. The target voltage is 300V with a 50V peak-to- peak oscillation ...... 52 5.20 Anode voltage simulated using LT Spice. The target voltage is 300V with a 70V peak-to- peak oscillation ...... 53 5.21 100V rail voltage simulated using LT Spice ...... 54 5.22 Nodes of interest for evaluating trace temperature ...... 59 5.23 Unpopulated Hall thruster power supply PCB ...... 60 5.24 Populated Hall thruster power supply PCB ...... 60 5.25 Chassis-mount resistors ﬁxed to an aluminum I-beam to be used as a load bank ...... 65

6.1 Eﬀects of gain and phase on duty cycle and output voltage over time. Arb. units. [33] . . 67 6.2 Sample Bode plot [33] ...... 68 6.3 Block diagram of a converter with feedback [33] ...... 69 6.4 Illustration of crossover frequency and gain and phase margin [33] ...... 70

6.5 Gvd transfer function for the current-fed push-pull converter in the Hall thruster power supply [33][29] ...... 73 6.6 Boost converter with a feedback ampliﬁer [35] ...... 74 6.7 Schematic illustration of an optocoupler showing the pull-up resistor and LED resistor [36] 75 6.8 Type-I compensator with a sketch of its transfer function [33] ...... 76 6.9 T(s) for the current-fed push-pull converter including computation time ...... 77

ix Chapter 1

Introduction

1.1 NORSAT-2

Background

The Automatic Identification System, commonly referred to as AIS, is used for the tracking of large ships. AIS data is commonly collected from ship transponders using a satellite-borne AIS receiver. Demand for maritime data service has been increasing, which led to the development of the Very High Frequency Data Exchange System (VDES). The VHF band is in the range of (156.025 to 162.025 MHz). The VDES supports the distribution of maritime data, including meteorological and hydrographic data and traffic information, by integrating AIS with Application Specification Messages (ASM) channels, which have a higher capacity and increased reliability . NORSAT-2 is the first satellite to incorporate a VDES payload, developed by Kongsberg Seatex. The satellite also carries an advanced AIS receiver, also developed by Kongsberg Seatex. NORSAT-2 was developed and built by the SFL for Space Norway and the Norwegian Space Centre [1].

Objectives and outcomes

It is a common practice in the spacecraft industry to integrate the sub-assemblies prior to building the satellite itself. NORSAT-2 spare parts were combined into a flatsat, which is a physical twin of the launched satellite. However, the flatsat is only useful for testing if it is built to match the final satellite as closely as possible. There are specific requirements for achieving this standard, which are validated using unit tests according to the requirements in each subsection. This includes tests on each of the spare components of the satellite, including power, command and data handling, communications, attitude-determination and control system, and thermal subsystems, as well as the spacecraft payloads. It is crucial to perform unit tests during the development of a spacecraft, as this ensures that problems at the unit level do not complicate system-level testing. In addition, the spares must be qualified so that they can replace a flight part if necessary.

1 Chapter 1. Introduction 2

1.2 Vector Gravimeter for Asteroids

Background

The Vector Gravimeter for Asteroids (VEGA) is an ultra-high-accuracy, three-axis, planetary gravimeter. Its high accuracy allows for the geophysical surveying of low-gravity environments such as asteroids, the Moon, or Mars. Local gravitational ﬁelds can be mapped to the surface of the planetary body, allowing for geophysical analysis of the studied region. VEGA is designed to have zero bias or bias-drift in its measurements. As a result, VEGA allows a spacecraft to use inertial navigation methods, where acceleration measurements are integrated to obtain velocity and distance measurements [2].

Objectives and outcomes

The IOBC takes data output from the payload and passes this to the spacecraft computer using standard communications protocols. It accepts commands from the spacecraft computer and controls the payload in response. The power board accepts commands from and passes telemetry to the IOBC. The power board controls the actuation of the motors that orient the VEGA instrument. In addition, it controls the heaters that regulate the temperature of the VEGA instrument. All of this IOBC functionality must be implemented on a printed circuit board with appropriate electrical interfaces so that it can interact with the power board, the spacecraft bus, and the VEGA instrument.

1.3 Electric propulsion for microsatellites

Background

The nascent age of New Space has ushered in expansive microsatellite constellations to provide low- Earth orbit imaging, ubiquitous wireless internet, and other services. Simultaneously, space agencies have created road maps that set their sights on cislunar space and the asteroid belt as a proving ground for new technologies, while new firms view this region with an eye for profit. For successful commercial and research exploitation of these regions, propulsion technologies must be up to the task, possessing low cost, low mass, high specific impulse, long operation lifetimes, and being easily integrated into existing spacecraft buses. Solar electric propulsion technology, including Hall thrusters and ion thrusters, have demonstrated all of these desirable qualities. Hall thrusters in particular, are a moderately mature technology, with the first successful laboratory tests occurring over half a century ago, but with the need for spacecraft propulsion growing, the circumstances for this technology to flourish appear imminent. The Canadian Space Agency (CSA), through its Space Technology Development Program (STDP), awarded the SFL a contract to develop an on-board propulsion system that would enable station keeping as well as de-orbiting for micro and small satellites. This intent of this research from the perspective of the STDP was to develop and demonstrate technologies that would meet the current and future needs of various Canadian Space Programs [3]. In the first phase of a two-phase project, the Space Flight Laboratory (SFL) developed a 200W, 26 mm diameter ionization chamber Hall thruster for the Canadian Space Agency that was highly re- configurable, with the goal of facilitating optimization of performance parameters such as thrust, specific impulse, and power consumption. For the second phase, the SFL has continued development of a 300W Chapter 1. Introduction 3

Cylindrical Hall Thruster (CHT) speciﬁcally to meet these requirements of low mass and power for microsatellite missions. This second thruster is shown in Figure 1.1 [3].

Figure 1.1: SFL’s cylindrical hall thruster using Argon propellant

All testing of the thruster was done with a laboratory power supply, but it is too large and heavy to be used for ﬂight. If the CHT is to be used on a spacecraft mission a power supply must be devised that is suitable for that application.

Objectives and outcomes

To meet government and industry demand, a prototype 300W power processing unit was developed by the author at the SFL. This power processing unit was designed to fulfill the operating requirements of the SFLs existing miniaturized cylindrical Hall thruster, and it is the first commercial power processing unit to take advantage of recent discoveries in the field of Hall thruster physics that enable greater power efficiency at a given thrust compared to standard driving techniques. Research published in 2015 demonstrated a novel and power-efficient pulse-synchronous driver system for Hall thrusters. By applying a pulsating anode voltage with a frequency close to the predator-prey oscillation frequency in the thruster, the researchers produced stable operation of a Hall thruster. This driving technique requires fewer and smaller parts while improving thrust performance at a given power input by approximately 30% [4]. Chapter 2

NORSAT-2 FlatSat design, manufacturing, and unit testing

2.1 Introduction

The NORSAT-2 satellite was developed and built by the SFL for the Norwegian Space Centre and for Space Norway. The satellite is based on the SFL’s Next-generation Earth Monitoring and Observation (NEMO) bus [1]. The following section describes the unit tests and their results performed by the author for the NORSAT-2 flatsat. This includes tests on each of the spare components of the satellite, including power, command and data handling, communications, attitude-determination and control system, thermal, imaging, and the spacecraft payloads. It is crucial to perform unit tests during the development of a spacecraft, as this ensures that problems at the unit level do not complicate system-level testing. In addition, the spares must be qualified so that they can replace a flight part if necessary. It is a common practice in the spacecraft industry to integrate the sub-assemblies prior to building the satellite itself. NORSAT-2 spare parts were combined into a flatsat, which is a physical twin of the launched satellite. The flatsat is electrically and electronically identical to the final satellite, but with all the parts laid out flat and mounted to a metal plate. This make it useful for testing the operation of the satellite after installing new software. However, the flatsat is only useful for testing if it is built to match the final satellite as closely as possible. There are specific requirements for achieving this standard, which are validated using unit tests according to the requirements in each subsection.

2.2 Structure

Requirements

This subsystem is an aluminum plate with cutouts and mounting holes for the various printed circuit boards and payloads. These must be arranged to allow for the subsystems to be electrically connected using the shortest path whenever possible. Coaxial cables that carry radio-frequency signals must be approximately the same length as on the real satellite to preserve impedance values that are close to that of the satellite. The threaded holes for mounting components to the plate must be slightly larger than

4 Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 5 they would be typically, since they must accommodate helicoils. These are steel coils that are inserted into the mounting holes and provide a harder and more durable interface. Aluminum is softer than steel, so without helicoils the steel screws would abrade the aluminum threads.

Methodology and set-up

Earlier ﬂatsat designs were used as a template for designing this ﬂatsat. Drawings were made in the computer program SolidEdge.

Results

The flatsat plate was manufactured externally and helicoils were installed by SFL technicians. The components of the flatsat were integrated on the flatsat plate, shown in Figure 2.1.

Figure 2.1: Flatsat with components added

2.3 Power

The power system comprises the Modular Power System (MPS), the umbilical box, the battery, and a solar array simulator.

Requirements

A complete list of requirements is shown in Table 2.1. Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 6

Table 2.1: NORSAT-2 ﬂatsat power requirements

No. Description Rationale P1 System startup at solar array worst-case hot Satellite must be able to start when solar cells are worst-case hot. P2 System startup at solar array worst-case cold Satellite must be able to start when solar cells are worst-case cold. P3 Peak power tracking at worst-case hot and Peak power tracking must function in worst- worst-case cold case hot and cold for the satellite to maintain the power margin as designed. P4 Maximum battery discharge test starting from Satellite must be able to supply sufficient cur- a fully charged battery with no solar array rent from the battery alone without loadshed- power ding. This test is valid for a fully charged battery only. P5 Umbilical box verification Umbillical box supplies useful functionality to satellite operators. P6 Satellite off dongle Used to deactivate the satellite by modifying the harness. P7 Test system reset firecode Firecodes are an important functionality as they allow the satellite to be reset from any state. P8 Inrush current testing Inrush currents can indicate physical problems with printed circuit boards, such as a shorts.

Methodology and set-up

To qualify this system, the ability of the satellite to start in simulated worst-case hot and cold, perform peak power tracking, respond to ﬁrecodes broadcast over radio, and to operate with no solar array power was tested. Further testing evaluated the power consumption of each component of the spacecraft, to see if there were any anomalies. Inrush current testing was performed for the radios and payloads. Finally, the functionality of the umbilical box was checked, since it is an important piece of supporting equipment that allows the state of the ﬂatsat to be checked remotely over the local area network.

Results

The results of testing are shown in Table 2.2. Current and voltage measurements for each component were within limits. Inrush currents were small and indicated normal operation of all components with no electrical shorts present. The umbilical box functions well and the satellite operators continue to use it to interact with the ﬂatsat. Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 7

Table 2.2: NORSAT-2 ﬂatsat power results

No. Description Results P1 System startup at solar array worst-case hot Pass P2 System startup at solar array worst-case cold Pass P3 Peak power tracking at worst-case hot and Pass worst-case cold P4 Maximum battery discharge test starting from Pass a fully charged battery with no solar array power P5 Umbilical box verification Pass P6 Satellite off dongle Pass P7 Test system reset firecode Pass P8 Inrush current testing Pass

2.4 Command and Data Handling

Requirements

To qualify this subsystem, the housekeeping attitude determination and control, and payload computers were tested for their response to ﬁrecodes. Lastly, the clock drift of the payload computer was measured. A complete list of requirements is shown in Table 2.3.

Table 2.3: NORSAT-2 ﬂatsat command and data handling requirements

No. Description Rationale CDH1 HKC On/Off and Reset Firecodes Verify on/off and reset firecodes CDH2 ADCC On/Off and Reset Firecodes Verify on/off and reset firecodes CDH3 POBC Clock Drift Measure the rate of OBC clock drift when no PPS signal is present

Methodology and set-up

The ﬁrecodes were sent over a radio link to the spacecraft radio receiver and the OBCs were observed to see if they turned oﬀ or on in response to the corresponding code. An oscilloscope was used to probe the POBC clock drift and to determine the accumulated delay.

Results

The OBC ﬁrecodes function as intended and the accumulated clock drift on the POBC was within limits.

2.5 Very High Frequency Data Exchange payload

This payload provides two-way communication at higher data rates than possible with the current AIS system [1]. In terms of data modulation, it allows quadrature phase-shift keying (QPSK), binary-phase Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 8 shift keying (BPSK), and amplitude-shift keying, the last of which is the default carrier wave.

Requirements

A complete list of requirements is shown in Table 2.4.

Table 2.4: NORSAT-2 ﬂatsat VDES requirements

No. Description Rationale VDES1 Playback test waveform, verify on spectrum Connect output of VDES payload to spec- analyzer trum analyzer. Execute one of the test waveforms in the VDES payload. Verify output. Measure power at each level and with each carrier externally and internally. This is done to verify the ability of the payload to output a signal at close to the commanded power level. Return power should be measured as a high proportion of transmitted power being returned would indicate a de- fect with the payload. The error waveform shall not exceed 10%. VDES2 Test output power (ﬂight payload only) The voltage and current deviation (e.g. ripple) of the output waveform shall not exceed 10 percent for the three carrier wave options (default CW, BPSK, QPSK). Also perform these spectrum analyzer measurements:

• Plot 500 kHz bandwidth centered at 161.8625 MHz

• Plot 500 kHz bandwidth centered at 157 MHz

• Plot 50 MHz bandwidth centered at 2030 MHz

• Plot 10 MHz bandwidth centered at 1575.4 MHz

• Plot 1 MHz- 10 GHz

These measurements allow one to spot if the payload is transmitting a signal at a frequency that it was not designed to produce a signal at. Continued on next page Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 9

Table 2.4 – continued from previous page No. Description Rationale VDES3 Amplitude Frequency Response (ﬂight pay- Use carrier wave at levels of 27, 30 and 33 load only) dBm. Sweep carrier from 160 to 164 MHz in 500 kHz steps and observe with spectrum analyzer VDES3 Transmit timing accuracy (ﬂight payload With the payload synchronized to the GPS only) PPS, look at the accuracy of the transmission relative to the PPS signal, measure with an oscilloscope

Methodology and set-up

The Very High Frequency Data Exchange (VDES) payload was tested in terms of its output power, ability to accept commands and output test waveforms, its amplitude frequency response, and its transmit timing accuracy. The output power of the ﬂight model VDES was measured using a FSH3 spectrum analyzer and a FSH-Z1 power measurement device. The internal measurement of the VDES output power and the return power were also measured. The ranged studied was 20 dBm to 31 dBm in steps of 1 dBm. These measurements are plotted below for each of the following three ﬁles played on the VDES which were provided by Kongsberg.

Results test waveform

This test is a simpliﬁed version of the following output power test, as it is only concerned with verifying that the payload correct outputs a pre-loaded test waveform. As such, it serves as an easy and rapid means of determining if the payload is functional, before more extensive testing is performed. The payload passed this test. This test (VDES1) is the same as the default CW option in VDES2, so the results shown in Figures 2.2 and 2.3 apply.

Results for output power test

For requirement VDES1, the VDES payload was commanded to run through several other test waveforms. In addition to the power measurement plots, for each of the files a plot was generated that shows the percent difference between the internally measured VDES output power and the externally measured VDES output power. This was done in order to see if the relationship between them was a constant offset, linear, or some other function. The waveforms were the following:

• Carrier wave : 161.8625 MHz

• QPSK 19.2 ksps: 161.8625 MHz

• BPSK 19.2 ksps: 161.8125 MHz

Figure 2.2 shows that internally measured power was consistently 2% to 3.3% higher than the externally measured power. The diﬀerence between these two power measurements decreases monotonically Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 10 with transmission power. For all power levels, the deviation was smaller than 10%, so the payload meets requirements.

Figure 2.2: Power measurement for carrier wave

Figure 2.3: Diﬀerence between power measurement for carrier wave

Figure 2.4 shows that externally measured power was consistently 3.1% to 5.7% higher than the internally measured power. For this test, the diﬀerence between the externally and internally measured power dropped linearly with increasing transmission power. For all power levels, the deviation was smaller than 10%, so the payload meets requirements. Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 11

Figure 2.4: Power measurement for QPSK

Figure 2.5: Diﬀerence between power measurements for QPSK Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 12

Figure 2.6 shows that externally measured power was 6.9% to 10.4% higher than the internally measured power. For this test, the diﬀerence between the externally and internally measured power dropped linearly with increasing transmission power. For all power levels, the deviation was smaller than 10%, so the payload meets requirements.

Figure 2.6: Power measurement for BPSK

Figure 2.7: Diﬀerence between power measurements for BPSK

These measurements show that the payload is functioning The VDES payload functions according to speciﬁcations for all requirements. The following spectrum analyzer measurements were performed:

• Plot 500 kHz bandwidth centered at 161.8625 MHz Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 13

• Plot 500 kHz bandwidth centered at 157 MHz

• Plot 50 MHz bandwidth centered at 2030 MHz

• Plot 10 MHz bandwidth centered at 1575.4 MHz

• Plot 1 MHz- 10 GHz centered at 5 GHz

The results were presented to senior staﬀ engineers and were found to be acceptable.

Amplitude frequency response

A parametric sweep over a range of frequencies and a range of power levels was conducted. Due to the large number of plot and the size of each plot they will be omitted. Inspection of each spectrum analyzer plot by the author and a senior engineer found no visible errors, so this test was considered a pass.

Transmit timing accuracy

The payload was synchronized to the GPS PPS signal and the accuracy of the transmission relative to the PPS signal was measured using an oscilloscope. The prescribed payload transmission delay was set to be 30.8 µs, 33.5 µs, and 25.6 µs. These times were arbitrary but set with the intent of investigating whether the delay time deviation changes with the delay itself. The result was that for all three cases the payload delay matched the PPS signal to the ﬁrst decimal place. Therefore, this test was considered a pass.

2.6 Cameras

This spacecraft carries a small camera payload called the Miniature Visual Inspection Camera (MVIC) that is used to take an image of its deployed antennas.

Requirements

A complete list of requirements is shown in Table 2.5.

Table 2.5: NORSAT-2 ﬂatsat miniature visual inspection camera payload requirements

No. Description Rationale R1 Capture an image Take a picture with all three imagers. Trans- fer data to POBC. Download and verify image R2 Take a video with all three imagers. Transfer data to POBC. Download and verify video

Methodology and set-up

The functionality of the units and the ability to transfer and image and video to payload computer and ability to download an image and video from the payload computer were veriﬁed. Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 14

Results

The MVIC was able to take an image and capture a video of acceptable quality.

2.7 High speed radio receiver

Requirements

A complete list of requirements is shown in Table 2.6.

Table 2.6: NORSAT-2 ﬂatsat HS-RX payload requirements

No. Description Rationale HS-RX1 Bulk upload large test file, verify Configure the RF rack with an attenuator so that the HS-RX signal strength is -92dBm Transmit a 100MB test file Download the file and verify it is complete. Download and verify image HS-RX2 Test command reception and relay Send commands to various subsystems over the HS-RX and confirm that they are received

Methodology and set-up

The functionality of this receiver was tested by uploading and transmitting a large test ﬁle that was checked against the original. The ability to receive and relay commands to various subsystems was conﬁrmed as well.

Results

A large (100 MB) test ﬁle was uploaded over this receiver successfully. Commands were sent over the receiver to multiple subsystems and these were received correctly. Therefore, both tests were considered a pass.

2.8 Command radio downlink

Requirements

A complete list of requirements is shown in Table 2.7.

Table 2.7: NORSAT-2 ﬂatsat command radio downlink requirements

No. Description Rationale CDH1 HKC On/Off and Reset Firecodes Verify on/off and reset firecodes CDH2 ADCC On/Off and Reset Firecodes Verify on/off and reset firecodes Continued on next page Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 15

Table 2.7 – continued from previous page No. Description Rationale CDH3 POBC Clock Drift Measure the rate of OBC clock drift when no PPS signal is present

Methodology and set-up

The command radio downlink is used to communicate between the satellite and a ground station. It is an S-band transmitter. A large test file was downloaded over the downlink from the House-keeping Computer (HKC), Attitude-Determination and Control Computer (ADCC), and Payload On-board Computer (POBC) to test the transmit function. In addition, the ability of the transmitter to turn off after fifteen minutes was evaluated. This ability is important because it prevent the satellite from being locked into a transmit-only mode.

Results

Downlink from the HKC, the ADCC, and the POBC was successfully performed at the requisite rate. The downlink transmitter correctly turned oﬀ after ﬁfteen minutes. Therefore, both tests were considered a pass.

2.9 Command uplink

The command radio uplink is used to communicate between the satellite and a ground station. It is an S-band receiver.

Requirements

A complete list of requirements is shown in Table 2.8.

Table 2.8: NORSAT-2 ﬂatsat command radio uplink requirements

No. Description Rationale CRU1 Command uplink to HKC Verify command uplink to HKC via 4kbps S-Band RX CRU2 Command uplink to ADCC Verify command uplink to ADCC via 4kbps S-Band RX

Methodology and set-up

To test the command radio uplink, an radio transmission test apparatus was conﬁgured to simulate a transmission from the ground to the spacecraft. The uplink was veriﬁed by examining the transmission of data to the HKC and the ADCC via the S-band receiver. Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 16

Results

The command uplink was executed successfully and at the correct bit rate. Therefore, both tests were considered a pass.

2.10 Attitude determination and control system

This subsystem is composed of sun sensors, reactions wheels, a magnetometer, and rate sensors.

Requirements

A complete list of requirements is shown in Table 2.9.

Table 2.9: NORSAT-2 ﬂatsat ADCS requirements

No. Description Rationale ADCS1 Verify communications with sun sensors Verify on/off and reset firecodes ADCS2 Verify communications with reaction wheels Verify on/off and reset firecodes ADCS3 Verify communications with magnetometer Measure the rate of OBC clock drift when no PPS signal is present ADCS4 Verify communications with rate sensor Measure the rate of OBC clock drift when no PPS signal is present ADCS5 Verify magnetorquer current, amplitude and Measure the rate of OBC clock drift when polarity no PPS signal is present

Methodology and set-up

The ability of the HKC to communicate with these components was verified. To test the sun sensors, their readouts when sunlit and shadowed were measured. To test the reaction wheels, they were activated. Finally, the magnetorquers were tested by measuring the magnetic field generated by the device and verifying that the direction and strength of the field are predicted by the current magnitude and direction.

Results

The sun sensors, reactions wheels, a magnetometer, and rate sensors were successfully communicated with from the ADCC. The sun sensors provided the correct signal when illuminated and shadowed. The reaction wheels were activated and they behaved acceptably. The magnetorquers outputted the correct magnetic ﬁeld in terms of intensity and direction as measured by an external magnetometer. Therefore, all tests were considered a pass.

2.11 Global positioning system

This subsystem is composed of a single electronics board that outputs a pulse-per-second (PPS) timekeep- ing signal to the spacecraft computers and payloads. This signal is received from the global positioning system (GPS). Chapter 2. NORSAT-2 FlatSat design, manufacturing, and unit testing 17

Requirements

A complete list of requirements is shown in Table 2.10.

Table 2.10: NORSAT-2 ﬂatsat GPS requirements

No. Description Rationale GPS1 Verify communications with GPS from HKC Necessary to provide the PPS signal to the HKC from the GPS GPS2 Verify communications with GPS from Necessary to provide the PPS signal to the ADCC ADCC from the GPS GPS3 Verify communications with GPS from Necessary to provide the PPS signal to the POBC POBC from the GPS GPS4 Verify PPS signal to HKC This signal provides an alternative to the OBC clock. GPS5 Verify PPS signal to ADCC This signal provides an alternative to the OBC clock. GPS6 Verify PPS signal to POBC This signal provides an alternative to the OBC clock. GPS7 Verify PPS signal to VDES Payload This signal provides an alternative to the OBC clock. GPS8 Verify PPS signal to AIS Payload This signal provides an alternative to the OBC clock.

Methodology and set-up

The ability of the GPS board to communicate with the spacecraft computers was tested by enabling GPS logs on those computers and verifying that logging occurred. Subsequently, the integrity of the PPS signal to the spacecraft computers was measured at the input to the spacecraft computers, VDES payload, and AIS payload. This signal provides an alternative to the OBC clock.

Results

PPS signals were measured at the input to each of the components described in the requirements and found to be of acceptable integrity. The spacecraft computer logs showed that the HKC, the ADCC, and the POBC received GPS PPS signals. Therefore, all tests were considered a pass. Chapter 3

Design and layout of the VEGA instrument on-board computer

3.1 Introduction

The Vector Gravimeter for Asteroids (VEGA) is an ultra-high-accuracy, three-axis, planetary gravimeter. SFL’s contribution to this instrument is the instrument on-board computer (IOBC) and the power board. In brief, the relationship between VEGA, the IOBC, and the power board is as follows. The IOBC accepts commands from the spacecraft computer and controls the payload in response. The power board accepts commands from and passes telemetry to the IOBC. The power board drives the actuation of the motors that orient the VEGA instrument in an open feedback loop, with magnetic encoders used to verify the motor’s ﬁnal position. In addition, it controls the heaters that regulate the temperature of the VEGA instrument in a closed feedback loop. A more detailed explanation of the relationships between all the elements of VEGA is described in the following two subsections in reference to power electronics architectures. The scope of this chapter will be the design and layout of the VEGA IOBC. The author contributed parts of the design and the entirety of the layout of the printed circuit board (PCB).

3.1.1 Electronics architecture

Central to the electronic architecture of VEGA, shown in Figure 3.1, are three pieces of hardware: the Data Acquisition Electronics (DAE), the instrument power board, and the instrument on-board computer. The function of the DAE is ﬁlter and digitize accelerometer and temperature sensor readings. The instrument power board takes power from the spacecraft bus, provides power conditioning, distributes power to the IOBC and to the instrument heaters and motors. The IOBC is used to command accelerometer measurements, motor positions, and heater duty cycles. It also processes and stores science data and engineering telemetry and in doing so provides an interface between the spacecraft or rover bus and the instrument [5]. The VEGA instrument is designed to accept a wide range of unregulated input voltages: 8 to 32V. This range includes the typical bus voltages of small spacecraft and rovers up to small-class platforms. The power board provides a regulated 5V output to power the instrument hardware, while the IOBC

18 Chapter 3. Design and layout of the VEGA instrument on-board computer 19 is supplied with unswitched 5V power to ensure that the instrument can be commanded whenever it is powered on by the host platform. All other loads are fed with switched supplies, allowing their state to be toggled between on and off. The benefit of this arrangement of switched and unswitched power lines it that the instrument can be operated in a low power mode when it is not making measurements. Furthermore, it enables the isolation of faulty or failed pieces of hardware without disrupting the entire payload. The accelerometers will be powered by a dedicated supply on the DAE electronics at 13.5V, but the DAE electronics are built by Gedex themselves and were not a part of the SFL’s contribution. Current flow to the X and Y-axis motors is driven by motor controllers on the power board. Current flow to the resistive heaters at the required duty cycle is also provided by the power board [5].

Figure 3.1: VEGA power architecture [6]

3.1.2 Data architecture

The VEGA data architecture is shown in Figure 3.2. It accepts both Controller Area Network (CAN) and asynchronous RS485 serial communications between the instrument and the host platform. Analog signal measurements from the accelerometers and from several Resistance Temperature Detectors (RTDs) are passed to the data acquisition electronics to be digitized. The digitized telemetry is passed to the IOBC over a Serial Peripheral Interface (SPI) bus. The DAE have options that are controlled by toggling I/O lines on the IOBC high or low. The optical encoders are read directly by the IOBC using a Bidirectional Serial Synchronous C-mode, which is a standard interface for reading position sensor systems. The IOBC uses Inter-integrated Circuit (I2C) bus to interrogate the power board for telemetry and to provide commands. The power board reads directly form the magnetic encoders using general purpose input outputs (GPIOs) and it will also read coarse RTD signals to monitor system health [5]. Chapter 3. Design and layout of the VEGA instrument on-board computer 20

Figure 3.2: VEGA data architecture [6]

3.2 Objective

The VEGA IOBC must be able to support the operations of the VEGA instrument and power board outlined above, while serving as an interface between VEGA and the spacecraft. Modiﬁcations to the IOBC schematic must be made to account for the new requirements of the VEGA IOBC relative to the standard SFL IOBC. The new PCB must be laid out, taking into account the smaller area allowed for the board and the new geometric constraints.

3.3 Requirements

The requirements for the VEGA IOBC are described in Table 3.1. Many of these requirements are naturally satisfied by having the IOBC be a modified SFL OBC. However, the requirements related to communications interfaces are quite different due to the demands of communicating with the optical encoders and required extra effort to satisfy. Physically, the VEGA IOBC and power board combined must fit into a volume of 10 x 10 x 3 cm. A 10 x 10 cm area is less than half of the area of the SFL IOBC, which presents a design challenge. Chapter 3. Design and layout of the VEGA instrument on-board computer 21

Table 3.1: VEGA IOBC requirements

No. Requirement Rationale VEGA-G1 The power board and IOBC should have This is a CubeSat form-factor that is de- combined dimensions of less than 10 x 10 sirable. x 3 cm. VEGA-C1 CPU and memory margins shall be no less Changing to a larger processor or adding than 50% in the detailed design phase. more memory would require a total design of the IOBC and must be avoided. VEGA-C2 The instrument shall have the ability to Required for commissioning. store and execute a sequence of pre-upload time-tagged commands. VEGA-C3 A measurement campaign may produce Expected value from Gedex estimations. up to 5 MB of data. VEGA-C4 The spacecraft shall have sufficient non- Allows the instrument to collect an ad- volatile data storage to maintain a teleme- equate amount of data without commu- try and health data backlog of at least 7 nicating with the main carrier craft con- days. stantly. VEGA-C5 Critical software shall be protected by Required to mitigate single-event upsets hardware Error Detection and Correction due to radiation. (EDAC), and volatile data should be protected by software or hardware EDAC. VEGA-C6 The instrument OBC shall, by default Only applies to instrument hardware that and at a minimum, log instrument health is powered on. Health telemetry will in- telemetry, with a period of no longer than clude at least instrument non-precision 60 seconds, and subsequently allow it to temperatures, switch currents, and switch be downloaded when in view of an Earth voltages. station. VEGA-C7 The Instrument OBC shall allow the It is assumed that this is not performed telemetry logging to be turned on or off, during nominal operations. This is in- and to allow the collection period to be tended for commissioning and debugging reduced to at least 5 seconds. This ad- purposes only. justment capability shall be independent for each subsystem group. VEGA-C8 The instrument OBC shall, at a minimum, This requirement is a global worst-case support an internal timestamp accuracy of timing specification. This applies unless better than 1s for all reported or recorded another requirement further constrains times. performance under certain conditions. VEGA-C9 The instrument OBC should provide an The basic tool needed to synchronize optional CMOS logic input for a PPS clocks precisely. (pulse per second) signal to provide precision time synchronization if desired. Continued on next page Chapter 3. Design and layout of the VEGA instrument on-board computer 22

Table 3.1 – continued from previous page No. Requirement Rationale VEGA-C10 The instrument OBC shall support CAN The RS485 interface will be able to sup- (5V), asynchronous RS485, 5V-tolerant port standard baud rates of 38400 and be- SPI, and 3V I2C data interfaces. low. VEGA-C11 The instrument OBC SPI interface to the Driven by science and temperature data DAE board shall be capable of handling a output from the data acquisition electron- minimum combined data rate of 30 kbps. ics: nominally 10 values, each 24 bits, sampled at 100Hz, plus margin for overhead. VEGA-C12 The instrument OBC shall be capable of Simpliﬁes communication with the power routing commands from CAN or RS485 to board. I2C data interfaces, and replies back. VEGA-C13 The instrument OBC shall allow new ap- Allows software updates on-orbit. plication code to be uploaded and executed at any time. VEGA-C14 The instrument OBC shall provide an op- With no radio interface and hence no ﬁre- tional CMOS logic input to reset the OBC codes, it is highly desirable to provide an without power-cycling it. alternate way to reset the OBC without obliterating memory contents, and to control the bootloader’s memory choice. VEGA-C15 The instrument OBC shall provide any Needed to toggle options on the DAE additional digital I/O lines needed to con- board. trol operation of the DAE board. VEGA-C16 The OBC shall be capable of interrogating The instrument has two such encoders. two high-precision absolute encoders. VEGA-C17 The instrument OBC shall provide the Pullups are needed since the CPU’s I2C pullups needed for the I2C data buses it interfaces are not power down-tolerant. drives.

3.4 Methodology

The design started with the standard SFL IOBC schematic as a foundation. All of the requirements were implemented in the schematic capture process. Small modifications were made to the connector interface and pull-up resistor configuration. A particularly large modification was that the VEGA IOBC has no need for an FPGA, octal UART, or a firecode detector, so these integrated circuit were removed from the schematic.

With the VEGA schematic fully developed, the board was laid out using Altium Designer, manufactured externally, and then assembled in-house by the SFL’s technicians. Chapter 3. Design and layout of the VEGA instrument on-board computer 23

3.5 Results

The complete VEGA IOBC is shown in Figure 3.3. Since it is a modified SFL IOBC and the SFL IOBC is known to be compliant with the requirements described in this chapter, all that is necessary to qualify this design to show that is passes the same long-form functional test (LFFT) as the SFL IOBC, which tests internal Random Access Memory (RAM), GPIOs, external RAM, external flash memory, internal universal asynchronous receiver/transmitter (IUART), serial peripheral interface (SPI), and inter-integrated circuit (I2C). The VEGA IOBC passed all of these tests. The next chapter will explain the author’s contributions to the LFFT, which were the I2C, GPIO, and SPI LFFT modules. They had to be re-written because the testing procedure for these items were configured differently for the VEGA IOBC compared to the SFL IOBC.

Figure 3.3: Complete VEGA IOBC Chapter 4

Unit testing of the VEGA instrument on-board computer

4.1 Introduction

The scope of this chapter will be the unit testing of the VEGA IOBC. Unit testing included standard thermal acceptance testing as well as developing software for automating the testing of the IOBC’s input and output functionality, subsequently referred to as the IOBC autotester.

4.2 Objective

The VEGA IOBC must be able to communicate with the VEGA power board, the instrument itself, and the spacecraft main computer. This relationship is shown in Figure 3.2. The communications protocols include general purpose input-outputs, 5V controller area network (CAN), 3V inter-integrated circuit (I2C), 5V serial peripheral interface (SPI), and asynchronous RS485. This chapter is concerned with testing the I2C, SPI, and GPIO channels. The method for testing these communications channels must be repeatable and easily transferred to Gedex, so that they may validate the IOBC’s functionality independently if they choose to. Consequently, it was decided that developing and using an autotester would fulﬁll these objectives.

4.3 Requirements

The requirements for the VEGA IOBC are described in Table 4.1.

24 Chapter 4. Unit testing of the VEGA instrument on-board computer 25

Table 4.1: VEGA IOBC autotester requirements

No. Description Rationale VEGAT1 Test I2C communications and obtain zero The VEGA IOBC has only one I2C chan- errors nel compared to the SFL IOBC’s two channels, so the VEGA IOBC cannot perform the autotest by communicating with itself. Therefore, code must be written to allow the VEGA IOBC to communicate with an external computer VEGAT2 Test SPI communications and obtain zero The VEGA IOBC has only one SPI chan- errors nel compared to the SFL IOBC’s two channels, so the VEGA IOBC cannot perform the autotest by communicating with itself. Therefore, code must be written to allow the VEGA IOBC to communicate with an external computer VEGAT3 Test GPIOs and obtain zero errors The VEGA IOBC has many more GPIO channels in use than the SFL IOBC does, so the new code must be written VEGAT4 The IOBC shall pass a standard SFL ther- The long-form functional test is run while mal acceptance test for a printed circuit the PCB is at worst-case hot and worst- board case cold temperatures to verify that it will meet operational requirements

4.4 Software development

Several options were considered for implementing the autotester functionality of verifying the integrity of the IOBCs multiple communications channels. One option was to have two IOBC boards testing their communications with one another. However, the ﬂaw with this conﬁguration was that it requires a even number of IOBCs, which is an unnecessary constraint for future IOBC operators. A better architecture was to program a microcontroller development board to participate in these communications integrity tests and then to provide this unit and its harness to Gedex. The methodology of these communications integrity tests will be described in the subsequent subsections.

4.4.1 I2C

The I2C protocol is shown in Figure 4.1. This protocol has a clock line (SCL) and a data line (SDA). The VEGA IOBC initiates the start condition by holding SDA low before SCL goes low. Then the board that is designated the Master, the VEGA IOBC, begins sending a clock signal and clocking out data. The program drops into a loop described below.

1. The IOBC sends a character to the development board Chapter 4. Unit testing of the VEGA instrument on-board computer 26

2. The development board stores the character in memory and then re-transmits it when the IOBC requests to see that position in memory

3. The IOBC compares the received character to the sent character and then increments the error count if the two characters do not match

4. Repeat steps one to three 255 times.

If the error count is larger than zero, then the test was failed. The design of the test is such that it is only possible to pass if the sent and received characters match exactly, so the channel must work successfully for a reasonable number of characters. The loop number of 255 was chosen arbitrarily. It could be increase but this would only lengthen the test and would not provide any extra information since a dysfunctional I2C channel would display errors immediately.

Figure 4.1: I2C protocol

4.4.2 SPI

The algorithm for evaluating the integrity of this communications channel is exactly the same as described in the previous subsection for I2C, except that there is a separate channel for the master to select a slave (SS), master out slave in (MOSI), and master in slave out (MISO). This is shown in Figure 4.2. The clock (SCK) is provided by the master as with I2C. Since there is only one slave on the channel, the slave select line is held low and the master outputs a clock as it sends out data.

Figure 4.2: SPI protocol

4.4.3 GPIO

The integrity of the GPIO communications protocol is evaluated using the following exercise. Chapter 4. Unit testing of the VEGA instrument on-board computer 27

1. Each GPIO line from the IOBC processor looped back to another GPIO line to make a collection of paired lines.

2. Half of the GPIO pairs are assigned to be input and half are assigned to be outputs.

3. Each output GPIO is set high.

4. Each input GPIO reads the input and increments its error counter if necessary.

5. Each output GPIO is set low.

6. Each input GPIO reads the input and increments its error counter if necessary.

7. Each GPIO input becomes an output and vice-versa. Repeat the previous steps to test each GPIO in its new role

If the error count is larger than zero, then the test was failed.

4.5 Thermal acceptance

The SFL’s thermal acceptance test for printed circuit boards has ﬁve phases. The temperature limits of the PCB are set by the most limited component on the PCB. During testing, the temperature of the VEGA IOBC processor and the board itself are logged using two temperature sensors, shown in Figures 4.3 and 4.4.

1. Initial LFFT at 25◦C

2. LFFT at the hottest allowed operating temperature of the board after a thermal soak at the hot survival temperature

3. LFFT at the coldest allowed operating temperature of the board after a thermal soak at the cold survival temperature

4. Continuous LFFT as the board cycles between the hottest allowed operating temperature and the coldest allowed operating temperature. Chapter 4. Unit testing of the VEGA instrument on-board computer 28

Figure 4.3: Location of the temperature sensor that measures board temperature

Figure 4.4: Location of the temperature sensor that measures processor temperature

4.6 Results

During the development of these tests, an oscilloscope was used to verify the integrity of the signals output from the development board and from the VEGA IOBC and they were found to be acceptable. The criteria for acceptability was a clean waveform with a straight rising and falling edge with no ringing. The measured waveforms matched the theoretical appearance of the protocol waveforms shown in Figure 4.1 and Figure 4.2. The test for evaluating the GPIOs is simply checking the DC voltage since there is no data stream that is synchronized with the clock (i.e. they are simply held low or held high). For all three cases the results were acceptable. The allowed number of failures for any test is zero as described in the requirements. Each VEGA IOBC was tested using these new modules in the autotesting software and they passed all tests with no errors. To ensure that the autotester code was operating correctly, it was tested on VEGA IOBCs that were intentionally modiﬁed to provide the incorrect output. This was done for all three tests and the VEGA IOBC autotester ﬂagged all the errors correctly. This shows that the code is testing the functionality that it targets. Both VEGA IOBCs presented to Gedex passed thermal acceptance testing. Chapter 5

Power processing unit for a cylindrical Hall thruster

5.1 Introduction

This chapter documents the design of a power processing unit (PPU) for a Hall thruster. Physically, this design takes the form of a printed circuit board with a microcontroller, communications circuitry, and power conversion circuity. The reasoning used to arrive at the ﬁnal conﬁguration will be described herein.

5.1.1 Abbreviations

A list of common abbreviations used in this chapter is presented below:

• PWM Pulse Width Modulation • TBC To Be Conﬁrmed

• CAN Controller Area Network • IC Integrated Circuit

• SFL Space Flight Laboratory • MPS Modular Power System

• SMPS Switching Mode Power Supply • PCB Printed Circuit Board

• COTS Commercial Oﬀ The Shelf • PPU Power Processing Unit

5.1.2 Motivation

According to the SpaceWorks Nano/Microsatellite Market Assessment Report, the number of satellites is expected to grow robustly [7], with the need for small satellite technologies growing commensurately. An unaddressed need in that space is that for propulsion systems capable of performing on-orbit maneuvers, station keeping, and deorbit impulses all with minimal propellant consumption. Hall thrusters are considered to have many features that make them suitable for these applications including the best thrust to power ratio among electric propulsion technologies, high thrust density and a simple mechanical design in comparison to other electric propulsion technologies [8][9]. Modern Hall thrusters operate in the 0.2–100 kW power range, with thrust eﬃciencies (kinetic energy of exhaust

29 Chapter 5. Power processing unit for a cylindrical Hall thruster 30 divided by input power) in the range of 30–70%. In terms of speciﬁc impulse, they are in the same range as ion thrusters: 1000–4000 s range.

5.1.3 Mechanism of operation of an annular Hall thruster

A cross-section of a Hall thruster is shown in Figure 5.1. This device provides thrust by ejecting gas at high velocity. This gas, usually a noble gas such as xenon, argon, or krypton, is ionized and then accelerated in an electric field. Hall thrusters have an anode, which is positively charged, and a virtual cathode, which is negatively charged and located at the space-facing opening of the thruster. Electrons ejected from the exterior hollow cathode near the thruster are captured in the virtual cathode region by the Lorentz force, and spiral along the radial magnetic field lines. The radius of the spiral is called the Larmor radius and it is far smaller for electrons than for ions, due to higher mass of the ions, so the ions are not confined to the thruster while the electrons are confined, forming a volume with negative charge. This electron cloud is used to ionize the neutral noble gas propellant that is injected into the ionization chamber. Ionized noble gas will in large proportion be neutralized as it passes through the virtual cathode. This phenomenon stops the spacecraft from charging up [10].

Figure 5.1: Cross-sectional diagram of a Hall thruster [10]

A specific sequence of events must occur for the thruster to be turned on. These steps will be described in reference to Figure 5.2. The majority of these steps are concerned with the conditioning of the hollow cathode. This entails the operation of two components in the cathode: a heater and an ignition electrode, called a keeper, which covers the cathode. Propellant is flowed through the cathode, which is heated by an electric current from the heater supply. This heat provides sufficient thermal energy to the electrons in the cathode such that they can be extracted using an electric field in a process called thermionic emission. This field is generated by an approximately 60V difference between the Chapter 5. Power processing unit for a cylindrical Hall thruster 31 keeper and the cathode emitter. The hollow cathode then emits a beam of electrons that are used to populate the virtual cathode [11].

Figure 5.2: Annular Hall thruster with electrical components labelled [12]

5.1.4 Development of cylindrical Hall thrusters

Cylindrical Hall thrusters were devised as a means of overcoming the poor performance of Hall thrusters when they are scaled down for use on power-limited and small satellites. Khayms and Martinez-Sanchez produced a detailed analysis of scaling laws for annular Hall thrusters and found that the characteristic dimension of the discharge scale L (i.e. the approximate depth of the annular channel) should scale as the discharge power IDVD, and the axial magnetic field applied to the plasma should scale as 1/L. This results in the discharge power area density scaling with 1/L as well, meaning that reducing L causes an increase in the discharge power area density, causing large thermal stress in the thruster walls and a linear drop in the power efficiency of the device [13][14]. Concepts other than a cylindrical topology have been proposed that would allow scale-down of Hall thrusters. Schmidt et al. developed a promising linear channel Hall thruster, which has the limitation of inherently less efficient discharge than an annular topology because of the electron Hall current striking the sidewall instead of flowing in a closed annular drift [15]. Smirnov et al. used another approach, which was to recess the central part of the annular channel. Their successful test showed that this approach produced an efficiency of 15–32% at 50–300W [16][17][18]. The cylindrical Hall thruster was developed at the Princeton Plasma Physics Laboratory [19]. It overcomes the problems of high heating and low efficiency at small dimensions by reducing the ratio of channel surface area to volume, which limits electron transport and ion losses [17][18]. Chapter 5. Power processing unit for a cylindrical Hall thruster 32

5.1.5 Comparison between cylindrical and annular Hall thrusters

A side-by-side comparison of an annular and cylindrical Hall thruster is shown in Figures 5.3 and 5.4, respectively. The annular geometry has an axial electric field and radial magnetic field. The cylindrical geometry has an axial electric field but its magnetic field that has a radial and an axial component, forming a cusp-type magnetic field. The cylindrical topology has a lower surface-to-volume ratio than the annular topology, which should result in lower wall losses in the channel and less heating [18].

Figure 5.3: Annular Hall thruster with electrical components labelled

Figure 5.4: Cylindrical Hall thruster with electrical components labelled Chapter 5. Power processing unit for a cylindrical Hall thruster 33

5.1.6 Plasmadynamics of a Hall thruster modelled using the predator-prey model

New findings in the physics of Hall thrusters have revealed a more power efficient method of driving the emission of ionized gas from a Hall thruster that improves efficiency, measured in Watts per unit of thrust, by up to a third [4]. To understand this performance improvement and how it can be achieved, one needs to understand the movement of charged gases, or plasmadynamics, inside a Hall thruster. In a Hall thruster there are three species of interest: electrons, neutral atoms of gas, and charged atoms of gas. Electrons are injected into the system from the hollow cathode, which functions like an electron gun. Neutral atoms of gas are injected into the system at a steady rate from the anode gas feed. After setting up the hollow cathode in a constant voltage mode, the operator would set the anode voltage to be a constant voltage of 300 VDC. The constant voltage drives a current that oscillates at approximately 20 kHz [4]. The resulting voltage and discharge current is shown in Figure 5.5

Figure 5.5: Typical driving voltage and resulting current [4]

One can examine the thruster from the outside and note that electrons are not being emitted from the device. They are trapped by the magnetic ﬁeld inside the thruster chamber and ﬁnd their way through the insulating walls back to the negative terminal of our battery at a low rate. Since the only other charged species are the charged gases inside the chamber, we can surmise that their movement is causing periodic rises and falls in current. In the literature this is commonly referred to as the breathing mode of the thruster.

Breathing mode

To verify that the SFL’s CHT behaved in a similar manner to other thrusters in the literature and therefore that it can be analyzed using the same models, the anode current and voltage were measured. The results are shown in Figure 5.6 and support that this is the case. The CHT displays the same characteristic breathing mode as other Hall thrusters from the literature, albeit at a lower frequency of approximately 10 kHz. Chapter 5. Power processing unit for a cylindrical Hall thruster 34

Figure 5.6: SFL CHT displaying a 10 kHz breating mode

This breathing mode is driven by predator-prey oscillations between electrons and neutral gas atoms, ﬁrst modelled in 1910 by Lotka and applied to autocatalytic chemical reactions [20]. Volterra independently discovered and modelled biological systems using the same equations in 1926 [21]. These two equations allow one to determine the population of prey (x) and predators (y) as a function of time (t). The solution to these equations is two sine waves, with one lagging the other. This is shown in Figure 5.7.

Figure 5.7: Canonical solution of predator-prey equations

Change in prey population over time is shown in (5.1). The first term is the rate of prey population increase, dependent on a coefficient (α) and the quantity of prey. With no predators, this would be exponential growth. The second term is the rate of predator population decrease and is equal to a Chapter 5. Power processing unit for a cylindrical Hall thruster 35 coefficient (β) multiplied by the number of predators and prey.

dx = αx − βxy (5.1) dt Change in predator population over time is shown in (5.2). The first term is the rate of predator population increase, dependent on a coefficient (δ) and on the number of predators and prey. The second term is the rate of predator population decrease and is equal to a coefficient (γ) multiplied by the number of predators. If there is no prey, this term causes an exponential decline in predator population.

dy = δxy − γy (5.2) dt The conditions for applying this model are as follows [22]. The validity of this model as a tool for understanding the electrons as predators and neutral gas atoms as prey must be evaluated.

1. The prey population (x) finds ample food at all times. Yes, but with a caveat. In a Hall thruster the amount of neutral gas particles is constant and does not fluctuate, so it will increase rapidly but we do not increase the gas flow in proportion with the quantity of gas in the thruster chamber. Over a short time frame we can approximate this as exponential.

2. The food supply of the predator population (y) depends entirely on the size of the prey population. Yes. The electrons are ionizing the neutral gas — converting it into charged gas atoms. The more gas there is the faster this will proceed because avalanche ionization occurs, where each ionization event releases a new electrons

3. Predators have limitless appetite. Yes. A free electron will ionize a large number of gas particles due to its high reactivity

4. The rate of change of population is proportional to its size. Yes. The larger the quantity of ionized gas, the faster the free electrons can ionize it all. This is only true in a limited sense for the population of gas, see point 1.

5. During the process, the environment does not change in favour of one species and genetic adaptation is inconsequential. Yes. Although the environment can be engineered a priori.

5.1.7 Insights from the model

One proﬁts from applying this model, as it provides three key insights:

1. This model explains the oscillation in discharge current. Gas enters the thruster chamber with no net charge, so the current draw that one would measure on the power supply is small. Avalanche ionization occurs and the neutral gas is rapidly converted to charged gas, which is rapidly accelerated and ejected from the thruster after being neutralized in the virtual cathode. Our power supply will see the thruster draw much more current as this occurs, but the net charge of the system remains approximately zero. This ejection depletes the gas and the number of electrons exponentially declines. The neutral gas slowly ﬁlls up the thruster chamber and the cycle begins anew. Chapter 5. Power processing unit for a cylindrical Hall thruster 36

2. This model shows us how to manipulate the thruster to increase its performance through the δ coeﬃcient. The δ coeﬃcient puts a weight on how much population growth is obtained from an act of predation. In a Hall thruster, this can be controlled by adjusting the anode voltage. This increases the mean electron energy, increasing their reactivity and therefore increasing the strength of the avalanche ionization phenomenon.

3. If the system is only receptive to expelling ionized gas when the neutral gas population is restored, then we can save power by applying a driving voltage that oscillates at the predator-prey oscillation frequency of the thruster. Keeping the anode voltage at 300V consumes a great deal of power as P = IV , so reducing the mean voltage by a third while holding current constant reduces power consumption proportionally.

5.1.8 Realizing performance improvements in a Hall thruster

Research published in 2015 demonstrated a novel and power-eﬃcient pulse-synchronous driver system for Hall thrusters. By applying a pulsating anode voltage with a frequency close to the predator-prey oscillation frequency in the thruster, approximately 20 kHz, the researchers produced stable operation of a Hall thruster. This driving technique, shown in Figure 5.8 have many attractive features compared to the traditional technique, shown in Figure 5.5. It requires fewer parts that are also smaller, while thrust performance at a given power level is improved by 30%, measured at 200W input power. This oscillating anode voltage can be achieved with a canonical boost converter, shown in Figure 5.9 These insights will be included in the design of the PPU. Interestingly, it was found that the thruster predator-prey oscillations in current become synchronized to the anode driving voltage, so one only has to drive to within a few kilohertz of the breathing mode achieve the aforementioned performance improvements. Each particular thruster has a band of physically allowed frequencies, determined by the characteristic length of the thruster L, at which the current can oscillate [4].

Figure 5.8: An oscillating voltage on the anode drives a oscillating current Chapter 5. Power processing unit for a cylindrical Hall thruster 37

Figure 5.9: The canonical boost converter

5.2 Requirements

5.2.1 Diﬀerence between an engineering model and a ﬂight model

The goal of this project was to develop an engineering model (EM) that could be tested on a laboratory bench and easily probed and debugged. Furthermore, it was decided by the author to focus on achieving performance improvements demonstrated in the literature. This was to be realized by focusing on the development of the anode power electronics and to demonstrate operation of said as soon as possible. This is consistent with the microspace design philosophy practised at the SFL, which emphasizes rapid development cycles that reduce mission cost and increase the experience of the engineering team. As a result, this engineering model departs from a protoﬂight model is several ways.

1. The EM does not include a means of powering a cathode directly, since the characteristics of a flight-quality cathode (e.g. mechanism of electron emission) are underdefined and therefore cannot be designed for. However, the power needs of a suitable cathode are known in an approximate way, so the PPU provides sufficient power and an output for supporting an external cathode electronics board.

2. The EM does not include pressure and thermal control systems, as these can be built on a bread- board separately and the propulsion system mass flow regulation hardware is under-defined at the time of writing. In addition, these systems are not necessary for demonstrating successful operation of the anode supply. However, the power needs of a suitable valve system and a cathode heater are known in an approximate way, so the PPU provides sufficient power and an output for supporting a cathode heater and a valve system.

3. The EM is not miniaturized to the greatest possible extent, since this makes it harder to physically probe the PPU while debugging it and makes it harder to sink heat from hot components due to a smaller board having a smaller thermal mass.

4. The electromagnetic interference (EMI) produced by the board was not modelled using a rigorous method due to time constraints and due to the fact that an estimate of the deleterious eﬀect of this EMI would only be signiﬁcant when considered for a particular satellite with known geometry, materials, and EMI sensitivity. Best practices of PCB manufacturing and component layout were implemented to limit EMI.

5. The thermal behaviour of the EM PPU not modelled using multiphysics software, which would provide a superior estimate of the thermal characteristics of the board but at the cost of a signiﬁcant Chapter 5. Power processing unit for a cylindrical Hall thruster 38

time investment. To save time while still providing a suﬃcient estimate of part temperature, analytic thermal analysis was performed on a each part instead.

5.2.2 Customer requirements

The customer of this project is the SFL, which would like to oﬀer this Hall thruster propulsion system to its own customers. The thruster is operational but it cannot be used in space until a PPU exists. The SFL has a number of qualitative requirements that must be interpreted to produce functional requirements:

1. SFL desires that the PPU be capable of powering the proto-ﬂight thruster described in detail in [3], which puts the power requirement at 300W maximum.

2. The PPU should be constructed from flight heritage parts whenever possible because flight heritage parts have already been qualified for use in space. New parts must be subjected to thermal, radiation, and other testing, which makes them more burdensome to include. More generally, the customer requires that the PPU be constructed in compliance with its existing standards on parts, including derating for the space environment, connector integrity, part standards, etc.

3. The PPU should have as few parts as possible, to reduce cost and simplify testing.

4. The PPU shall use the Controller Area Network (CAN) communication protocol. Communication within SFL satellites is done over the CAN bus, so this would allow the PPU be easily integrated with an SFL satellite.

5. The PPU should be designed following best practices for limiting electromagnetic noise.

6. The PPU shall provide voltage, and current telemetry to the spacecraft OBC. This allows the operators of the spacecraft to monitor the state of the PPU.

5.2.3 Functional requirements

Based on the customer requirements above, functional requirements can be derived for the PPU. The requirements are shown in Table 5.1. They have been separated into four topics: power, thermal, control, and data. The PPU shall be controlled by a microcontroller that receives commands from the main spacecraft computer over CAN. Based on these commands, the microcontroller controls the four supplies that make up the power electronics. The requirements of the power supplies are described in Table 5.2. All values described for voltage, current, and power are maxima. The timescale of the component is a rough measure of how long that component operates for during a typical thrust that lasts ﬁve minutes. For example, the hollow cathode keeper can be thought of as analogous to a spark plug, and it draws a signiﬁcant amount of power but only on the timescale of tens of microseconds. The heater is somewhat special, since it is turned on to heat up the cathode before the cathode and the thruster are turned on, so its load is not applied the same time as the others. Chapter 5. Power processing unit for a cylindrical Hall thruster 39

Table 5.1: Requirements of the Cylindrical Hall thruster engineering model power processing unit

Topic Type Requirement Power Shall Shall supply a minimum of 200W to the thruster anode Power Should Should supply a minimum of 300W to the thruster anode Power Should The supply should have a power conversion efficiency of greater than 95% Power Shall The discharge supply shall be capable of sourcing 1A at 300 VDC Power Shall Shall be galvanically isolated from the rest of the spacecraft Power Shall This supply on the PPU shall source 0.28 A at 28 VDC for holding open the normally closed (NC) feed valve, which does not latch. Power Shall All components shall be derated according to ECSS specifications. Thermal Shall The temperature rise of a trace shall be no higher than 10◦C above 25◦C (ambient) Thermal Shall Shall be capable of operating continuously Thermal Shall The junction temperature of a part shall not exceed the rated temperature of the part minus 20◦C, or 110◦C, whichever is smaller. Thermal Shall The propulsion system shall survive, though not necessarily operate within specification, over a temperature range of -40C to +80C. Control Shall Shall require a command to arm before it can thrust Control Shall Should accept commands in the form: arm, fire, duration Data Shall Shall use a NSPv4 protocol over Controller Area Network (CAN)

Component Voltage [V] Current [A] Power [W] Timescale [s] Heater 40 1 to 1.2 50 102 Hollow cathode keeper 600 1.5 to 2 1200 10−4 Hollow cathode 15 1.5 to 2 30 constant Anode 200 to 300 0.5 to 1 300 constant Valves 28 0.28 8 1

Table 5.2: Electrical requirements of the ﬁve power supplies needed by the thruster

5.3 Methodology

5.3.1 Electrical

While the electrical requirements of the four power supplies on the PPU are known, the requirements for the hollow cathode are likely to change. This is because the hollow cathode that is currently used on SFL’s CHT could be modified to improve the efficiency of the thruster, which would change its electrical characteristics, including power requirements [3]. Therefore, it was decided to leave the design of the cathode power supply for future work and to focus on developing the anode electronics, which are where new discoveries can be exploited to produce higher thruster power efficiency. The approach here will be to design the PPU to provide power for the hollow cathode, while allowing the hollow cathode electronics that conditions this power to be designed on a separate board. Testing of the PPU on the CHT will Chapter 5. Power processing unit for a cylindrical Hall thruster 40 be accomplished by having cathode supply provided to the thruster by a laboratory power supply. This enables laboratory testing of the PPU on the CHT without the development of a separate cathode power electronics board. The first step of this design to to develop a circuit topology that allows for 12A of current at 28V to be electrically isolated from the spacecraft bus. This isolation requirement necessitates the use of a transformer. Since any inefficiencies on the board result in a proportional dissipation of the 300W throughput to be dissipated into the board as heat, this design necessitates the use of a switched-mode power supply (SMPS) to be thermally feasible, since an SMPS uses inductive and capacititive elements for energy storage, resulting in a higher efficiency. A isolated SMPS topology was selected that was best suited to the constraints of the design problem. Subsequently, this topology and the boost chopper circuit were simulated in a numerical electrical simulation program called LTSPICE. To save time, no other circuits of the final printed circuit board were modelled in LTSPICE. This can be justified by the complex behaviour of an isolated SMPS and the boost chopper, while the other circuits in the printed circuit board have simple behaviour that can be modelled analytically. The results from the simulation were checked with part parameters, which were derated according to SFL and ECSS standards, to perform requirement checks for each candidate part. With the SMPS topology and the boost chopper fully populated with suitable parts, the electrical schematic for these circuits and their supporting circuits can be created in Altium Designer, where the logical connections between all the parts in the printed circuit board are shown.

5.3.2 Derating parts for space

The European Cooperation for Space Standardization space product assurance derating guide was used to derate parts used in this device [23].

5.3.3 Thermal

The steady-state temperature of all parts should be estimated, to allow one to discriminate between suitable parts that remain within temperature limits and unsuitable parts that would overheat. There are two main sources of heating in integrated circuits and circuit elements that must be considered: Joule heating and switching losses.

Joule heating

Joule heating, often referred to as conduction losses, is modelled using (5.3), where I is the current ﬂowing through the circuit element and R is the resistance of that element. This simple analysis applies to resistors, traces, capacitors via their equivalent series resistance, and inductors via their direct current resistance.

2 Pjoule = I R (5.3)

MOSFET switching losses

Switching losses are modelled using (5.4), where VDS is the drain-source voltage, ID is the drain current, fs is the switching frequency, QGD is the reverse transfer charge (caused by the reverse transfer capac- Chapter 5. Power processing unit for a cylindrical Hall thruster 41

itance also known as Miller capacitance), and QGS2 is the gate-source charge. The last two quantities are found in the MOSFET datasheet [24]. An illustrative example is shown in Figure 5.10

QGD + QGS2 Pswitching = VDSIDfs (5.4) IG Switching losses are caused by the MOSFET storing and dissipating energy through its parasitic capacitance on each switching cycle. These losses are relevant to evaluating transistors used in the current-fed push-pull converter, the boost chopper, and the isolated 28V rail because their high switching frequency mean that the switching losses may be nearly as large as the conduction losses [24].

Figure 5.10: Understanding MOSFET switching losses [24]

Determining steady-state junction temperature

With the power dissipation determined, one can evaluate whether the electronic device or IC will operate within its deﬁned limits in compliance with derating requirements. The temperature of the semiconductor die inside the packaging is called the junction temperature.

This is calculated using (5.5), where ΘJA is the thermal resistance of the part obtained from the datasheet Chapter 5. Power processing unit for a cylindrical Hall thruster 42

or estimated for a similar package, TJ is the junction temperature, TA is the ambient temperature, and

PD is the power dissipation [25].

TJ = ΘJAPD + TA (5.5)

5.4 Electrical design

5.4.1 Architecture

The final electrical architecture of the power processing unit is shown in Figure 5.11. In this block diagram, power circuits are shown with white blocks and data handling circuits are shown with yellow blocks. Power flow is indicated with solid lines while information flow is indicated with dashed lines. The inputs are ground (not shown), an unregulated 28V supply (the voltage fluctuates over a range of 24V to 32V), and communication lines to the spacecraft’s on-board computer. The outputs are a 100V rail for powering the future hollow cathode power board, the 300V rail that powers the anode, an isolated ground (not shown), and an isolated 28V rail for powering the heater. The PPU is required to be isolated from the main spacecraft bus because this greatly reduces the possibility of large currents travelling into the bus from the thruster, which necessitates the use of an isolated SMPS topology that incorporates a transformer. Many isolated SMPS topologies are possible, of which push-pull is only one, so a suitable topology will be selected later in this chapter. Typically, SMPS require power transistors. These are large semiconductor switches that need a brief but substantial current on the order of 1 to 10A to charge the gate capacitance at a frequency demanded by SMPS, usually in the range of 0.1 MHz to 10 MHz. This driving current is provided by power transistor driver integrated circuits, which accept logic level inputs and output a driving signal. These drivers require a lower voltage than the bus input, so this necessitates a 15V source on the board. The microcontroller accepts 5V power, so this necessitates a 5V source on the board. The role of the microcontroller is to communicate with the spacecraft bus over serial and CAN and to control the 300V and 100V rails. For the microcontroller to control these two rails, error signals must be passed across an isolation barrier through some isolation circuit. For the boost converter, the driving logic must be passed across isolation as well. The main isolation converter that produces the 100V rail does not require that power transistor driving signals be passed across isolation since its power transistors are located on the microcontroller side of the PCB’s isolation barrier. This difficulty raises the question of why the microcontroller was placed on the non-isolated side of the power processing unit (PPU). This was done for two reasons: to reduce design complexity and to raise power efficiency. Placing the microcontroller on the isolated side would required that the CAN communications and the serial communications be passed across isolation, which necessitates adding a complicated digital isolator circuit and an analog to digital converter. Furthermore, if the microcontroller were on the isolated side of the board, it would still need to pass drive signals across the isolation barrier back to the MOSFET drivers that drive the push-pull converter’s MOSFETs, so there is additional overhead there. Chapter 5. Power processing unit for a cylindrical Hall thruster 43

Figure 5.11: Power processing unit block diagram

5.4.2 Selecting an isolated switching-mode power supply topology

Following a literature review, four candidate converter topologies were compared: resonant, push-pull, half-bridge, and full-bridge. The results of this qualitative trade study are shown in Table 5.3. After reviewing the design trades, the resonant and full-bridge converters were ruled out due to how complex they are to implement and the high peak current on the resonant converter. The half-bridge was ruled out because its transistors see double the current but half the voltage that the push-pull converter sees, which causes additional stress on the transistors and increases conduction losses. The halved voltage stress in the half-bridge compared to the push-pull is not a signiﬁcant advantage, since the input voltage is only a maximum of 32V. The push-pull converter maintains a high volumetric power density, a useful attribute in a microsatellite power supply. Therefore, the push-pull topology was selected. Chapter 5. Power processing unit for a cylindrical Hall thruster 44

Table 5.3: A trade study of isolated DC-DC converter topologies

Name Advantages Disadvantages Resonant

• Zero current or zero voltage switch- • Higher peak currents ing • Complex to engineer • Low component stress

• Low electromagnetic interference

• Improved diode recovery

Push-pull

• Compact transformer and output ﬁl- • Each transistor must block twice the ter input voltage

• Small output voltage ripple • Prone to ﬂux symmetry imbalance results in saturation at high input • Typically used in the 100W to 500W voltages range

• High power volumetric density

Half-bridge

• Transistors never see a voltage • One transistor must have an isolated greater than the input voltage drive

• No problems with transformer satu- • High complexity and cost usually ration exclude use of this system at over 500W • Low output ripple • Better suited to high voltage input • Zero voltage switching possible (e.g. mains)

Full-bridge

• Very high power and current • High voltage across the auxiliary switch • Low output voltage ripple • Isolated drive for two ﬂoating poten- • Zero voltage switching possible tial transistors is required

• Complex to engineer Chapter 5. Power processing unit for a cylindrical Hall thruster 45

5.4.3 Current- and voltage-fed push-pull converters

Once the push-pull topology was determined to be optimal for this application, the choice was between two topologies of the push-pull converter: current-fed and voltage-fed. A voltage-fed converter, shown in Figure 5.12, has a serious failure mode called shoot-though. This occurs when both switches conduct simultaneously. In this situation, the transformer perceives no net current and hence no net magnetization, so it behaves as if it is a short. Therefore, there will be little impedance between the input voltage and ground, causing a large shoot-through current that could destroy the switch [26].

Figure 5.12: Circuit diagram of voltage-fed push-pull converter [26]

To avoid this failure mode, the voltage-fed topology requires dead time between the turn-on of the switches. During this dead time, the diodes on the secondary side of the transformer free-wheel as the inductor on the secondary side generates a current. This freewheeling current must be cancelled out the next time the switches close. This situation can result in a low impedance path across the voltage source due to the diode turn-off time, which would cause transformer saturation if the voltage-time product were large enough compared to that of the transformer. This problem of flux imbalance is a major one for voltage-fed converters, and can cause serious damage. Moving the inductor to the primary side of the transformer, as shown in Figure 5.13, creates a current-fed converter. This change resolves these problems by creating an instantaneous high impedance, which restricts sudden changes in current. Furthermore, this inductor on the centre-tap reduces turn-on and turn-off transients, limits flux imbalance, and restricts transformer saturation [27]. Another small benefit is that having long lead lengths connecting to the input is no longer as issue, since the inductance of the wires is negligible compared to the input inductor L, which means that this power processing unit can be mounted at a substantial distance from the spacecraft power system, if necessary [27].

Operation

A current-fed push-pull converter’s transfer function is shown in (5.6). The number of turns of wire around the transformer on the primary and secondary sides are deﬁned as Nprimary and Nsecondary respectively, Vin is the input voltage, and D is the duty cycle of the switch (i.e. the fraction of time it Chapter 5. Power processing unit for a cylindrical Hall thruster 46

Figure 5.13: Circuit diagram of current-fed push-pull converter [26]

is on divided by the period). The current-fed push pull converter derives its name from the inductor L on the centre tap of the transformer. This inductor causes the converter to resist changes in the input current, hence it is constant-current or current-fed [27].

Nsecondary 1 Vout = Vin (5.6) Nprimary 2(1 − D) The converter’s function in this application is to take an input of 24V to 32V and to boost the output voltage to 100V. The output voltage is kept at a steady value of 100V by varying D. The exact value of D is determined by numerical calculations on the microcontroller. Software control of SMPS is a challenging task, and will be described in Chapter 5. A current-fed push-pull converter works by rapidly toggling on and off two switches, Q1 and Q2, at a frequency f and a period T , typically in the range of hundreds of kHz to low MHz. During the switching cycle, inductive and capacitive elements store energy and are used to boost the output voltage. An illustration of the driving waveforms for each transistor is shown in Figure 5.14. Q1 and Q2 are intentionally operated in the overlapping mode where the duty cycle, D, of each switch is greater than 0.5 and one switch is delayed by half a period relative to the other, so that as D increases the amount of overlap increases. During this period of switch overlap, indicated by the shaded region in Figure 5.14, there is no net flux in the transformer, as the primary windings NP 1 and NP 2 are both conducting but in opposite directions. The primary windings appear shorted to ground through the switches, so the transformer is effectively shorted to ground. The inductor L sees Vin applied across it, which induces a linear rise in current through it. Since there is no voltage on the primary side of the transformer, there Chapter 5. Power processing unit for a cylindrical Hall thruster 47 is no voltage induced on the secondary side, so the output capacitor sustains the load on the secondary side and the inductor current is divided between the two switches during this off period, which is defined in (5.7) [27].

1 t = (D − )T (5.7) oﬀ 2

The off period, toff, elapses and ton, defined in 5.8, begins when one switch, let it be Q1, becomes non- conducting as directed by the control system. Now Q2 carries the full inductor current. The inductor develops a negative voltage across it as it sustains the current into the transformer. As the inductor discharges the energy stored in its magnetic field, the current it drives drop linearly as it drives current into the transformer’s upper primary. This energy is in turn supplied to the output capacitor and to the load on the secondary side. The switches alternate between conducting and not conducting at each new ton period [27].

T 1 1 t = − (D − ) = (D − )T (5.8) on 2 2 2

Figure 5.14: Gate drive pulse-width modulation of current-fed push-pull converter

Circuit parameters

Using the design methodology described in [27], the components of current-fed push-pull converter were selected. The inputs into the design method are Vin,min = 24V , Vin,max = 32V , Vout = 100V , the maximum power throughput Pout = 300W , the switching frequency fs = 200kHz, and the desired converter eﬃciency η = 95%. This information was used to set the average centre tap voltage in (5.9), which is set to be 5% higher than the maximum input voltage. The trade here is that a lower average centre tap voltage voltage reduces the stress on the switches, while a higher centre tap voltage reduces the duty cycle required to achieve the required output voltage. In this case, even the maximum duty cycle is not anticipated to exceed 0.65, which is quite standard in the literature, so the centre tap voltage can safely be set using the value of 105% of the maximum input voltage without compromising the switches with an overly high duty cycle that might cause them to overheat. Chapter 5. Power processing unit for a cylindrical Hall thruster 48

Vct = 1.05Vin,max = 1.05(32V ) = 33.6V (5.9)

The maximum duty cycle can be calculated as shown in (5.10). It occurs when the input voltage is at a minimum.

Vin,min 28V Dmax = 1 − = 1 − = 0.64 (5.10) 2Vct 2(33.6V ) The minimum duty cycle can be calculated as shown in (5.11). It occurs when the input voltage is at a maximum.

Vin,max 32V Dmin = 1 − = 1 − = 0.52 (5.11) 2Vct 2(33.6V )

Dmax allows one to calculate the volt-second product, λ, that we need in (5.12), which measures the magnetic ﬂux in the transformer. The transformer used in this design must have a volt-second value greater than λ so as to not reach magnetic saturation [28].

Vin,max λ = Dmax = 103V − µs (5.12) fs Now, the turns ratio can be calculated in (5.13):

N V n = primary = out = 0.34 (5.13) Nsecondary Vct The average input current can be calculated as shown in (5.14) using the conversion eﬃciency, input power, and the minimum input voltage:

Pout 300W Iin,average = = = 13.16A (5.14) ηVin,min (0.95)(24V ) The design trade on inductance is that on one hand, the higher the inductance the more the converter can resist changes in load current without affecting the output voltage. On the other hand, a higher value of inductance is associated with a physically larger part. To select the minimum size inductor, it should be sized so as to put a limit, x, on the allowable current ripple magnitude ∆I. In the literature, values in the range of 0.05 and 0.3 are typically sufficient [27]. This application stretches the application of generalized formulas or rules of thumb prepared for less demanding applications, since the boost chopper is a periodic and substantial load on this line. Thus, a simulation of the circuit was used to estimate an appropriate value for x. The final value of 2% was determined by iteratively adjusting input inductance and measuring the ripple that resulted. The result is shown in (5.15).

∆I = xIin,average = (0.02)(13.16A) = 0.26A (5.15)

We can solve for the inductance by evaluating the input voltage as a function of the centre tap voltage as shown in (5.16).

2L∆I Vin = 2Vct(1 − D) = (5.16) toﬀ Substitute (5.7) into (5.16) and re-arrange to obtain (5.17). Chapter 5. Power processing unit for a cylindrical Hall thruster 49

1 L∆I = V 2(1 − D)(D − )T ct 2 (5.17) V = ct (3D − 1 − 2D2) 2fs

By setting D = Dmax = 0.64, from (5.11), (5.18) can be derived.

V ∆I = ct (5.18) 16Lfs

(5.18) can be re-arranged a ﬁnal time to obtain (5.19), which shows the minimum value of L in terms of the centre-tap voltage, the allowed current ripple, and the switching frequency.

V L = ct 16fs∆I 33.6V L = (5.19) (16)(200 kHz)(0.26A) L = 40µH

Now attention can be turned to the output capacitor. The energy stored in a capacitor is described in (5.20):

1 E = CV 2 (5.20) 2 During the oﬀ period the load is sustained by the output capacitor alone, so it must be sized so that it does not discharge during the oﬀ-period. This equality can be written as in (5.21). T is the switching period.

1 2 2 ∆E = C(Vd,max − Vd,min) = Pouttoff 2 (5.21) 1 ∆E = P (D − )T out 2

Equation 5.21 can be re-arranged to form (5.22), an expression for the capacitance under this constraint.

Pout(2D − 1) C = 2 2 (5.22) (Vd,max − Vd,min)fs

Here, the allowable peak-to-peak voltage ripple, y, is set in (5.23):

∆Vp−p = yVout (5.23)

Then the output voltage can be re-written in (5.24): Chapter 5. Power processing unit for a cylindrical Hall thruster 50

Vd,max = Vout + ∆Vp−p (5.24) Vd,min = Vout − ∆Vp−p

Now the minimum capacitance value can be solved for in (5.25). Normally, allowing a 1% ripple would be suﬃcient, but since there is a boost chopper that is periodically and heavily loading on the output of this supply, this will be increased by a factor of ten to avoid voltage sag caused by the capacitor becoming discharged.

Pout(2D − 1) C = 2 4yVoutfs (300W )(2(0.64) − 1) C = (5.25) 0.01V 2 (4)(( 10 )(100V ) (200 kHz) C = 8µF

With this information, a thorough numerical model of this circuit can be developed. First, the boost chopper will be explored, as the push-pull circuit was numerically modelled with the boost chopper for ease of simulation.

5.4.4 Boost chopper

The circuit shown in Figure 5.15 is based on the work in [4]. It is the canonical boost converter, with the transfer function shown in (5.26), but operating in the discontinuous conduction mode - meaning that the switch is operated with a short duty cycle so the voltage delivered to the anode spikes to 350V before dropping to 100V, at a frequency of 15 to 25 kHz. The authors of [4] found that the amplitude of the output pulses was increased when the size of the output capacitor decreased. In addition, they found that capacitors in the range of 0.5 to 1 µF provided the optimal output for their thruster. Since SFL’s thruster differs subtly from that in the paper in terms of predator-prey oscillation frequency (20 vs. 10 kHz), current draw, and operation voltage, this range of capacitance can be used as a starting point but due to the different physical nature of the CHT compared the the thruster in [4], the correct value of capacitance will need to be confirmed experimentally. Appropriate parts were selected that met or exceeded the ECSS derating criteria.

1 V = V out in 1 − D (5.26) 1 Vout = Vin 1 − tonfs

5.4.5 Circuit simulation using numerical methods

The analytic model of the boost chopper and the current-fed push-pull converter was used to develop a numerical model of these two circuits in LTSPICE. The numerical results are shown in Figures 5.16, 5.17, and 5.18. This numerical model did not include a feedback loop to stabilize the output in response Chapter 5. Power processing unit for a cylindrical Hall thruster 51

Figure 5.15: Circuit diagram of pulsating boost chopper[4]

to changes in load nor did it include soft-start on the boost chopper. This was done intentionally to to reduce the simulation time and to simplify the model. Both of these features will be included in the device. With those two features included, the results for the 100V rail voltage would be smoother without rises and falls in voltage in response to the boost chopper loading, such as those found from 0.2 ms to 1.4 ms on Figure 5.17, for example. In practice, the current-fed push-pull converter will be soft-started at a rate that allows the controller to smooth out the voltage peaks.

Figure 5.16: Anode voltage simulated using LT Spice. The target voltage is 300V.

Figure 5.17: 100V rail voltage simulated using LT Spice. The target voltage is 100V Chapter 5. Power processing unit for a cylindrical Hall thruster 52

Figure 5.18: Anode current simulated using LT Spice. The target current is 1A

One might notice that the amplitude of the boost chopper oscillations in Figure 5.16 is on the order of 40V, while the oscillations demonstrated in [4] and shown in 5.8 are on the order of 60V. The amplitude of these anode voltage oscillations can be increased by using a larger or smaller capacitor. This effect is shown in the following two plots. Figure 5.19 shows the anode voltage of a boost chopper that has a 0.5 µF capacitor and the oscillation has an amplitude of roughly 40V peak-to-peak. Figure 5.20 shows the anode voltage of a boost chopper that has a 0.25 µF capacitor and the oscillation has an amplitude of roughly 70V peak-to-peak. The obvious importance of the boost chopper output capacitor drove a specific design decision. The output capacitor is made of two 0.25 µF capacitors in parallel, allowing for easy tuning of the anode oscillation amplitude by removing one capacitor. Also, capacitors of different values but with the same footprint can be procured and substituted for one or both 0.25 µF capacitors.

Figure 5.19: Anode voltage simulated using LT Spice. The target voltage is 300V with a 50V peak-to- peak oscillation Chapter 5. Power processing unit for a cylindrical Hall thruster 53

Figure 5.20: Anode voltage simulated using LT Spice. The target voltage is 300V with a 70V peak-to- peak oscillation

An important quality of the current-fed push-pull converter is resonance in response to ripple on the input voltage. If a converter is too sensitive to resonance, then the voltage oscillations at the output could be damaging to parts on the secondary side of the transformer. Analytically, the resonance frequency was found to be approximately 1.5 kHz using the method from [29]. LTSPICE cannot perform a frequency sweep when there are active components like transistors involved, but an alternative method of doing a frequency sweep with a sine wave of 2V peak-to-peak superimposed on a 28V input at varying frequencies can be used. The results were that the converter resonated at approximately 1.5 kHz, with the gain dropping off rapidly beyond 0.5 kHz and 2 kHz. The maximum peak-to-peak amplitude at resonance was found to be 19V. which is manageable and will not present problems in the design. The location of this resonance peak matches what was found using analytical calculations performed in the next chapter, shown in Figure 6.5. One important finding, shown in Figure 5.21, is that with 10 µF of capacitance on the output of the current-fed push-pull converter, the output ripple with the boost chopper on was less than 1V. Recall that the calculated value for output capacitance was 8µF. This result is important for two reasons. First, it gives credibility to the analytic results. Second, it shows that it is possible to implement software control. This last point is not obvious, and will require elaboration. Based on the organization’s experience on previous missions, the flight-heritage microcontrollers used at SFL can adjust the duty cycle at approximately 300 Hz. This allows the microcontroller to adjust the duty cycle of the switches at a rate that will allow noise at frequencies of 100 Hz or less to be compensated out, due to the Nyquist limit. The magnitude of the boost chopper’s loading on this rail at 20 kHz exceeds all other loads by an order of magnitude in the frequency regime of >100 Hz. The effect on the 100V rail is negligible even in this worst-case, as proven by the small amplitude of the perturbations of the 100v rail voltage shown in Figure 5.17 after 1.6 ms of simulation. Therefore, it is Chapter 5. Power processing unit for a cylindrical Hall thruster 54 safe to shape the loop gain to have a crossover frequency at 300 Hz but no higher. This means that the microcontroller will only see and act on perturbations at 100 Hz or less. Therefore, software control can be used instead of hardware control, which allows easier and more rapid prototyping and testing. This will be discussed in greater detail in the next chapter.

Figure 5.21: 100V rail voltage simulated using LT Spice

5.4.6 Supporting components

With the design of the boost chopper and the current-fed push-pull converter fully developed, attention must now be turned to the circuits and components that support the operation of those two core modules. Brieﬂy, these circuits and components include fuses, power transistor drivers, feedback across isolation, and range low voltage sources.

Re-settable fuse

The function of this fuses on the unregulated 28V input into the printed circuit board is to protect the power supply from being damaged by the PPU drawing too much current. A re-settable fuse will be used, since the fuse may need changing during testing.

Power transistor drivers

These power transistor drivers are integrated circuits that accept a logic-level input and output a large current that is used to drive the power transistors. These driver integrated circuits are rated based on their peak output current because the larger the peak output current the faster the transistor’s gate charge can be charged, meaning that it can change between conducting and non-conducting states faster, which is to say that the switching frequency is faster. This relationship is described in (5.27) and (5.28). In this design three such drivers are needed: one for the boost chopper and two for the current-fed push-pull converter. For the current-fed push-pull converter driver. Chapter 5. Power processing unit for a cylindrical Hall thruster 55

1 Ioutput,peak 6A fs = = = = 95 MHz (5.27) T Qgate 63nC For the boost chopper driver.

1 Ioutput,peak 6A fs = = = = 133 MHz (5.28) T Qgate 45nC

The requirement for the boost chopper’s power transistor driver is to be able to switch at at 20 kHz or less. The requirement for the current-fed push-pull converter’s power transistor drivers is to be able to switch at 200 kHz or less. In both cases the driver can drive the transistors at a frequency far higher than the required frequencies of 200 kHz and 20 kHz, so a power transistor driver with a 6A output is more than suﬃcient.

Voltage rails

Various supply voltages are needed on the board to supply the various circuits. These rails cannot be shared across the isolation barrier. As can be seen in Table 5.4, all of these rails have suﬃcient capacity to meet requirements.

Table 5.4: Voltage rails requirements check

Isolated Voltage [V] Requirement [mA] Capability [mA] Compliant No 5 25 50 Yes No 15 51 100 Yes Yes 5 26 50 Yes Yes 15 13 50 Yes Yes 28 1770 2000 Yes

Isolated feedback

According to requirements, there must be galvanic isolation between the primary and secondary side of the transformer to protect the rest of the spacecraft. However, feedback signals must still be passed across this barrier. Many technologies exist for this application including isolation amplifiers using transformers, digital isolators, and optocouplers. Isolation amplifiers mix an analog signal onto an AC waveform, which is passed over a transformer. Digital isolators pass digital signals only, so they require an analog to digital converter on the input. Optocouplers feed an analog signal into a light-emitting diode that faces a phototransistor. Typically, optocouplers are not used in space applications as they degrade in the space environment. However, they are the easiest to implement, so for this prototype device they are sufficient.

5.4.7 Eﬀect of layout on electromagnetic interference

Electromagnetic interference, or EMI, is deﬁned by [30] as unwanted coupling between one circuit or system to another. Conducted EMI is undesired coupling of signals through parasitic impedences, power, and ground connections. Radiated EMI is undesired coupling through radio transmission. The latter category is produced by a PCB and can negatively aﬀect the operation of the PCB or other electronic Chapter 5. Power processing unit for a cylindrical Hall thruster 56 components in the spacecraft by inducing current through inductive coupling or inducing voltage through capacititive coupling [30]. The PPU is not associated with a particular mission that has EMI requirements and predicting the intensity of EMI before testing is not trivial, since it is a multiphysics problem that must be solved for a particular set of boundary conditions including geometry and materials. Due to the absence of a spacecraft providing quantitative EMI limits, no requirements were provided that would set a quantitative limit on the electromagnetic interference (EMI) that the PPU is allowed to produce, but there is still a qualitative customer requirement that the EMI be limited to being as low as possible, as this would allow the PPU to be carried on the largest set of candidate spacecraft. In this environment, one can employ the strategy of following best design practices, such as careful layout of power stage components and a particular PCB layer sequence, to limit EMI without performing challenging and time-consuming multiphysics analysis. This can be followed up by measurements on the PCB when it is being tested.

5.4.8 Printed circuit board layers

When designing a PCB, EMI is managed by following certain best design practices. If the board is a multilayer board, then the ground plane should be placed between the small-signal layer and the high current power component layer, which shields the small signal traces from the noisy traces that carry current to the power components. In a four-layer board, the correct stack-up is as follows [31].

1. Power components

2. Ground plane

3. Small signal

4. Small signal/controller

Other conﬁgurations increase the capacititive noise coupling between the high current/voltage power layer and the small analog signal layer [31].

5.4.9 Power stage component layout

Beyond the obvious step of making high current traces short and wide to minimize inductance, resistance, and the resulting voltage drop, it is important to minimize the inductance of loops where current changes rapidly over time (i.e. high di/dt). Such regions are found in SMPS particularly around transistors. Due to the parasitic inductance of traces, these pulsating current regions radiate magnetic ﬁelds and also generate voltage ringing and spikes. To minimize these undesirable eﬀects, the pulsating current loop should have a small circumference and use short and wide traces. A decoupling capacitor can be used to decouple high frequency noise [31]. High change in voltage over time (i.e. high dv/dt) nodes are of concern as they are also a strong source of EMI. These nodes are found in SMPS around transistors where the voltage swings between

Vin and Vout. This voltage swing causes capacititive coupling between the switching node and nearby noise-sensitive nodes. To limit this eﬀect, the area of this copper should be minimized. However, this must be balanced by the need for suﬃcient copper to conduct large currents and to provide a heat sink Chapter 5. Power processing unit for a cylindrical Hall thruster 57 to a heat-producing part, such as a power MOSFET. Furthermore, a copper plane connected to ground beneath the transistor provides additional EMI shielding to other components on the board [31].

5.5 Controller design

A microcontroller was selected with space heritage that supports CAN communications and has two internal programmable counter arrays (PCAs). These allow the microcontroller to supply two PWM outputs with adjustable duty cycles at two different frequencies. The datasheet was used to determine that it is possible to set one PCA PWM output to a frequency of 191 kHz to drive the push-pull converter and the other to 12 kHz to drive the boost chopper MOSFET drivers. The consequence of driving the push-pull converter at a slightly lower frequency is that slightly larger output inductance and input capacitance are needed, but these components were selected conservatively from the start of the design process, so this slight increase can be absorbed without increasing the risk of the design. The consequence of a slightly higher driving boost chopper driving frequency is harder to anticipate but based on other results, it should cause no ill effect. The breathing mode frequency of the thruster should synchronize with the driving frequency over a small range of frequencies as shown in [4], where synchronization was observed over a range of 12 to 26 kHz. Of course, this was for an annular thruster while the SFL thruster is cylindrical. The plasmadynamics are slightly different for these two geometries primarily due to the axial vs. cusped magnetic field causing different movement of electrons, so the question of whether the 10 kHz breathing mode of the SFL thruster will increase to 12 kHz and synchronize with a 12 kHz driving signal can only be confidently answered through experimentation. The schematic of the microcontroller circuitry was inherited from an earlier SFL design. However, an integrated circuit was added near the microcontroller to allow it to control the push-pull converter. This IC accepts an input and outputs the exact same signal with a programmable delay. The purpose of this IC is to accept a PWM signal from the 200 kHz PCA on the microcontroller. This signal is split at the microcontroller, with one branch going to one push-pull converter driver and the other branch, fed into the delay IC, is delayed by half a period and passed to the other push-pull converter driver. This timing arrangement is required to achieve the gate driving waveforms shown in Figure 5.14 and discussed in Section 5.4.3 on page 45.

5.6 Thermal design

5.6.1 Evaluating the junction temperature of critical components

Power dissipation values were calculated for candidate parts using the methodology described in Section 5.3.3 on page 40. This value was used in conjunction with the thermal resistance of the part to calculate the steady-state temperature of the part and to determine if it meets requirements, based on the pro- jected steady-state temperature. As can be seen in Table 5.5, all parts meet the junction temperature requirements. Further calculations were performed for resistors and other components to ensure that they can meet requirements. Due to the large number of calculations and to considerations of brevity these will be omitted. Chapter 5. Power processing unit for a cylindrical Hall thruster 58

Table 5.5: Thermal design requirements check for critical components

◦ ◦ Part Pjoule[W] Pswitch[W] TJ,calc[ C] TJ,max[ C] Pass Boost chopper MOSFET 0.47 0.34 46 110 Yes Push-pull MOSFETs 1.09 0.18 82 110 Yes 28V rail MOSFETs, Isolated 0.06 0.02 33 110 Yes 15V source IC, Isolated 0.68 N/A 59 110 Yes 5V source IC, Isolated 1.18 N/A 84 110 Yes 15V source IC 0.21 N/A 34 110 Yes 5V source IC 0.52 N/A 51 110 Yes

5.6.2 Evaluating the steady-state temperature of critical traces on the push- pull converter

According to requirements the temperature rise of a trace shall be no higher than 10◦C above 25◦C (ambient). The set of high current traces were evaluated at their smallest width to obtain the worst-case temperature rise. This set was obtained by noting that the high-current traces are located on the primary side of the current-fed push pull converter transformer (i.e. the non-isolated side that is galvanically connected to the bus). This is because the voltage is upconverted over the push-pull converter, resulting in much smaller currents on the secondary side of the transformer. As a result, the traces to be studied are all associated with the push-pull converter. The results are shown in Table 5.6. The smallest width is often found at the interface between the trace and a component, since the certain components have smaller interface areas than others. The nodes of interest are shown in Figure 5.22. The Vbus trace is shown in blue, the push-pull MOSFET drain and source in red, the secondary side rectifying diodes in green, and the secondary side ground in purple. The temperature rise was calculated for 1 oz (35 µm) and 2 oz copper (70 µm) to determine if it was necessary to manufacture the board with thicker copper. The convention for describing copper thickness on a PCB is ounces per square foot, with the per unit area descriptor usually omitted. All traces fulﬁlled the temperature rise requirement at 1 oz copper so it is not necessary to manufacture with 2 oz copper. A thicker copper layer would help to sink heat from components and ICs, but due to the copper etching process in PCB manufacturing the thicker the copper that is used the wider the minimum trace width. As a consequence for this design, using 2 oz copper would disqualify several ICs that met requirements due to the gap between their leads being too small, requiring the part selection process to restart. Chapter 5. Power processing unit for a cylindrical Hall thruster 59

Figure 5.22: Nodes of interest for evaluating trace temperature

Table 5.6: Thermal design requirements check for traces

Trace Current[A] Width[mm] Rating, 1 oz[A] Rating, 2 oz[A] Pass at 1 oz Vbus 12.0 12.0 28.8 57.6 Yes Push-pull 8.4 5.0 12.0 24.0 Yes MOSFETs Diodes on 2.1 2.0 4.8 9.6 Yes secondary side Ground on 3.1 3.0 7.4 14.88 Yes secondary side

5.6.3 Eﬀect of layout on component thermal stress

Heat sinks are often used to prevent high power parts, such as power MOSFETs and inductors, from overheating. However, these increase the volume and mass of the PCB. It possible to forego heat sinks by using suﬃcient area of copper underneath the part to act as a heat sink and spread heat more evenly throughout the board. This technique was used on this PCB. Chapter 5. Power processing unit for a cylindrical Hall thruster 60

5.7 Results

The PCB was manufactured externally using the design ﬁles created in Altium designer by the author. The unpopulated board is shown in Figure 5.23. After inspection, components were soldered onto the PCB by technicians at the SFL. The populated board is shown in Figure 5.24. Part numbers have been obscured in compliance with the federal government’s regulations on controlled goods. A summary of the results compared to requirements is shown in Table 5.7. These results are based on the theoretical performance of the EM PPU and does not include the results from testing.

Figure 5.23: Unpopulated Hall thruster power supply PCB

Figure 5.24: Populated Hall thruster power supply PCB Chapter 5. Power processing unit for a cylindrical Hall thruster 61

Table 5.7: Requirements check for the Cylindrical Hall thruster engineering model power processing unit

Topic Type Requirement Compliant Power Shall Shall supply a minimum of 200W to the thruster anode Yes Power Should Should supply a minimum of 300W to the thruster anode No Power Should The supply should have a power conversion efficiency of greater No than 95% Power Shall The discharge supply shall be capable of sourcing 1A at 300 VDC Yes Power Shall Shall be galvanically isolated from the rest of the spacecraft Yes Power Shall This supply on the PPU shall source 0.28 A at 28 VDC for holding Yes open the normally closed (NC) feed valve, which does not latch. Power Shall All components shall be derated according to ECSS specifications. Yes Thermal Shall The temperature rise of a trace shall be no higher than 10◦C Yes above 25◦C (ambient) Thermal Shall Shall be capable of operating continuously Yes Thermal Shall The junction temperature of a part shall not exceed the rated Yes temperature of the part minus 20◦C, or 110◦C, whichever is smaller. Thermal Shall The propulsion system shall survive, though not necessarily op- Yes erate within specification, over a temperature range of -40C to +80C. Control Shall Shall require a command to arm before it can thrust Yes Control Shall Should accept commands in the form: arm, fire, duration Yes Data Shall Shall use a NSPv4 protocol over Controller Area Network (CAN) Yes

5.7.1 Power

Based on the parts that were selected, the maximum throughput power of the PPU is 300W. This limit is driven by the transformer power rating. According to the requirements described in Table 5.2 on page 39, the cathode supply, the valves, and the heater require 30W, 8W, and 50W, respectively. A total of 38W of the 300W throughput capacity are allotted to needs other than anode driving. The heater is operated before the thruster is powered, so it can be excluded from this calculation. With 262W remaining, the PPU is compliant with the requirement to drive 200W to the thruster anode. The preference to provide 300W to the thruster anode is not fulfilled. The high power requirement of the hollow cathode keeper is extremely brief and therefore can be sustained by capacitors in the keeper electronics board. To summarize, all of the supplies in Table 5.2 can be powered from the engineering model PPU. To determine the efficiency of the PPU, the power dissipation was calculated in each component and compared to the theoretical maximum throughput of 300W. This is summarized in Table 5.8. The overall efficiency was found to be 93%, which is not compliant with the efficiency requirement of 95%. Other losses that not considered in this calculation might reduce this figure further by 1 to 2 Chapter 5. Power processing unit for a cylindrical Hall thruster 62

Table 5.8: Calculated losses in each component of the PPU and the expected eﬃciency

Item Sub-item Losses in sub-item [W] Losses in item [W] Main Supply 15.0 Input inductors in series 5.13 MOSFETs 2.55 Transformer Primary 0.99 Transformer Secondary 0.06 Diodes 6.30 Output capacitor 0.005 Boost Chopper 3.6 Input inductor 0.73 MOSFET 0.81 Diode 2.10 Output capacitor 0.01 ICs 3.6 Microcontroller 0.075 MOSFET Drivers 0.23 100V rail controller 0.80 15V rail controller 0.05 Isolated 28V to 15V Rail 0.68 Isolated 28V to 5V Rail 1.18 15V to 5V Rail 0.52 Isolation ICs 0.03 Error Ampliﬁer 0.08 Sum of items 22.3 Throughput 300 Eﬃciency 93%

This calculation does not include conduction losses in traces and connectors, or hysteresis and eddy current loss in the transformer. These losses are time-consuming to calculate and will not add up to a large loss. The exact conduction loss in traces and connectors is expected to be small due to the short and wide traces, which have low resistance, and the low resistance of the connectors. Hysteresis and eddy current losses are proportional to the switching frequency f, which is 200 kHz. This value is on the lower end of the allowed range for the transformer, so the loss is expected to be small. Overall, the efficiency is quite good for an engineering model. The 95% requirement was inherited from the protoflight requirements, making them overly stringent for the level of technical readiness in- herent in an engineering model. To raise the efficiency of the protoflight model to meet requirements, higher quality components with lower conduction losses can be used - particularly inductors and MOS- FETs on the main supply where the majority of the losses are. A particular kind of semiconductor switching called a Gallium Nitride Field Effect Transistor (GaNFET) can be used to reduce the main supply MOSFET losses to nearly zero. Another step would be putting extra diodes in parallel on the Chapter 5. Power processing unit for a cylindrical Hall thruster 63 main supply and on the boost chopper. Having two diodes in parallel where previously there was only one would reduce the current in each diode of half of what it was previously. The voltage drop across a diode is constant, so this would result in halving the power loss in the diodes. The steps described above would raise the efficiency to 95% The maximum RMS voltage achievable at on this PPU is approximately 480V, with a 100V peak-to- peak oscillation at 10 kHz. The RMS anode voltage can be controlled by adjusting the duty cycle on the boost chopper. Therefore, the requirement of 300V at the anode is satisfied, with room for improvements in power efficiency because Hall thrusters are more efficient at a higher anode voltage.

5.7.2 Control and data

All requirements related to control and data have all the required infrastructure present on the EM PPU. However, the necessary software must be now be implemented on the microcontroller.

5.7.3 Thermal

All thermal requirements have been met, as described in Section 5.6 on page 57.

5.8 Testing

5.8.1 Anode driving

The most important function to be tested is whether or not the PCB can output the desired driving waveform to the load bank for an extended period. This is a high-level function compared to others on the board, since it relies on the microcontroller to correctly control the push-pull transistor drivers and the boost-chopper transistor drivers, to correct read feedback across galvanic isolation, and to correctly alter the duty cycle. To test this waveform, a load of some kind must be used. This could be the thruster or a simulated load of some kind. Due to cost constraints, testing could not be performed on the thruster itself. Therefore, a suitable artificial load had to be created or purchased that was capable of sinking an 20 kHz alternating current of approximately 1A at a peak value of 400V. The reason that the output voltage could be somewhat higher than the nominal peak of 300V, up to 400V, is that the board is being calibrated, so the boost chopper could boost the voltage higher than expected. One concern was whether it was important for the load to accurately model the subtle electrical characteristics of a Hall thruster, such as reactive inductance and reactive capacitance, beyond that of simple impedance. In [32] the electrical characteristics of the thruster being driven using a boost chopper were investigated. It was found that a phase difference between current and voltage exists, and that it is, in the words of the authors, almost identical as that of a series LC (inductor-capacitor) circuit. This has important consequences for how the thruster behaves as a load. Recall that capacititive reactance decreases with frequency while inductive reactance increases with frequency. This means that for low frequencies, the thruster acts as a capacititive load. In this situation, the phase of the current leads the voltage. For high frequencies, the thruster acts like an inductive load and the phase of the current lags [32]. Fortunately, the phase lag at the operating frequency of 20 kHz was found to be approximately 10 µs, which is so small for the purposes of devising a simulated load that is is negligible [32]. Therefore, Chapter 5. Power processing unit for a cylindrical Hall thruster 64 it was decided that the load bank could be purely resistive, with no significant amount of reactance - since this also results in a phase lag of zero.Now one can move on to the question of how the load bank should be constructed.

5.8.2 Load bank

The load bank will be designed to dissipate the output of the discharge, or anode, supply: 1A at 300V. Therefore the load bank should be able to dissipate at least 300W. Using Ohm’s law, one ﬁnds that a resistor of size 300Ω is needed. A resistive load bank was designed to meet the requirements described in Table 5.9.

Table 5.9: PPU load bank requirements

No. Description Rationale CHTTEST1 Power dissipation shall be sustainable at The thruster is rated to output at least 300W or greater this value of discharge power CHTTEST2 Resistance must be within 15% of 300Ω The thruster can be simulated with a load bank of approximately this value CHTTEST3 Heat sink area must be 3000 cm2 of alu- Three resistors that each need 1000 cm2 minum at 3 mm thick of aluminum at 3 mm thick

Three 1000 kΩ chassis-mount resistors were put in parallel, resulting in a parallel resistance of 333Ω. According to the datasheet, each resistor is capable of sustaining 150W of dissipation at steady state when mounted to a 1000 cm2 heat sink that is 3 mm thick. An aluminum I-beam was found that provides 3900 cm2 of heat sink area, which exceeds the requirement. Mounting holes were drilled into the I-beam and the resistors were mounted to the I-beam and electrically connected in parallel with wires of sufficient current capacity. Wires of appropriate gauge and voltage rating were soldered to the chassis-mount resistors and connected in parallel. The resulting load bank is shown in Figure 5.25. An additional benefit of the configuration where three resistors are in parallel is that is allows one to increase the resistance of the load by removing resistors from the parallel circuit. This allows the load current to be decreased to one third of the max value, enabling testing at 100W rather than the full 300W. A low power configuration reduces the number of laboratory power supplies needed in parallel for testing the PPU, which makes testing easier. Chapter 5. Power processing unit for a cylindrical Hall thruster 65

Figure 5.25: Chassis-mount resistors ﬁxed to an aluminum I-beam to be used as a load bank

5.9 Future Work

Future work will be to test each voltage rail to verify that it is producing the correct voltage. Subse- quently, the microcontroller will be programmed and it’s ability to output a duty cycle in response to a changing analog input will be measured. If the microcontroller is able to output the correct duty cycle waveforms for the boost chopper and for the push-pull converter and the isolation circuitry is passing the boost chopper driving signal across isolation, then the push-pull converter will be powered on and thorough testing of the PPU on the load bank will begin. Software implementation of command and control requirements must be implemented on the microcontroller. Chapter 6

Hall thruster power processing unit control

6.1 Introduction

For the PPU to provide nominal and reliable power to the thruster it must be governed in some fashion. Controlling the low voltage rails is done in hardware using integrated circuits, but controlling the 300V and 100V outputs are challenging, particularly because the microcontroller’s feedback and control signals must be passed across galvanic isolation. This chapter will be concerned primarily with how the 300V and 100V rails are controlled.

6.1.1 Overview of basic control theory

A current-fed push-pull converter’s transfer function is shown in (6.1). Nprimary and Nsecondary are the number of turns of wire around the transformer on the primary and secondary sides, Vin is the input voltage, and D is the duty cycle of the switch (i.e. the fraction of time it is on divided by the period) [27].

Nsecondary 1 Vout = Vin (6.1) Nprimary 2(1 − D)

(6.1) suffices for calculating the output voltage in steady-state conditions as a function of D and Vin, but it does not provide sufficient information for determining how the system is to be controlled. To illustrate this, consider that the duty cycle is changing over time as described in (6.2). In this equation, there is a small ripple of amplitude d added to the constant component of the duty cycle D. A hat, also referred to as a circumflex (e.g.x ˆ), denotes a small variation in that quantity. Therefore,v ˆ is the small variation in output voltage and dˆ is the small variation in duty cycle. The frequency is denoted by ω. Phase delay is denoted by φ. It is the difference in phase between the change in output voltage in

vo response to a change in duty cycle. The ratio d is called the gain [33].

66 Chapter 6. Hall thruster power processing unit control 67

D d d(t) = D + dˆ(t) d(t) = D + |d| sin(ωt) (6.2)

vo(t) = Vo +v ˆ(t)

vo(t) = Vo + |b| sin(ωt + φ)

The importance of phase delay and gain to power converter design can be shown in Figure 6.1. In Case A on the left the phase delay between the change in duty cycle and the change in output voltage is zero and the gain is greater than one. This means that the output voltage increases substantially when the duty cycle increases, and there is a negligible delay in that relationship. In Case B on the right the phase delay is 180◦ but the gain is still greater than, so the output voltage increases substantially when the gain decreases. Case B is a dangerous mode of operation, because typically power converters are regulated by negative feedback, so the controller would now be operating in a positive feedback mode, which would cause large oscillations and would eventually cause the breakdown of some component of the converter [33].

Figure 6.1: Eﬀects of gain and phase on duty cycle and output voltage over time. Arb. units. [33]

These two quantities are functions of the frequency of the perturbation and can be graphed to produce Chapter 6. Hall thruster power processing unit control 68 a Bode plot, shown in Figure 6.2. We can now see the quantitative diﬀerence between Cases A and B from Figure 6.1. With this understanding of the importance of phase and gain and their importance to system stability, the feedback loop and the power stage can be modelled.

Figure 6.2: Sample Bode plot [33]

6.1.2 Overview of feedback loop stability

A power converter with a feedback circuit can be modelled as shown in Figure 6.3. The variation in output voltage is a linear combination of three quantities, as shown in (6.3). The three quantities are the ˆ variation in duty cycle, d, multiplied by a gain in output voltage with respect to duty cycle Gvd(s), the variation in input voltage,v ˆin, multiplied by the gain in output voltage with respect to input voltage,

Gvg, and the variation in the load current, ˆiload, multiplied by the output impedance Zout(s). The gain of the compensator is HC (s) and the gain of the pulse-width modulation circuit or software function is

GM [33].

ˆ vˆo(s) = Gvd(s)d + Gvg(s)ˆvin − Zout(s)ˆiload (6.3)

The transfer functions or gains Gvd, Gvg, Zout are described as below [33]: Chapter 6. Hall thruster power processing unit control 69

Figure 6.3: Block diagram of a converter with feedback [33]

vô Gvd(s) = : Wherev în = 0 and îload = 0 (6.4) dˆ

vô ˆ Gvg(s) = : Where din = 0 and îload = 0 (6.5) vîn

vô ˆ Zout(s) = − : Wherev în = 0 and d = 0 (6.6) îload Looking at Figure 6.3, a term called the loop gain T (s) can be defined. It is the product of all the gains along the loop. This is defined mathematically in (6.7) [33].

T (s) = Gvd(s)HC (s)GM (6.7)

The feedback loop can be closed and two transfer functions are produced: (6.8) shows the transfer function from input voltage to output voltage and (6.9) shows the transfer function from output current to output voltage. One insight from re-arranging the constituent equations in this way is that the output voltage variation is approximately inversely proportional to the loop gain [33].

vô Gvg(s) = : when îload = 0 andv ˆref = 0 (6.8) vîn 1 + T (s)

vô Gvg(s) = : when îload = 0 andv ˆref = 0 (6.9) vîn 1 + T (s) The higher the gain of the power converter, the better the regulation and bandwith, and the shorter the delay of the system in response to sudden changes in load. Provided that the gain of the converter crosses unity (0 dB) only once, then the system can be analyzed using Bode plots. This point is called the crossover frequency. Contributions at frequencies higher than this point are attenuated and contributions from lower frequencies are amplified. Loop gain decreases with increasing frequency and this is accompanied by phase lag, as shown in (6.2). The amount of phase lag is a linearly related to the slope of the gain curve. The Nyquist stability criterion is that the loop will be unstable if the additional phase lag exceeds 180◦ at the crossover frequency. The difference between 180◦ and the phase lag is referred to as phase margin. In practice, the phase lag at the crossover frequency should be Chapter 6. Hall thruster power processing unit control 70 significantly smaller than 180◦, otherwise the loop will be stable but the transient response will exhibit under-damped oscillations. At frequencies other than the crossover frequency, the phase lag may exceed 180◦. In addition to phase margin, there is also gain margin, which is the factor by which the gain is less than 0 dB at the frequency where the phase lag is 180◦. These two margins are illustrated in Figure 6.4 [34]. The shape of the gain curve, and by extension the phase curve, are determined by the topology (e.g. current-fed push-pull rather than a boost converter), the control method, and the compensation network. The last item is used to shape the loop gain to provide sufficient gain and phase margins so that the system exhibits good dynamic response, line and load regulation, and stability [33].

Figure 6.4: Illustration of crossover frequency and gain and phase margin [33]

6.2 Requirements

Practically, a phase margin of 45◦ and a gain margin of at least 10 dB is required for a stable closed-loop system. The microcontroller used for this application can only adjust the duty cycle that it outputs at a frequency of approximately 300 Hz, which limits the range of perturbations that can be controlled out of the system to those with frequencies lower than 100 Hz because of the Nyquist limit. Chapter 6. Hall thruster power processing unit control 71

The current-fed push-pull converter will be controlled in a closed-loop fashion, therefore its quality can be evaluated by these requirements. The boost chopper is operating in discontinuous mode, where the magnetic field in the inductor is completed depleted each cycle, which has a different and complex transfer functions compared to continuous mode operation. In addition, it is not necessary for this circuit to operate in a closed-loop fashion since the output is not intended to be smooth in the first place. Therefore, it will be designed for simple open loop control, with the circuit to be turned off if the RMS output exceeds a threshold to be determined after testing (e.g. for RMS voltages greater than 350V the boost chopper will be turned off). The feedback signal must be averaged so account for the pulsing nature of the anode voltage. The low voltage rails use internal hardware control that is built into each integrated circuit, so they do not have control requirements.

6.3 Design Methodology

6.3.1 Controlling the current-fed push-pull converter

Normally, control of a switch-mode power supply would be done in hardware, as software is slow in comparison, limiting the bandwidth of software based control. In Section 5.4.5 on page 50 it was shown that the current-fed push-pull converter in this power processing unit can be controlled using a microcontroller implementing software-based control. This requires that the crossover frequency occur at approximately 100 Hz, so that the contributions from frequencies higher than 100 Hz will be strongly attenuated. This will enable the implementation of a negative-feedback control algorithm. The microcontroller will take the voltage error and compute the adjustment that it should make to the duty cycle. The duty cycle is output by the microcontroller’s programmable counter array (PCA) at 200 kHz with the duty cycle adjusted at 100 Hz. This signal will be split with one signal being passed integrated circuit that delays one signal by half a period. These two logic-level signals are then fed to the power transistor drivers that drive the transistors so that one transistor is half a period behind another, which is necessary for the push-pull converter. As discussed previously and described in (6.7), in principle to produce a Bode plot that would allow a requirements check, one must be able to plot T (s), which is made up of three functions: Gvd(s), and

ﬁnally HC (s). However, there are several non-idealities that must be included in the loop gain T (s).

Both of them have a dependence on frequency. One non-ideality is optocoupler pole, denoted as Gopto(s).

Another non-ideality is the computation time of the microcontroller, denoted as Gdelay(s).

6.3.2 Boost chopper

This circuit can be controlled in a coarse manner. The pulsed output will be scaled down and smoothed before being passed to across galvanic isolation to the microcontroller, which will run a simple control routine that will turn oﬀ the boost chopper if the output voltage is too high. In the future, if com- puting power can be spared, negative feedback control algorithm such as that in Section 6.3.1 will be implemented. Chapter 6. Hall thruster power processing unit control 72

6.3.3 Low voltage rails

These rails, described in Table 5.4, will use internal hardware control that is built into each integrated circuit.

6.4 Design

6.4.1 Transfer function of output voltage variation with respect to duty cycle variation

The transfer function of output voltage variation with respect to duty cycle variation, Gvd(s), can be derived using small-signal analysis as well as other techniques. Two sources for the resulting equation were be found in the literature. The transfer functions from [27] and [29] were used to compute the transfer function for the particular values of input inductor L, output capacitor Co, output voltage Vo, and transformer turns ratio n. One representation of this transfer function for the current-fed push-pull converter, from [27], is shown in (6.10). A circuit diagram of the converter is shown in Figure 5.13 on page 46. The variation in the output voltage veout(s) and the variation in the duty cycle is de(s). The transfer function expresses the small signal response of the output voltage to small signal variations of the duty cycle. The results are plotted in Figure 6.5 and show that the two sources match closely.

veout(s) Gvd = de(s) −i Ls L + 1 (6.10) V 2n(1 − D)V = out out (1 − D) LC s2 L o + s + 1 4n2(1 − D)2 4n2(1 − D)2 Chapter 6. Hall thruster power processing unit control 73

Figure 6.5: Gvd transfer function for the current-fed push-pull converter in the Hall thruster power supply [33][29] .

6.4.2 Pulse-width modulation gain

This transfer function is not a function of frequency. It is simply the inverse of the triangle wave peak- to-peak voltage used in canonical pulse-width modulation (PWM) circuit, shown in Figure (6.6). In this application, the conversion of error signal to PWM is done in software, so the gain can be set arbitrarily. Chapter 6. Hall thruster power processing unit control 74

Figure 6.6: Boost converter with a feedback ampliﬁer [35] .

6.4.3 Optocoupler transfer function

An optocoupler, shown schematically in Figure 6.7 is used in isolated topologies to pass output voltage information from the secondary side of the transformer across to the primary side, where it is fed into the controller [33]. The transfer function for the optocoupler pole is shown in (6.11) [36]. The current transfer ratio is denoted as KCTR, the LED current-limiting resistor is RLED, and the transistor pull-up resistor Rpull−up. The capacitance of the collector base area is denoted as C. This capacitance is the cause of the optocoupler pole. Both of these quantities can be found in the datasheet of the optocoupler [36].

Rpull−upKCTR 1 Gopto(s) = (6.11) RLED 1 + sCRpull−up Chapter 6. Hall thruster power processing unit control 75

Figure 6.7: Schematic illustration of an optocoupler showing the pull-up resistor and LED resistor [36] .

6.4.4 Delay transfer function

Normally, switch-mode power supplies use hardware and not software control, so in most cases and literature sources the computation time is considered negligible for all but extremely high frequencies.

However, software control is used in this design, so this function Gdelay(s) must be considered and modelled. The transfer function of a time delay is shown in (6.12). T is the time delay measured in units that are consistent with s. That is to say that T is measured in seconds if s is measured in Hz. The maximum frequency of calculation is approximately 300 Hz, so this will be used for the value of T .

−sT Gdelay(s) = e (6.12)

As a consequence of this computation time, the phase lag becomes unmanageable past approximately 100 Hz, so that perturbations to the system at frequencies greater than this cannot be compensated.

6.4.5 Compensator transfer function

This transfer function is designed to shape the loop gain to provide gain and phase margins that meet requirements. There are several types of compensators but a type-I compensator, shown in Figure 6.8 provides the correct shape for the loop gain because it contains only an integrator [33]. The transfer function for a type-I compensator is shown in (6.13).

ωI 1 HC (s) = : where ωI = (6.13) s RI CF Chapter 6. Hall thruster power processing unit control 76

Figure 6.8: Type-I compensator with a sketch of its transfer function [33]

6.5 Results

The loop transfer function T (s) is plotted in Figure 6.9. Mathematically, it is deﬁned in (6.14).

T (s) = Gvd(s)HC (s)GM Gdelay(s)Gopto(s) (6.14)

The gain and phase margins are shown on the curve. The gain margin is 10.3 dB while the phase margin is 62.6 degrees. The system is closed-loop stable. Control will be implemented in software, so this plot indicates that closed loop control in software is an achievable goal with a controller that can cycle at approximately 25 Hz or faster, which is the crossover frequency. The eﬀects of the time delay on the phase are that the phase delay increases at frequencies higher than the crossover frequency. Chapter 6. Hall thruster power processing unit control 77

Figure 6.9: T(s) for the current-fed push-pull converter including computation time

6.6 Future work

With the loop transfer function quantiﬁed and shown to be closed loop stable, what that remains is to implement Proportional, Integral, Diﬀerential (PID) control to replicate the function of the feedback circuit shown in lower half of Figure 6.6. This will be accomplished by adjusting the duty cycle of a programmable counter array (PCA) on the microcontroller using a PID control algorithm. A programmable counter array will output a duty cycle of varying length but at a constant frequency that can be far higher than the frequency that the duty cycle can be adjusted at. For this application, the microcontroller will output a 200 kHz duty cycle with the duty cycle being adjusted at a frequency of 100 Hz. Chapter 7

Conclusion

This thesis has described the author’s contributions to the design, analysis, and implementation of three projects at the Space Flight Laboratory: the NORSAT-2 mission, the Vector Gravimeter for Asteroids (VEGA) accelerometer payload, and an engineering model power processing unit for a Cylindrical Hall thruster. The author’s contributions to the NORSAT-2 mission were performing unit tests for the spare components of all the spacecraft subsystems as well as designing and assembling the flatsat from said spares. The flatsat is an important article of ground support equipment that enables satellite operators to test new programs and operational modes on an exact duplicate of the NORSAT-2 satellite, which reduces risk to the mission. Furthermore, integration of the flatsat and testing of the subsystems before integration of the satellite allows one to locate and address problems before they can interfere with the mission. The NORSAT-2 satellite along with its companion NORSAT-1 were launched on the 14th of July, 2017. The author’s contributions to the Vector Gravimeter for Asteroids, an ultra-high-accuracy, three-axis, planetary gravimeter, were modifying the instrument computer board schematic, laying out the parts as a printed circuit board, developing and applying test software, and performing thermal acceptance testing of two instrument computer boards. The VEGA payload is not yet associated with a mission, but it remains an excellent candidate for an asteroid or moon prospecting mission, or a mission that requires extremely sensitive acceleration measurements, such as qualifying an electric propulsion system. Finally, the author designed, analyzed, and implemented an engineering model power processing unit for a Cylindrical Hall thruster. This engineering model is not expected to be suitable for flight, but it is an important step towards a flight model and raises the technical readiness level of the payload. One engineering model has been assembled and testing is ongoing. In addition, the author produced a load bank that allows for bench-top testing of the power processing unit at multiple levels of current. With this load bank, testing will not need to be conducted on the thruster inside a vacuum chamber, which will allow rapid development cycles and therefore reduce the cost of developing the propulsion system and its power system to higher technical readiness.

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