5 4 3 2 1 TMDSEVM6657 SCHEMATIC

MAJOR REVISION HISTORY : I2C ADDRESS TABLE :

D D PCB REV.SCH. REV. DESCRIPTION DATE REF DES DESCRIPTION 7 BIT ADDRESS

1.0 0.6 Initial Draft 03-FEB-2012 EEPROM1 DSP EEPROM 0x50, 0x51 1.1 Release for Alpha Boards 20-MAR-2012 U264 ETHERNET EEPROM 0x50 2.0 2.5 Release for Beta Boards 26-JUL-2012

2.9 Redundant pull-up and termination NU 28-NOV-2013 on EMU_TCK

C C

PCB LAYER STACK-UP DETAILS : PCB MECHANICAL DETAILS :

TOP 1.0 oz 1. PCB SIZE: 7.11" x 2.89" x 0.063" 3.6mils p.p L2_GND 1.0 oz 2. PCB MATERIAL: FR4_IT168G 4mils core 3. NUMBER OF LAYERS: 12 L3 0.5 oz 4. IMPEDANCE CONTROL: YES 4.8mils p.p L4_PWR 1.0 oz 5mils core L5 0.5 oz 4.4mils p.p L6_GND 1.0 oz

B 4mils core B 1.0 oz L7_GND NOTES, UNLESS OTHERWISE SPECIFIED : 4.4mils p.p L8 0.5 oz 5mils core 1.0 oz L9_PWR 1. RESISTANCE VALUES ARE IN OHMS. 4.8mils p.p L10 0.5 oz 2. CAPACITANCE VALUES ARE IN MICROFARADS. 4mils core 3. PARTS NOT INSTALLED ARE INDICATED WITH 'NU'. 1.0 oz L11_GND 4. SIGNAL NET NAMES WITH "#" SUFFIX, ARE ACTIVE LOW SIGNALS. 3.6mils p.p BOT 1.0 oz

Project A DISCLAIMER: THIS CIRCUIT DESIGN IS Designed for TI by eInfochips A TMDSEVM6657 PROVIDED AS REFERENCE ONLY, Copyright (C) 20xx Texas Instruments Incorporated. WITHOUT WARRANTY EXPRESSED OR Title IMPLIED. THE USER IS ENCOURAGED All rights reserved. TO PERFORM ALL DUE DILIGENCE WITH COVER PAGE RESPECT TO DESIGN AND ANALYSIS. Document Number Rev FOR COMMITTED PERFORMANCE AND Size FUNCTIONALITY OF THE xxxx DEVICE, C 16_00132_02 2.9 PLEASE REFER TO THE DEVICE DATA MANUAL. Date: Thursday, November 28, 2013 Sheet 1of 29 5 4 3 2 1 5 4 3 2 1

SCHEMATIC PAGE DESCRIPTION :

D D

01 : COVER PAGE 02 : TABLE OF CONTENTS 03 : SYSTEM BLOCK DIAGRAM 04 : PLACEMENT 05 : POWER CONSUMPTION 06 : POWER SEQUENCE 07 : POWER DISTRIBUTION 08 : CLOCK DIAGRAM 09 : FPGA INTERFACE CONTROL 10 : MANAGEMENT MAP 11 : AMC CONNECTOR 12 : MMC, HYPERLINK COMM

C 13 : DSP - SERDES PORTS C 14 : DSP - DDR3 15 : DDR3 & ECC 16 : DSP - EMIF & JTAG 17 : DSP - MISC 18 : DSP - CLOCK & SMART REFLEX 19 : CLOCK GENERATION 20 : USB - JTAG 21 : GIGABIT ETHERNET 22 : FPGA - POWER, RESET CTRL, McBSP 23 : FPGA - BOOT_MODE & SMART REFLEX 24 : DSP - POWER 1 25 : DSP - POWER 2 26 : SMART REFLEX & CORE VOLT

B 27 : POWER SUPPLY 1 B 28 : POWER SUPPLY 2 29 : REVISON HISTORY

Project A Designed for TI by eInfochips A TMDSEVM6657 Title TABLE OF CONTENTS

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 2of 29

5 4 3 2 1 5 4 3 2 1

BLOCK DIAGRAM

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title BLOCK DIAGRAM

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 3of 29

5 4 3 2 1 5 4 3 2 1

PLACEMENT

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title PLACEMENT

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 4of 29

5 4 3 2 1 5 4 3 2 1

POWER CONSUMPTION

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title POWER CONSUMPTION

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 5of 29

5 4 3 2 1 5 4 3 2 1 POWER SEQUENCE

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title POWER SEQUENCE

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 6of 29

5 4 3 2 1 5 4 3 2 1

POWER DISTRIBUTION

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title POWER DISTRIBUTION

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 7of 29

5 4 3 2 1 5 4 3 2 1

CLOCK DIAGRAM

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title CLOCK DIAGRAM

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 8of 29

5 4 3 2 1 5 4 3 2 1

FPGA INTERFACE CONTROL DIAGRAM

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title CLOCK DIAGRAM

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 9of 29

5 4 3 2 1 5 4 3 2 1

MANAGEMENT MAP

D D

C C

B B

Project A Designed for TI by eInfochips A TMDSEVM6657 Title MANAGEMENT MAP

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 10of 29

5 4 3 2 1 5 4 3 2 1

AMC CONNECTOR FAN CONNECTOR

VCC12 Front Panel and ESD Strip

WB_3V_2.0mm 3 NU 2 1 R158NU 0E

D D FAN1 C526 NU R157NU 0E R936 10M 1uF R937 10M

TRIP1 TRIP1 TRIP2 TRIP3 4 1 2 3

VCC3V3_AUX ESD1

AMC-ESD-B AMC_JTAG_TDI R445 10K

AMC_JTAG_TDO R446 10K

VCC12_AMC AMC1 AMC_JTAG_TMS R447 10K GF-AMC-B VCC3V3_MP_AMC 1 170 AMC_JTAG_TCK R449 10K 2 GND_1 GND_56 169 OUT AMC_JTAG_TDI [20] MMC_PS_N1 3 PWR_12V_1 TDI 168 AMC_JTAG_RST# R448 10K PS1 TDO IN AMC_JTAG_TDO [20] 4 167 [20] 5 MP TRST 166 OUT AMC_JTAG_RST# [12] MMC_GA0 IN GA0 TMS OUT AMC_JTAG_TMS [20] Management Power 6 165 [20] 7 RSRVD6 TCK 164 OUT AMC_JTAG_TCK VCC3V3_AUX 8 GND_2 GND_55 163 9 RSRVD8 Tx20+ 162 VCC3V3_AUX 10 PWR_12V_2 Tx20- 161 VCC1V8 11 GND_3 GND_54 160 R484 0E DSP_SCL_AMC R339 [21] AMC_SGMII_TXP IN 12 Tx0+ Rx20+ 159 R487 0E DSP_SDA_AMC [21] AMC_SGMII_TXN IN 100K 13 Tx0- Rx20- 158 C355 14 GND_4 GND_53 157 [21] AMC_SGMII_RXP OUT 15 Rx0+ Tx19+ 156 100nF C411 [21] AMC_SGMII_RXN OUT 16 Rx0- Tx19- 155 U245 R175 R90 17 GND_5 GND_52 154 PCA9306DCUR 100nF [12] MMC_GA1 IN 18 GA1 Rx19+ 153 2 7 PWR_12V_3 Rx19- VREF1 VREF2 C 19 152 8 4.7K 4.7K C 20 GND_6 GND_51 151 EN 21 Tx1+ Tx18+ 150 DSP_SCL 3 6 DSP_SCL_AMC [12,17] DSP_SCL IN 22 Tx1- Tx18- 149 DSP_SDA 4 SCL1 SCL2 5 DSP_SDA_AMC [12,17] DSP_SDA BI 23 GND_7 GND_50 148 SDA1 SDA2 24 Rx1+ Rx18+ 147 1 25 Rx1- Rx18- 146 GND GND_8 GND_49 [12] 26 145 MMC_GA2 IN 27 GA2 Tx17+ 144 28 PWR_12V_4 Tx17- 143 29 GND_9 GND_48 142 30 Tx2+ Rx17+ 141 31 Tx2- Rx17- 140 32 GND_10 GND_47 139 [22] 33 Rx2+ TCLKD+ 138 OUT TCLKD_P [22] 34 Rx2- TCLKD- 137 OUT TCLKD_N 35 GND_11 GND_46 136 Tx3+ TCLKC+ OUT TCLKC_P [22] 36 135 [22] 37 Tx3- TCLKC- 134 OUT TCLKC_N 38 GND_12 GND_45 133 VCC1V8_AUX 39 Rx3+ Tx15+ 132 VCC1V8 VCC3V3_AUX 40 Rx3- Tx15- 131 41 GND_13 GND_44 130 R160NU 0E DSP_SDA_AMC [12] MMC_ENABLE_N OUT 42 ENABLE Rx15+ 129 R161NU 0E DSP_SCL_AMC R1958 U13 C1128 43 PWR_12V_5 Rx15- 128 C1160 SN74AVC4T245PWR GND_14 GND_43 100nF [13] C301 100nF 44 127 AMCC_P4_PCIe_TX1P IN 45 Tx4+ Tx14+ 126 4.7K 100nF 16 1 [13] C302 100nF AMCC_P4_PCIe_TX1N IN 46 Tx4- Tx14- 125 VCCB VCCA 47 GND_15 GND_42 124 15 2 [13] AMCC_P4_PCIe_RX1P OUT 48 Rx4+ Rx14+ 123 14 1OE 1DIR 3 [13] [22] AMCC_P4_PCIe_RX1N OUT 49 Rx4- Rx14- 122 McBSP_AMC_EN# IN 2OE 2DIR C326 100nF 50 GND_16 GND_41 121 AMC_P12_McBSP_TX0 13 4 [13] AMCC_P5_PCIe_TX2P IN IN DSP_McBSP0_TX [12,13] C369 100nF 51 Tx5+ Tx13+ 120 AMC_P12_McBSP_TX1 12 1B1 1A1 5 [13] AMCC_P5_PCIe_TX2N IN IN DSP_McBSP1_TX [12,13] 52 Tx5- Tx13- 119 AMC_P12_McBSP_RX0 11 1B2 1A2 6 OUT DSP_McBSP0_RX [12,13] 53 GND_17 GND_40 118 AMC_P12_McBSP_RX1 10 2B1 2A1 7 [13] AMCC_P5_PCIe_RX2P OUT Rx5+ Rx13+ 2B2 2A2 OUT DSP_McBSP1_RX [12,13] [13] 54 117 AMCC_P5_PCIe_RX2N OUT 55 Rx5- Rx13- 116 GND_18 GND_39 [12] 56 115 9 8 B SMB_SCL_IPMBL OUT 57 SCL_L Tx12+ 114 GND2 GND1 B PWR_12V_6 Tx12- 58 113 OE# = 0 59 GND_19 GND_38 112 Tx6+ Rx12+ DIR = 0 --> B to A 60 111 DIR = 1 --> A to B 61 Tx6- Rx12- 110 62 GND_20 GND_37 109 [13] 63 Rx6+ Tx11+ 108 IN AMCC_P11_SRIO4_TXP [13] 64 Rx6- Tx11- 107 IN AMCC_P11_SRIO4_TXN 65 GND_21 GND_36 106 Tx7+ Rx11+ OUT AMCC_P11_SRIO4_RXP [13] 66 105 [13] 67 Tx7- Rx11- 104 OUT AMCC_P11_SRIO4_RXN 68 GND_22 GND_35 103 Rx7+ Tx10+ IN AMCC_P10_SRIO3_TXP [13] 69 102 [13] 70 Rx7- Tx10- 101 IN AMCC_P10_SRIO3_TXN GND_23 GND_34 [12] SMB_SDA_IPMBL BI 71 100 [13] 72 SDA_L Rx10+ 99 OUT AMCC_P10_SRIO3_RXP [13] 73 PWR_12V_7 Rx10- 98 OUT AMCC_P10_SRIO3_RXN GND_24 GND_33 [22] 74 97 [13] TCLKA_P OUT 75 TCLKA+ Tx9+ 96 IN AMCC_P9_SRIO2_TXP [22] [13] TCLKA_N OUT 76 TCLKA- Tx9- 95 IN AMCC_P9_SRIO2_TXN 77 GND_25 GND_32 94 [19] [13] TCLKB_P OUT 78 TCLKB+ Rx9+ 93 OUT AMCC_P9_SRIO2_RXP [19] [13] TCLKB_N OUT 79 TCLKB- Rx9- 92 OUT AMCC_P9_SRIO2_RXN 80 GND_26 GND_31 91 [18] PCIE_REF_CLK_P OUT FCLKA+ Tx8+ IN AMCC_P8_SRIO1_TXP [13] [18] 81 90 [13] PCIE_REF_CLK_N OUT 82 FCLKA- Tx8- 89 IN AMCC_P8_SRIO1_TXN MMC_PS_N1 D3 B340A-13-F MMC_PS_N0 83 GND_27 GND_30 88 PS0 Rx8+ OUT AMCC_P8_SRIO1_RXP [13] 84 87 [13] 85 PWR_12V_8 Rx8- 86 OUT AMCC_P8_SRIO1_RXN GND_28 GND_29

Project A Designed for TI by eInfochips A TMDSEVM6657 Title AMC CONNECTOR

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 11of 29

5 4 3 2 1 5 4 3 2 1

MMC INTERFACE IPASS+HD for HyperLink

MSP430 Power VCC3V3_MP

Hyperlink1 D IPASS+HD_36H D R10 VCC3V3_MP VCC3V3_MP_AMC VCC3V3_AUX R11 iPass Plus HD 1x1 Assy NU D1 C1 [13] HyperLink_RXPMCLK OUT IN HyperLink_TXPMDAT [13] D10 PMEG4005AEA 10K D2 sideband5 sideband4 C2 [13] HyperLink_RXFLDAT IN IN HyperLink_TXPMCLK [13] 1 2 MMC_SBWTDIO 10K D3 sideband6 sideband2 C3 D4 GND_D3 GND_C3 C4

3 [13] [13] HyperLink_TXP0 IN D5 Txp0 Txp1 C5 IN HyperLink_TXN3 [13] HyperLink_TXN0 IN IN HyperLink_TXP3 [13] D9 PMEG4005AEA Q1 D D6 Txn0 Txn1 C6 2N7002 GND_D6 GND_C6 1 2 G [13] D7 C7 [13] 1 HyperLink_TXP1 IN D8 Txp2 Txp3 C8 IN HyperLink_TXP2 MMC_ENABLE_N [11] [13] [13] S IN HyperLink_TXN1 IN D9 Txn2 Txn3 C9 IN HyperLink_TXN2 C524 GND_D9 GND_C9 100nF 2 R16 [13] B1 A1 [13] HyperLink_RXPMDAT OUT B2 sideband3 sideband7 A2 OUT HyperLink_TXFLCLK [13] [13] 10K HyperLink_TXFLDAT OUT B3 sideband1 sideband0 A3 IN HyperLink_RXFLCLK GND_B3 GND_A3 [13] B4 A4 [13] HyperLink_RXP0 OUT B5 Rxp0 Rxp1 A5 OUT HyperLink_RXP1 [13] [13] HyperLink_RXN0 OUT B6 Rxn0 Rxn1 A6 OUT HyperLink_RXN1 B7 GND_B6 GND_A6 A7 [13] [13] HyperLink_RXP2 OUT B8 Rxp2 Rxp3 A8 OUT HyperLink_RXN3 [13] [13] HyperLink_RXN2 OUT B9 Rxn2 Rxn3 A9 OUT HyperLink_RXP3 GND_B9 GND_A9 NPTH1 NPTH2

H1 H2

SpyBiWire

SBW_MMC1 VCC3V3_MP VCC3V3_MP W_4V_2.54mm

C 4 MMC_SBWTCK B1 120_100MHz C 3 MMC_SBWTDIO MMC1 2 MSP430F5435IPNR C6 C1 C2 C3 C4 1 C371 72 C10 73 PJ.0/TDO 11 100nF 100nF 100nF 100nF 100nF 100nF 1000pF 74 PJ.1/TDI/TCLK AVCC DEBUG HEADER 75 PJ.2/TMS 16 PJ.3/TCK DVCC1 51 71 DVCC2 31 76 TEST/SBWTCK DVCC3 67 RST#/NMI/SBWTDIO DVCC4 21 MMC_GAPU C5 22pF MMC_XTAL1 13 P1.4/TA0.3 P7.0/XIN R13 R14 R15 1 Y1 TEST_PH1 14 SFM-140-L2-S-D-LC 60 P7.1/XOUT 3.3K 3.3K 3.3K H2 P8.0/TA0.0 61 [16] 2 1 62 P8.1/TA0.1 17 DSP_EMIFA00 IN 4 3 ABS10-32.768KHZ-T [16] BI DSP_SDA [11,17] 63 P8.2/TA0.2 P1.0/TA0CLK/ACLK DSP_EMIFA01 IN 6 5 2 P8.3/TA0.3 [16] DSP_EMIFA02 IN IN DSP_SCL [11,17] C8 22pF MMC_XTAL2 64 18 [11] [16] 8 7 BI DSP_EMIFD0 [16] 65 P8.4/TA0.4 P1.1/TA0.0 19 OUT MMC_GA0 DSP_EMIFA03 IN 10 9 P8.5/TA1.0 P1.2/TA0.1 OUT MMC_GA1 [11] [16] DSP_EMIFA04 IN BI DSP_EMIFD1 [16] 66 20 [11] [16] 12 11 BI DSP_EMIFD2 [16] 58 P8.6/TA1.1 P1.3/TA0.2 34 OUT MMC_GA2 DSP_EMIFA05 IN 14 13 [16] BI DSP_EMIFD3 [16] 59 P7.2/TB0OUTH/SVMOUT P2.7/ADC12CLK/DMAE0 TP7 TP8 TP9 DSP_EMIFA06 IN 16 15 R18 R19 R20 [16] BI DSP_EMIFD4 [16] 5 P7.3/TA1.2 DSP_EMIFA07 IN 18 17 P7.4/A12 [16] DSP_EMIFA08 IN BI DSP_EMIFD5 [16] 6 23 NU NU NU 20 19 BI P7.5/A13 P1.6/SMCLK 0E 0E 0E [16] DSP_EMIFA09 IN DSP_EMIFD6 [16] 7 33 [16] 22 21 BI DSP_EMIFD7 [16] 8 P7.6/A14 P2.6/ACLK 25 DSP_EMIFA10 IN 24 23 [16] BI DSP_EMIFD8 [16] 77 P7.7/A15 P2.0/TA1CLK/MCLK DSP_EMIFA11 IN 26 25 [16] DSP_EMIFA12 IN BI DSP_EMIFD9 [16] 78 P6.0/A0 40 R7NU 0E 28 27 OUT UART_FT_RX [17,20] [16] DSP_EMIFA13 IN BI DSP_EMIFD10 [16] 79 P6.1/A1 P3.5/UCA0RXD/UCA0SOMI 39 R6NU 0E 30 29 P6.2/A2 P3.4/UCA0TXD/UCA0SIMO IN UART_FT_TX [17,20] [16] DSP_EMIFA14 IN BI DSP_EMIFD11 [16] 80 The NU resistors on these connections to the [16] 32 31 BI DSP_EMIFD12 [16] 1 P6.3/A3 MSP430 are for debug use only and will be DSP_EMIFA15 IN 34 33 [16] BI DSP_EMIFD13 [16] 2 P6.4/A4 used only with the shunts removed from pins DSP_EMIFA16 IN 36 35 [16] BI DSP_EMIFD14 [16] 3 P6.5/A5 42 1 and 2 of CN7 DSP_EMIFA17 IN 38 37 [16] DSP_EMIFA18 IN BI DSP_EMIFD15 [16] 4 P6.6/A6 P3.7/UCB1SIMO/UCB1SDA 41 MMC_SCK 40 39 R963NU 0E [23] [16] [16] 53 P6.7/A7 P3.6/UCB1STE/UCA1CLK 38 IN MMC_SPI_SCK DSP_EMIFA19 IN 42 41 IN DSP_EMIFCE1Z [16] DSP_EMIFA20 IN IN DSP_EMIFCE2Z [16] B VCC3V3_MP 52 P4.7/TB0CLK/SMCLK P3.3/UCB0CLK/UCA0STE 35 SPI Interface for 44 43 B [16] DSP_EMIFA21 IN IN DSP_EMIFBE0Z [16] 48 P4.6/TB0.6 P3.0/UCB0STE/UCA0CLK 57 MMC_MISO R960NU 0E FPGA debugging. 46 45 OUT MMC_SPI_MISO [23] [16] DSP_EMIFA22 IN IN DSP_EMIFBE1Z [16] 47 P4.5/TB0.5 P5.7/UCA1RXD/UCA1SOMI 56 MMC_MOSI R961NU 0E 48 47 IN MMC_SPI_MOSI [23] [16] DSP_EMIFA23 IN IN DSP_EMIFOEZ [16] TP17 46 P4.4/TB0.4 P5.6/UCA1TXD/UCA1SIMO 55 MMC_STE R962NU 0E R1177 33E 50 49 IN MMC_SPI_STE [23] [13,22] DSP_McBSP0_RXCLK BI IN DSP_EMIFWEZ [16] R4 R3 45 P4.3/TB0.3 P5.5/UCB1CLK/UCA1STE 54 R1179 33E 52 51 [13,22] DSP_McBSP0_TXCLK BI IN DSP_EMIFRNW [16] 44 P4.2/TB0.2 P5.4/UCB1SOMI/UCB1SCL 70 VCC3V3_MP R1183 33E 54 53 [13,22] DSP_McBSP0_SLCLK OUT OUT DSP_EMIFWAIT1 [16] MMC_P43 43 P4.1/TB0.1 P5.3/XT2OUT 69 56 55 [13,22] DSP_McBSP0_FSR BI OUT DSP_TIMI0 [17,23] 330E 330E (Red LED) P4.0/TB0.0 P5.2/XT2IN 10 58 57 [13,22] DSP_McBSP0_FST BI IN DSP_TIMO0 [17,23] 1 2 MMC_LED1 22 P5.1/A9/VREF-/VEREF- 9 R2 R1 60 59 [11,13] DSP_McBSP0_RX OUT OUT DSP_TIMI1 [17,23] D1 LED MMC_LED2 24 P1.5/TA0.4 P5.0/A8/VREF+/VEREF+ 62 61 R [11,13] DSP_McBSP0_TX IN IN DSP_TIMO1 [17,23] P1.7 R1188 33E 64 63 R399 10E [13,22] DSP_McBSP1_RXCLK BI OUT DSP_SSPMISO [17,22] 1 2 49 33K 33K R1189 33E 66 65 [13,22] DSP_McBSP1_TXCLK BI IN DSP_SSPMOSI [17,22] D2 LED VCORE 37 R1186 33E 68 67 B IN SMB_SCL_IPMBL [11] [13,22] DSP_McBSP1_SLCLK OUT IN DSP_SSPCS1 [17,22] (Blue LED) 15 P3.2/UCB0SOMI/UCB0SCL 36 70 69 DVSS1 P3.1/UCB0SIMO/UCB0SDA BI SMB_SDA_IPMBL [11] [13,22] DSP_McBSP1_FSR BI IN PH_SSPCK [17] C7 50 32 [22] [13,22] BI 72 71 [17] 30 DVSS2 P2.5 29 OUT MMC_DETECT# DSP_McBSP1_FST 74 73 IN DSP_UART1_TX [22] [11,13] [17] 0.47uF 68 DVSS3 P2.4/RTCCLK 28 IN MMC_RSTSTAT# DSP_McBSP1_RX OUT 76 75 OUT DSP_UART1_RX DVSS4 P2.3/TA1.2 IN MMC_BOOTCOMP [22] [11,13] DSP_McBSP1_TX IN IN DSP_UART1_RTS [17] 12 27 [22] [17,23] BI 78 77 [17] AVSS P2.2/TA1.1 26 OUT MMC_POR_AMC# DSP_GPIO_14 80 79 OUT DSP_UART1_CTS P2.1/TA1.0 OUT MMC_WR_AMC# [22] [17,23] DSP_GPIO_15 BI H1

Project A Designed for TI by eInfochips A TMDSEVM6657 Title MMC, HYPERLINK & 80 CONN

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 12of 29

5 4 3 2 1 5 4 3 2 1

SRIO

DSP1P TMS320C6657

C164 100nF AE8 AC8 [11] AMCC_P8_SRIO1_RXP IN OUT AMCC_P8_SRIO1_TXP [11] C167 100nF AE9 RIORXP0 RIOTXP0 AC9 [11] AMCC_P8_SRIO1_RXN IN RIORXN0 RIOTXN0 OUT AMCC_P8_SRIO1_TXN [11] C165 100nF AD7 AB8 [11] AMCC_P9_SRIO2_RXP IN OUT AMCC_P9_SRIO2_TXP [11] C166 100nF AD8 RIORXP1 RIOTXP1 AB7 D [11] AMCC_P9_SRIO2_RXN IN RIORXN1 RIOTXN1 OUT AMCC_P9_SRIO2_TXN [11] D C168 100nF AE6 AC6 [11] AMCC_P10_SRIO3_RXP IN OUT AMCC_P10_SRIO3_TXP [11] C169 100nF AE5 RIORXP2 RIOTXP2 AC5 [11] AMCC_P10_SRIO3_RXN IN RIORXN2 RIOTXN2 OUT AMCC_P10_SRIO3_TXN [11] C170 100nF AD5 AB5 [11] AMCC_P11_SRIO4_RXP IN OUT AMCC_P11_SRIO4_TXP [11] C171 100nF AD4 RIORXP3 RIOTXP3 AB4 [11] AMCC_P11_SRIO4_RXN IN RIORXN3 RIOTXN3 OUT AMCC_P11_SRIO4_TXN [11]

Place ALL SERDES DC-blocking caps on top layer adjacent to the DSP's RX pins so that there are no additional vias

SGMII VOLTAGE LEVEL TRANSLATOR

VCC3V3_AUX VCC1V8 VCC2V5 VCC1V8 DSP1O TMS320C6657 R316 C327 C401 AC3 R957 R85 U244 R83 R82 OUT DSP_SGMII_TXP [21] 100nF SGMII0TXP AC2 100nF PCA9306DCUR 100K OUT DSP_SGMII_TXN [21] C172 100nF AE3 SGMII0TXN 2 7 [21] DSP_SGMII_RXP IN C173 100nF AE2 SGMII0RXP 4.7K 4.7K VREF1 VREF2 8 10K 10K [21] DSP_SGMII_RXN IN SGMII0RXN NU NU EN AB16 DSP_MDIO DSP_MDC 3 6 OUT ETH_MDC [21] MDIO AA16 DSP_MDC DSP_MDIO 4 SCL1 SCL2 5 MDCLK SDA1 SDA2 BI ETH_MDIO [21] 1 GND C C

PCIE McBSP

DSP1T TMS320C6657

DSP1Q AA21 AD23 [12,22] DSP_McBSP0_RXCLK BI CLKR0 CLKR1 BI DSP_McBSP1_RXCLK [12,22] TMS320C6657 [12,22] BI Y20 AE24 BI DSP_McBSP1_TXCLK [12,22] DSP_McBSP0_TXCLK AC23 CLKX0 CLKX1 AC21 [12,22] DSP_McBSP0_SLCLK IN IN DSP_McBSP1_SLCLK [12,22] C305 100nF AE11 AC11 CLKS0 CLKS1 [11] AMCC_P4_PCIe_RX1P IN PCIERXP0 PCIETXP0 OUT AMCC_P4_PCIe_TX1P [11] [11] C306 100nF AE12 AC12 [11] [12,22] BI AD24 AD22 BI DSP_McBSP1_FSR [12,22] AMCC_P4_PCIe_RX1N IN PCIERXN0 PCIETXN0 OUT AMCC_P4_PCIe_TX1N DSP_McBSP0_FSR AA20 FSR0 FSR1 AE23 [12,22] DSP_McBSP0_FST BI FSX0 FSX1 BI DSP_McBSP1_FST [12,22] [11] C307 100nF AD11 AB10 [11] AMCC_P5_PCIe_RX2P IN AD10 PCIERXP1 PCIETXP1 AB11 OUT AMCC_P5_PCIe_TX2P AB21 AD21 [11] C308 100nF [11] [11,12] [11,12] AMCC_P5_PCIe_RX2N IN PCIERXN1 PCIETXN1 OUT AMCC_P5_PCIe_TX2N DSP_McBSP0_RX IN AC22 DR0 DR1 AE22 IN DSP_McBSP1_RX [11,12] DSP_McBSP0_TX OUT DX0 DX1 OUT DSP_McBSP1_TX [11,12] R2958 R2959

4.7K 4.7K

B B

HYPERLINK

DSP1R TMS320C6657 The HyperLink routes must have a max of 2 vias C505 100nF N24 N22 [12] HyperLink_RXP0 IN OUT HyperLink_TXP0 [12] and no via stubs (Outer layer routing recommended) C470 100nF P24 MCMRXP0 MCMTXP0 P22 [12] HyperLink_RXN0 IN MCMRXN0 MCMTXN0 OUT HyperLink_TXN0 [12] C512 100nF N25 M21 [12] HyperLink_RXP1 IN OUT HyperLink_TXP1 [12] C511 100nF M25 MCMRXP1 MCMTXP1 N21 [12] HyperLink_RXN1 IN MCMRXN1 MCMTXN1 OUT HyperLink_TXN1 [12] C14 100nF K25 L22 [12] HyperLink_RXP2 IN OUT HyperLink_TXP2 [12] C12 100nF J25 MCMRXP2 MCMTXP2 K22 [12] HyperLink_RXN2 IN MCMRXN2 MCMTXN2 OUT HyperLink_TXN2 [12] C20 100nF L24 K21 TP5 TP6 [12] HyperLink_RXP3 IN OUT HyperLink_TXP3 [12] C19 100nF K24 MCMRXP3 MCMTXP3 J21 [12] HyperLink_RXN3 IN MCMRXN3 MCMTXN3 OUT HyperLink_TXN3 [12] G25 HL_REF_CLKP MCMREFCLKOUTP F25 HL_REF_CLKN MCMREFCLKOUTN R456 22E B24 E25 [12] HyperLink_RXFLCLK OUT MCMRXFLCLK MCMTXFLCLK IN HyperLink_TXFLCLK [12] Project A [12] C24 D25 [12] Designed for TI by eInfochips A HyperLink_RXFLDAT OUT E24 MCMRXFLDAT MCMTXFLDAT F24 IN HyperLink_TXFLDAT [12] R457 22E [12] TMDSEVM6657 HyperLink_RXPMCLK IN D24 MCMRXPMCLK MCMTXPMCLK G24 OUT HyperLink_TXPMCLK [12] HyperLink_RXPMDAT IN MCMRXPMDAT MCMTXPMDAT OUT HyperLink_TXPMDAT [12] Title DSP SERDES PORTS

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 13of 29

5 4 3 2 1 5 4 3 2 1

DDR3 INTERFACE

DSP1K TMS320C6657 OUT DSP0_DDR3_EA[15:0] [15] D A14 D16 DSP0_DDR3_EA0 VCC1V5 D [15] DSP0_DDR3_ECKP_0 OUT B14 DDRCLKOUTP0 DDRA00 A19 DSP0_DDR3_EA1 [15] DSP0_DDR3_ECKN_0 OUT A21 DDRCLKOUTN0 DDRA01 E16 DSP0_DDR3_EA2 DSP0_DDR3_ECKP_0 R37 39.2E C31 100nF B21 DDRCLKOUTP1 DDRA02 E15 DSP0_DDR3_EA3 DDRCLKOUTN1 DDRA03 B18 DSP0_DDR3_EA4 DSP0_DDR3_ECKN_0 R38 39.2E A16 DDRA04 A17 DSP0_DDR3_EA5 [15] DSP0_DDR3_ECKE_0 OUT A20 DDRCKE0 DDRA05 C16 DSP0_DDR3_EA6 B15 DDRCKE1 DDRA06 A18 DSP0_DDR3_EA7 [15] DSP0_DDR3_ECS_0# OUT C14 DDRCE0z DDRA07 D20 DSP0_DDR3_EA8 DDRCE1z DDRA08 E20 DSP0_DDR3_EA9 D14 DDRA09 E19 DSP0_DDR3_EA10 VCC0V75 [15] DSP0_DDR3_ECAS# OUT A15 DDRCASz DDRA10 B20 DSP0_DDR3_EA11 [15] DSP0_DDR3_ERAS# OUT E13 DDRRASz DDRA11 D18 DSP0_DDR3_EA12 [15] DSP0_DDR3_EWE# OUT DDRWEz DDRA12 C20 DSP0_DDR3_EA13 DDRA13 E18 DSP0_DDR3_EA14 C18 DDRA14 E17 DSP0_DDR3_EA15 DSP0_DDR3_EA0 [15] R41 39.2E C33 10nF DSP0_DDR3_EBA_0 OUT D17 DDRBA0 DDRA15 [15] DSP0_DDR3_EBA_1 OUT BI DSP0_DDR3_EDQ[7:0] [15] B19 DDRBA1 A9 DSP0_DDR3_EDQ0 DSP0_DDR3_EA1 R42 39.2E C34 100nF [15] DSP0_DDR3_EBA_2 OUT DDRBA2 DDRD00 C9 DSP0_DDR3_EDQ1 A8 DDRD01 D9 DSP0_DDR3_EDQ2 DSP0_DDR3_EA2 R43 39.2E C35 10nF [15] DSP0_DDR3_EDM_0 OUT E7 DDRDQM0 DDRD02 B9 DSP0_DDR3_EDQ3 [15] DSP0_DDR3_EDM_1 OUT F5 DDRDQM1 DDRD03 E9 DSP0_DDR3_EDQ4 DSP0_DDR3_EA3 R44 39.2E C36 100nF [15] DSP0_DDR3_EDM_2 OUT E1 DDRDQM2 DDRD04 E10 DSP0_DDR3_EDQ5 [15] DSP0_DDR3_EDM_3 OUT C12 DDRDQM3 DDRD05 A11 DSP0_DDR3_EDQ6 DSP0_DDR3_EA4 R45 39.2E C37 10nF [15] DSP0_DDR3_EDM_4 OUT DDRDQM8 DDRD06 B11 DSP0_DDR3_EDQ7 BI DSP0_DDR3_EDQ[15:8] [15] D10 DDRD07 E6 DSP0_DDR3_EDQ8 DSP0_DDR3_EA5 R46 39.2E C38 100nF [15] DSP0_DDR3_EDQSP_0 OUT C10 DDRDQS0P DDRD08 E8 DSP0_DDR3_EDQ9 [15] DSP0_DDR3_EDQSN_0 OUT B7 DDRDQS0N DDRD09 A6 DSP0_DDR3_EDQ10 DSP0_DDR3_EA6 R47 39.2E [15] DSP0_DDR3_EDQSP_1 OUT A7 DDRDQS1P DDRD10 A5 DSP0_DDR3_EDQ11 [15] DSP0_DDR3_EDQSN_1 OUT B4 DDRDQS1N DDRD11 D6 DSP0_DDR3_EDQ12 DSP0_DDR3_EA7 R48 39.2E [15] DSP0_DDR3_EDQSP_2 OUT A4 DDRDQS2P DDRD12 C7 DSP0_DDR3_EDQ13 [15] DSP0_DDR3_EDQSN_2 OUT A2 DDRDQS2N DDRD13 D7 DSP0_DDR3_EDQ14 DSP0_DDR3_EA8 R49 39.2E [15] DSP0_DDR3_EDQSP_3 OUT B2 DDRDQS3P DDRD14 B8 DSP0_DDR3_EDQ15 [15] DSP0_DDR3_EDQSN_3 OUT BI DSP0_DDR3_EDQ[23:16] [15] B13 DDRDQS3N DDRD15 E5 DSP0_DDR3_EDQ16 DSP0_DDR3_EA9 R50 39.2E [15] DSP0_DDR3_EDQSP_4 OUT A13 DDRDQS8P DDRD16 B3 DSP0_DDR3_EDQ17 [15] DSP0_DDR3_EDQSN_4 OUT DDRDQS8N DDRD17 F4 DSP0_DDR3_EDQ18 DSP0_DDR3_EA10 R51 39.2E [15] DSP0_DDR3_ECC[3:0] BI DSP0_DDR3_ECC0 D11 DDRD18 E4 DSP0_DDR3_EDQ19 DDRCB00 DDRD19 C DSP0_DDR3_ECC1 B12 A3 DSP0_DDR3_EDQ20 DSP0_DDR3_EA11 R52 39.2E C DSP0_DDR3_ECC2 C11 DDRCB01 DDRD20 B5 DSP0_DDR3_EDQ21 DSP0_DDR3_ECC3 A12 DDRCB02 DDRD21 C5 DSP0_DDR3_EDQ22 DSP0_DDR3_EA12 R53 39.2E DDRCB03 DDRD22 D5 DSP0_DDR3_EDQ23 BI DSP0_DDR3_EDQ[31:24] [15] DDRD23 E2 DSP0_DDR3_EDQ24 DSP0_DDR3_EA13 R54 39.2E B16 DDRD24 F2 DSP0_DDR3_EDQ25 [15] DSP0_DDR3_EMRESETN OUT DDRRESETz DDRD25 B1 DSP0_DDR3_EDQ26 DSP0_DDR3_EA14 R55 39.2E E14 DDRD26 C1 DSP0_DDR3_EDQ27 [15] DSP0_DDR3_EODT_0 OUT D12 DDRODT0 DDRD27 D1 DSP0_DDR3_EDQ28 DSP0_DDR3_EA15 R86 39.2E DDRODT1 DDRD28 D3 DSP0_DDR3_EDQ29 U1_DDRSLRATE0 C22 DDRD29 C3 DSP0_DDR3_EDQ30 U1_DDRSLRATE1 D22 DDRSLRATE0 DDRD30 E3 DSP0_DDR3_EDQ31 DDRSLRATE1 DDRD31 DSP_VREFSSTL E12 F15 VREFSSTL PTV15

C114 R58 10V 1% 100nF 45.3E Place these resistors at the end of the trace.

VCC0V75

DSP0_DDR3_EBA_0 R56 39.2E C39 10nF VCC1V8 VCC1V8 VCC1V5 DSP0_DDR3_EBA_1 R57 39.2E C40 100nF

B B DSP0_DDR3_EBA_2 R59 39.2E C41 10nF R69 R70 NU 1% 1% DSP0_DDR3_EODT_0 R60 39.2E C42 100nF C60 R77 10V 1% 2K 2K DSP0_DDR3_EWE# R61 39.2E C43 10nF 100nF 1K DSP0_DDR3_ERAS# R62 39.2E C44 100nF U1_DDRSLRATE0 U1_DDRSLRATE1 OUT DSP_VREFSSTL [15,28] DSP0_DDR3_ECAS# R63 39.2E

R78 R71 R72 DSP0_DDR3_ECKE_0 R64 39.2E C59 1% 1% NU 10V 1% DSP0_DDR3_ECS_0# R65 39.2E 100nF 1K 20 mil trace width 2K 2K

VCC1V5

DDR3 Slew-Rate Setting (DDRSLRATE[1:0]): 1% DSP0_DDR3_EMRESETN R66 4.7K 00 Fastest 01 Fast 10 Slow 11 Slowest

Project A Designed for TI by eInfochips A TMDSEVM6657 Title DSP DDR3

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 14of 29

5 4 3 2 1 5 4 3 2 1

DDR3 MEMORY INTERFACE

VCC1V5 U5 VCC1V5 MT41J128M16HA-125 U16 [14,15] DSP0_DDR3_EA[15:0] IN DSP0_DDR3_EA0 N3 B2 MT41J128M16HA-125 [14,15] DSP0_DDR3_EA[15:0] IN DSP0_DDR3_EA1 P7 A0 VDD_1 D9 DSP0_DDR3_EA0 N3 B2 DSP0_DDR3_EA2 P3 A1 VDD_2 G7 C65 C66 C67 C68 C69 C70 DSP0_DDR3_EA1 P7 A0 VDD_1 D9 DSP0_DDR3_EA3 N2 A2 VDD_3 K2 100nF 100nF 100nF 100nF 100nF 22uF DSP0_DDR3_EA2 P3 A1 VDD_2 G7 C88 C85 C86 C90 C89 C87 DSP0_DDR3_EA4 P8 A3 VDD_4 K8 DSP0_DDR3_EA3 N2 A2 VDD_3 K2 100nF 100nF 100nF 100nF 100nF 22uF DSP0_DDR3_EA5 P2 A4 VDD_5 N1 DSP0_DDR3_EA4 P8 A3 VDD_4 K8 DSP0_DDR3_EA6 R8 A5 VDD_6 N9 DSP0_DDR3_EA5 P2 A4 VDD_5 N1 D DSP0_DDR3_EA7 R2 A6 VDD_7 R1 DSP0_DDR3_EA6 R8 A5 VDD_6 N9 D DSP0_DDR3_EA8 T8 A7 VDD_8 R9 DSP0_DDR3_EA7 R2 A6 VDD_7 R1 DSP0_DDR3_EA9 R3 A8 VDD_9 A1 DSP0_DDR3_EA8 T8 A7 VDD_8 R9 DSP0_DDR3_EA10 L7 A9 VDDQ_1 A8 DSP0_DDR3_EA9 R3 A8 VDD_9 A1 DSP0_DDR3_EA11 R7 A10/AP VDDQ_2 C1 DSP0_DDR3_EA10 L7 A9 VDDQ_1 A8 DSP0_DDR3_EA12 N7 A11 VDDQ_3 C9 DSP0_DDR3_EA11 R7 A10/AP VDDQ_2 C1 DSP0_DDR3_EA13 T3 A12/BC VDDQ_4 D2 C163 100nF DSP0_DDR3_EA12 N7 A11 VDDQ_3 C9 A13 VDDQ_5 E9 DSP0_DDR3_EA13 T3 A12/BC VDDQ_4 D2 C328 100nF DSP0_DDR3_EBA_0 M2 VDDQ_6 F1 A13 VDDQ_5 E9 [14,15] DSP0_DDR3_EBA_0 IN DSP0_DDR3_EBA_1 N8 BA0 VDDQ_7 H2 DSP0_DDR3_EBA_0 M2 VDDQ_6 F1 [14,15] DSP0_DDR3_EBA_1 IN [14,15] DSP0_DDR3_EBA_0 IN DSP0_DDR3_EBA_2 M3 BA1 VDDQ_8 H9 DSP0_DDR3_EBA_1 N8 BA0 VDDQ_7 H2 [14,15] DSP0_DDR3_EBA_2 IN [14,15] DSP0_DDR3_EBA_1 IN BA2 VDDQ_9 DSP0_DDR3_EBA_2 M3 BA1 VDDQ_8 H9 20 mil trace width [14,15] DSP0_DDR3_EBA_2 IN DSP0_DDR3_EWE# L3 M8 DSP_VREFSSTL BA2 VDDQ_9 [14,15] DSP0_DDR3_EWE# IN IN DSP_VREFSSTL [14,28] 20 mil trace width DSP0_DDR3_ECAS# K3 WE VREFCA H1 DSP0_DDR3_EWE# L3 M8 DSP_VREFSSTL [14,15] DSP0_DDR3_ECAS# IN [14,15] DSP0_DDR3_EWE# IN DSP0_DDR3_ERAS# J3 CAS VREFDQ DSP0_DDR3_ECAS# K3 WE VREFCA H1 [14,15] DSP0_DDR3_ERAS# IN BI DSP0_DDR3_EDQ[7:0] [14] [14,15] DSP0_DDR3_ECAS# IN DSP0_DDR3_ECS_0# L2 RAS E3 DSP0_DDR3_EDQ0 DSP0_DDR3_ERAS# J3 CAS VREFDQ [14,15] DSP0_DDR3_ECS_0# IN [14,15] DSP0_DDR3_ERAS# IN BI DSP0_DDR3_EDQ[23:16] [14] CS DQL0 F7 DSP0_DDR3_EDQ1 DSP0_DDR3_ECS_0# L2 RAS E3 DSP0_DDR3_EDQ16 [14,15] DSP0_DDR3_ECS_0# IN DSP0_DDR3_EDQSP_0 F3 DQL1 F2 DSP0_DDR3_EDQ2 CS DQL0 F7 DSP0_DDR3_EDQ17 [14] DSP0_DDR3_EDQSP_0 IN DSP0_DDR3_EDQSN_0 G3 DQSL DQL2 F8 DSP0_DDR3_EDQ3 DSP0_DDR3_EDQSP_2 F3 DQL1 F2 DSP0_DDR3_EDQ18 [14] DSP0_DDR3_EDQSN_0 IN [14] DSP0_DDR3_EDQSP_2 IN DSP0_DDR3_EDQSP_1 C7 DQSL DQL3 H3 DSP0_DDR3_EDQ4 DSP0_DDR3_EDQSN_2 G3 DQSL DQL2 F8 DSP0_DDR3_EDQ19 [14] DSP0_DDR3_EDQSP_1 IN [14] DSP0_DDR3_EDQSN_2 IN DSP0_DDR3_EDQSN_1 B7 DQSU DQL4 H8 DSP0_DDR3_EDQ5 DSP0_DDR3_EDQSP_3 C7 DQSL DQL3 H3 DSP0_DDR3_EDQ20 [14] DSP0_DDR3_EDQSN_1 IN [14] DSP0_DDR3_EDQSP_3 IN DQSU DQL5 G2 DSP0_DDR3_EDQ6 DSP0_DDR3_EDQSN_3 B7 DQSU DQL4 H8 DSP0_DDR3_EDQ21 [14] DSP0_DDR3_EDQSN_3 IN DSP0_DDR3_EDM_0 E7 DQL6 H7 DSP0_DDR3_EDQ7 DQSU DQL5 G2 DSP0_DDR3_EDQ22 [14] DSP0_DDR3_EDM_0 IN BI DSP0_DDR3_EDQ[15:8] [14] DSP0_DDR3_EDM_1 D3 DML DQL7 D7 DSP0_DDR3_EDQ8 DSP0_DDR3_EDM_2 E7 DQL6 H7 DSP0_DDR3_EDQ23 [14] DSP0_DDR3_EDM_1 IN [14] DSP0_DDR3_EDM_2 IN BI DSP0_DDR3_EDQ[31:24] [14] DMU DQU0 C3 DSP0_DDR3_EDQ9 DSP0_DDR3_EDM_3 D3 DML DQL7 D7 DSP0_DDR3_EDQ24 [14] DSP0_DDR3_EDM_3 IN DSP0_DDR3_ECKP_0 J7 DQU1 C8 DSP0_DDR3_EDQ10 DMU DQU0 C3 DSP0_DDR3_EDQ25 [14,15] DSP0_DDR3_ECKP_0 IN DSP0_DDR3_ECKN_0 K7 CK DQU2 C2 DSP0_DDR3_EDQ11 DSP0_DDR3_ECKP_0 J7 DQU1 C8 DSP0_DDR3_EDQ26 [14,15] DSP0_DDR3_ECKN_0 IN [14,15] DSP0_DDR3_ECKP_0 IN DSP0_DDR3_ECKE_0 K9 CK DQU3 A7 DSP0_DDR3_EDQ12 DSP0_DDR3_ECKN_0 K7 CK DQU2 C2 DSP0_DDR3_EDQ27 [14,15] DSP0_DDR3_ECKE_0 IN [14,15] DSP0_DDR3_ECKN_0 IN CKE DQU4 A2 DSP0_DDR3_EDQ13 DSP0_DDR3_ECKE_0 K9 CK DQU3 A7 DSP0_DDR3_EDQ28 [14,15] DSP0_DDR3_ECKE_0 IN DSP0_DDR3_EODT_0 K1 DQU5 B8 DSP0_DDR3_EDQ14 CKE DQU4 A2 DSP0_DDR3_EDQ29 [14,15] DSP0_DDR3_EODT_0 IN ODT DQU6 A3 DSP0_DDR3_EDQ15 DSP0_DDR3_EODT_0 K1 DQU5 B8 DSP0_DDR3_EDQ30 [14,15] DSP0_DDR3_EODT_0 IN DSP0_DDR3_EMRESETN T2 DQU7 ODT DQU6 A3 DSP0_DDR3_EDQ31 [14,15] DSP0_DDR3_EMRESETN IN RESET A9 DSP0_DDR3_EMRESETN T2 DQU7 [14,15] DSP0_DDR3_EMRESETN IN R76 240E L8 VSS_1 B3 RESET A9 ZQ VSS_2 E1 R132 240E L8 VSS_1 B3 VSS_3 ZQ VSS_2 1% G8 E1 J1 VSS_4 J2 VSS_3 G8 NC_1 VSS_5 1% VSS_4 C J9 J8 J1 J2 C L1 NC_2 VSS_6 M1 J9 NC_1 VSS_5 J8 L9 NC_3 VSS_7 M9 L1 NC_2 VSS_6 M1 [14,15] DSP0_DDR3_EA[15:0] IN DSP0_DDR3_EA15 M7 NC_4 VSS_8 P1 L9 NC_3 VSS_7 M9 [14,15] DSP0_DDR3_EA[15:0] IN DSP0_DDR3_EA14 T7 NC_5 VSS_9 P9 DSP0_DDR3_EA15 M7 NC_4 VSS_8 P1 NC_7 VSS_10 T1 DSP0_DDR3_EA14 T7 NC_5 VSS_9 P9 VSS_11 T9 Supported Memories (96 FBGA) : NC_7 VSS_10 T1 VSS_12 B1 VSS_11 T9 VSSQ_1 B9 VSS_12 B1 VSSQ_2 D1 VSSQ_1 B9 VSSQ_3 D8 Mfgr 512MB (256MB x 2) 1024MB (512MB x 2) VSSQ_2 D1 VSSQ_4 E2 VSSQ_3 D8 VSSQ_5 E8 VSSQ_4 E2 VSSQ_6 F9 VSSQ_5 E8 VSSQ_7 G1 Micron MT41J128M16HA-125 MT41J256M16RE-125 VSSQ_6 F9 VSSQ_8 G9 VSSQ_7 G1 VSSQ_9 VSSQ_8 G9 VSSQ_9

VCC1V5 DDR3 ECC INTERFACE U6 NU MT41J128M16HA-125 DSP0_DDR3_EA0 N3 B2 DSP0_DDR3_EA1 P7 A0 VDD_1 D9 DSP0_DDR3_EA2 P3 A1 VDD_2 G7 C107 C108 C109 C110 C111 C112 DSP0_DDR3_EA3 N2 A2 VDD_3 K2 100nF 100nF 100nF 100nF 100nF 22uF - Data bits can be swapped within the byte DSP0_DDR3_EA4 P8 A3 VDD_4 K8 lane to ease routing. DSP0_DDR3_EA5 P2 A4 VDD_5 N1 A5 VDD_6 DSP0_DDR3_EA6 R8 N9 - Address/Command/Control/Clock routing DSP0_DDR3_EA7 R2 A6 VDD_7 R1 DSP0_DDR3_EA8 T8 A7 VDD_8 R9 must be Fly-By in byte order ECC, 0, 1, 2, 3. DSP0_DDR3_EA9 R3 A8 VDD_9 A1 B DSP0_DDR3_EA10 L7 A9 VDDQ_1 A8 B DSP0_DDR3_EA11 R7 A10/AP VDDQ_2 C1 DSP0_DDR3_EA12 N7 A11 VDDQ_3 C9 DSP0_DDR3_EA13 T3 A12/BC VDDQ_4 D2 C113 100nF A13 VDDQ_5 E9 DSP0_DDR3_EBA_0 M2 VDDQ_6 F1 DSP0_DDR3_EBA_1 N8 BA0 VDDQ_7 H2 DSP0_DDR3_EBA_2 M3 BA1 VDDQ_8 H9 BA2 VDDQ_9 20 mil trace width DSP0_DDR3_EWE# L3 M8 DSP_VREFSSTL DSP0_DDR3_ECAS# K3 WE VREFCA H1 DSP0_DDR3_ERAS# J3 CAS VREFDQ [14] DSP0_DDR3_EDQSP_4 IN BI DSP0_DDR3_ECC[3:0] [14] DSP0_DDR3_ECS_0# L2 RAS E3 DSP0_DDR3_ECC0 [14] DSP0_DDR3_EDQSN_4 IN CS DQL0 F7 DSP0_DDR3_ECC1 DSP0_DDR3_EDQSP_4 F3 DQL1 F2 DSP0_DDR3_ECC2 VCC1V5 DSP0_DDR3_EDQSN_4 G3 DQSL DQL2 F8 DSP0_DDR3_ECC3 R390 4.7K C7 DQSL DQL3 H3 R1160 4.7K Supported ECC Chip (96 FBGA) : R389 4.7K B7 DQSU DQL4 H8 R1361 4.7K DQSU DQL5 G2 R1484 4.7K DSP0_DDR3_EDM_4 E7 DQL6 H7 R1487 4.7K [14] DSP0_DDR3_EDM_4 IN Mfgr 256MB 512MB R387 4.7K D3 DML DQL7 D7 R348 4.7K DMU DQU0 C3 R353 4.7K DSP0_DDR3_ECKP_0 J7 DQU1 C8 R379 4.7K DSP0_DDR3_ECKN_0 K7 CK DQU2 C2 R382 4.7K DSP0_DDR3_ECKE_0 K9 CK DQU3 A7 R380 4.7K Micron MT41J128M16HA-125 MT41J256M16RE-125 CKE DQU4 A2 R381 4.7K DSP0_DDR3_EODT_0 K1 DQU5 B8 R388 4.7K ODT DQU6 A3 R383 4.7K DSP0_DDR3_EMRESETN T2 DQU7 RESET A9 R87 240E L8 VSS_1 B3 ZQ VSS_2 E1 VSS_3 1% G8 J1 VSS_4 J2 J9 NC_1 VSS_5 J8 L1 NC_2 VSS_6 M1 L9 NC_3 VSS_7 M9 NC_4 VSS_8 Project A DSP0_DDR3_EA15 M7 P1 Designed for TI by eInfochips A DSP0_DDR3_EA14 T7 NC_5 VSS_9 P9 TMDSEVM6657 NC_7 VSS_10 T1 VSS_11 T9 VSS_12 B1 Title VSSQ_1 B9 VSSQ_2 D1 VSSQ_3 D8 DDR3 & ECC VSSQ_4 E2 VSSQ_5 E8 VSSQ_6 F9 Document Number Rev VSSQ_7 G1 Size VSSQ_8 G9 VSSQ_9 C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 15of 29

5 4 3 2 1 5 4 3 2 1

C6657 - EMIF NAND FLASH

NAND1 VCC1V8 DSP1N MT29F1G08ABCHC TMS320C6657 DSP_EMIFD0 H4 J6 DSP_EMIFD0 U4 K1 DSP_EMIFD1 J4 IO0 VCC1 H8 [12] DSP_EMIFD0 BI OUT DSP_EMIFA00 [12] DSP_EMIFD1 U5 EMIFD00/UPP_D0 UPP_XD0/EMIFA00 M3 DSP_EMIFD2 K4 IO1 VCC2 C519 C159 C158 [12] DSP_EMIFD1 BI OUT DSP_EMIFA01 [12] DSP_EMIFD2 V1 EMIFD01/UPP_D1 UPP_XD1/EMIFA01 L2 DSP_EMIFD3 K5 IO2 100nF 100nF 10uF [12] DSP_EMIFD2 BI OUT DSP_EMIFA02 [12] DSP_EMIFD3 V2 EMIFD02/UPP_D2 UPP_XD2/EMIFA02 P5 DSP_EMIFD4 K6 IO3 [12] DSP_EMIFD3 BI OUT DSP_EMIFA03 [12] D DSP_EMIFD4 V3 EMIFD03/UPP_D3 UPP_XD3/EMIFA03 L1 DSP_EMIFD5 J7 IO4 D6 D [12] DSP_EMIFD4 BI OUT DSP_EMIFA04 [12] DSP_EMIFD5 V4 EMIFD04/UPP_D4 UPP_XD4/EMIFA04 P4 DSP_EMIFD6 K7 IO5 NC1 D7 [12] DSP_EMIFD5 BI OUT DSP_EMIFA05 [12] DSP_EMIFD6 W1 EMIFD05/UPP_D5 UPP_XD5/EMIFA05 M2 DSP_EMIFD7 J8 IO6 NC2 D8 [12] DSP_EMIFD6 BI OUT DSP_EMIFA06 [12] DSP_EMIFD7 V5 EMIFD06/UPP_D6 UPP_XD6/EMIFA06 M1 IO7 NC3 E3 [12] DSP_EMIFD7 BI OUT DSP_EMIFA07 [12] DSP_EMIFD8 W2 EMIFD07/UPP_D7 UPP_XD7/EMIFA07 N2 NC4 E4 [12] DSP_EMIFD8 BI OUT DSP_EMIFA08 [12] DSP_EMIFD9 Y1 EMIFD08/UPP_D8 UPP_XD8/EMIFA08 P3 DSP_EMIFCE0Z C6 NC5 E5 [12] DSP_EMIFD9 BI OUT DSP_EMIFA09 [12] DSP_EMIFD10 W4 EMIFD09/UPP_D9 UPP_XD9/EMIFA09 N1 DSP_EMIFA11 C4 CE NC6 E6 [12] DSP_EMIFD10 BI OUT DSP_EMIFA10 [12] DSP_EMIFD11 Y2 EMIFD10/UPP_D10 UPP_XD10/EMIFA10 P2 DSP_EMIFA12 D5 ALE NC7 E7 [12] DSP_EMIFD11 BI OUT DSP_EMIFA11 [12] DSP_EMIFD12 W5 EMIFD11/UPP_D11 UPP_XD11/EMIFA11 P1 DSP_EMIFOEZ D4 CLE NC8 E8 [12] DSP_EMIFD12 BI OUT DSP_EMIFA12 [12] DSP_EMIFD13 AA1 EMIFD12/UPP_D12 UPP_XD12/EMIFA12 R5 DSP_EMIFWEZ C7 RE NC9 F3 [12] DSP_EMIFD13 BI OUT DSP_EMIFA13 [12] DSP_EMIFD14 AB1 EMIFD13/UPP_D13 UPP_XD13/EMIFA13 R3 WE NC10 F4 [12] DSP_EMIFD14 BI OUT DSP_EMIFA14 [12] DSP_EMIFD15 AA2 EMIFD14/UPP_D14 UPP_XD14/EMIFA14 R4 A1 NC11 F5 [12] DSP_EMIFD15 BI EMIFD15/UPP_D15 UPP_XD15/EMIFA15 OUT DSP_EMIFA15 [12] DU1 NC12 R2 [12] A2 F6 UPP_CH0_CLK/EMIFA16 R1 OUT DSP_EMIFA16 A9 DU2 NC13 F8 UPP_CH0_START/EMIFA17 OUT DSP_EMIFA17 [12] DU3 NC14 T4 [12] A10 G6 UPP_CH0_ENABLE/EMIFA18 T1 OUT DSP_EMIFA18 B1 DU4 NC15 G7 [12] UPP_CH0_WAIT/EMIFA19 T5 OUT DSP_EMIFA19 B9 DU5 NC16 G8 UPP_CH1_CLK/EMIFA20 OUT DSP_EMIFA20 [12] DU6 NC17 U1 [12] B10 G3 UPP_CH1_START/EMIFA21 U2 OUT DSP_EMIFA21 L1 DU7 NC18 H3 UPP_CH1_ENABL/EMIFA22 OUT DSP_EMIFA22 [12] DU8 NC19 U3 [12] L2 H5 UPP_CH1_WAIT/EMIFA23 OUT DSP_EMIFA23 L9 DU9 NC20 H6 L10 DU10 NC21 H7 VCC1V8 K5 R236 22E DSP_EMIFCE0Z M1 DU11 NC22 J3 EMIFCE0z G1 R248 22E DSP_EMIFCE1Z M2 DU12 NC23 J5 VCC1V8 EMIFCE1z OUT DSP_EMIFCE1Z [12] DU13 NC24 J2 R249 22E DSP_EMIFCE2Z [12] M9 G4 EMIFCE2z M5 OUT DSP_EMIFCE2Z M10 DU14 NC25 D3 R183 EMIFCE3z DU15 NC26 F7 NC27 1K G5 R134 J1 DSP_EMIFBE0Z NC28 OUT DSP_EMIFBE0Z [12] 1K EMIFBE0z L3 DSP_EMIFBE1Z C5 OUT DSP_EMIFBE1Z [12] DSP_EMIFWAIT0 N5 EMIFBE1z K3 VSS1 C8 DSP_EMIFWAIT0 DSP_EMIFWAIT1 M4 EMIFWAIT0 K4 DSP_EMIFWEZ K8 VSS2 R/B C3 [12] DSP_EMIFWAIT1 IN OUT DSP_EMIFWEZ [12] IN NAND_WP# [22] EMIFWAIT1/UPP_2XTXCLK EMIFWEz L4 DSP_EMIFOEZ VSS3 WP EMIFOEz OUT DSP_EMIFOEZ [12] L5 DSP_EMIFRNW R135 EMIFRnW OUT DSP_EMIFRNW [12] 4.7K

C C

C6657 - JTAG & EMU TI-60 Header

VCC3V3_AUX

R903 EMU1 BB_30x2V_S1.27mm

4.7K H2 PTH EXT_EMU_DET0 A1 B1 D1 C1 [20] EXT_EMU_DET0 OUT A2 A1 C1 C2 R282 10E DSP_EMU_18 A3 C3 EMU_TRST#_R R288 10E EMU_TRST# OUT EMU_TRST# [20] A4 C4 R278 10E DSP_EMU_16 A5 C5 R277 10E DSP_EMU_15 A6 C6 R275 10E DSP_EMU_13 DSP1I NU A7 C7 R274 10E DSP_EMU_11 TMS320C6657 VCC1V8 R904 10K A8 C8 EMU_RTCK A9 C9 R281 10E DSP_EMU_10 V24 DSP_EMU_00 BI DSP_EMU_00 [20] A10 C10 R272 10E DSP_EMU_08 EMU00 V25 DSP_EMU_01 A11 C11 DSP_EMU_06 BI DSP_EMU_01 [20] R273 10E EMU01 W25 DSP_EMU_02 R290 A12 C12 R269 10E DSP_EMU_04 EMU02 W23 DSP_EMU_03 4.7K A13 C13 R267 10E DSP_EMU_03 EMU03 W24 DSP_EMU_04 A14 C14 EMU_01_R EMU_EMU_01 R286 10E BI EMU_EMU_01 [20] EMU04 Y25 DSP_EMU_05 TRGRSTZ A15 C15 [22] TRGRSTZ OUT B DSP_TRST# AB19 EMU05 Y24 DSP_EMU_06 B [20] DSP_TRST# IN DSP_TMS AE18 TRSTz EMU06 Y23 DSP_EMU_07 B1 D1 [20] DSP_TMS IN DSP_TDI AE17 TMS EMU07 W22 DSP_EMU_08 EMU_TMS R295 10E EMU_TMS_R B2 D2 VCC1V8 VCC1V8 [20] DSP_TDI IN [20] EMU_TMS OUT DSP_TCK AD17 TDI EMU08 Y22 DSP_EMU_09 DSP_EMU_17 R279 10E B3 D3 [20] DSP_TCK IN DSP_TDO AD19 TCK EMU09 AA24 DSP_EMU_10 EMU_TDI R294 10E EMU_TDI_R B4 D4 [20] DSP_TDO OUT [20] EMU_TDI OUT TDO EMU10 AA25 DSP_EMU_11 VCC1V8 DSP_EMU_14 R280 10E B5 D5 R1119 EMU11 AB25 DSP_EMU_12 DSP_EMU_12 R276 10E B6 D6 C1526 EMU12 AC25 DSP_EMU_13 EMU_TDO R293 10E EMU_TDO_R B7 D7 U268 100nF [20] EMU_TDO IN EMU13 AA23 DSP_EMU_14 R658 100E B8 D8 4.7K SN74AUC1G32DCKR EMU14 AB22 DSP_EMU_15 DSP_EMU_09 R271 10E B9 D9 EMU_TCK 1 5 EMU15 AD25 DSP_EMU_16 DSP_EMU_07 R270 10E B10 D10 A VCC EMU16 AC24 DSP_EMU_17 DSP_EMU_05 R268 10E B11 D11 2 OR 4 R377 33E EMU_RTCK EMU17 Y21 DSP_EMU_18 EMU_TCK R292 33E EMU_TCK_R B12 D12 R1120 B Y EMU18 DSP_EMU_02 R266 10E B13 D13 3 GND [20] EMU_EMU_00 BI EMU_EMU_00 R287 10E EMU_00_R B14 PTH D14 B15 D15 100E

C1528 VCC1V8 8.2pF VCC1V8 H1

C1527 U269 100nF SN74AUC1G32DCKR 1 5 A VCC

2 OR 4 R378 33E VCC1V8 B Y OUT EMU_TCK_BUF [20] R896 3 R893 R895 R897 GND 4.7K 4.7K 4.7K 4.7K NU R901 R902 EMU_TMS_R

4.7K 4.7K EMU_TDI_R EMU_00_R EMU_TDO_R Project A EMU_01_R Designed for TI by eInfochips A EMU_TCK_R TMDSEVM6657 C555 47pF EMU_TRST#_R NU Title

R905 R67 DSP EMIF & JTAG 4.7K 49.9E 1% NU Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 16of 29

5 4 3 2 1 5 4 3 2 1

1Mb I2C EEPROM I2C, TIMER[1:0], SPI 32Mb SPI NOR Flash VCC1V8 VCC1V8 VCC1V8 VCC1V8 R1960 R1961 C304 R180 R964 VCC1V8 100nF DSP1M 4.7K 4.7K C303 R162 VCC1V8 TMS320C6657 100nF 4.7K 4.7K EEPROM1 DSP_SCL AA17 AA12 R337 10E DSP_SSPCS0 4.7K U260 R427 R428 R429 AT24C1024BN-SH-T R4000 [11,12] DSP_SCL OUT DSP_SDA AA18 SCL GPIO28/SPISCS0 AA14 DSP_SSPCS1 N25Q032A11ESE40F NU NU NU 8 6 DSP_SCL [11,12] DSP_SDA BI OUT DSP_SSPCS1 [12,22] SDA GPIO29/SPISCS1 AA13 R340 10E DSP_SSPCK 8 VCC SCL 5 DSP_SDA AD20 SPICLK AB14 DSP_SSPMISO NOR_HD# 7 VCC 0E 0E 0E SDA 4.7K D [12,23] DSP_TIMI0 IN IN DSP_SSPMISO [12,22] D AE21 TIMI0/GPIO16 GPIO30/SPIDIN AB13 R363 10E DSP_SSPMOSI DSP_SSPCS0 1 HOLD/DQ3 1 [12,23] DSP_TIMI1 IN OUT DSP_SSPMOSI [12,22] R341 10E AC19 TIMI1/GPIO17 GPIO31/SPIDOUT NOR_SSPCK 6 S 2 NC 7 [12,23] DSP_TIMO0 OUT IN EEPROM_WP [22] R347 10E AE20 TIMO0/GPIO18 DSP_SSPMOSI 5 SCK 3 A1 WP 4 [12,23] DSP_TIMO1 OUT TIMO1/GPIO19 AB17 DSP_UARTRTS_V1P8 DSP_SSPMISO R398 10E 2 DQ0 R164 A2 GND GPIO23/UARTRTS AC17 DSP_UARTCTS_V1P8 3 DQ1 NU R165 R167 R1227 [22] NOR_WP# IN R185 R186 GPIO22/UARTCTS AA15 DSP_UARTTXD_V1P8 4 W/Vpp/DQ2 0E 0E NU 4.7K 4.7K GPIO21/UARTTXD AB15 DSP_UARTRXD_V1P8 R166 R163 VSS 0E GPIO20/UARTRXD 4.7K

4.7K 4.7K AD15 [12] Read Address: 1010 0001 (0x50), 1010 0011 (0x51) GPIO27/UARTRTS1 AE16 OUT DSP_UART1_RTS [12] Write Address: 1010 0000 (0x50), 010 0010 (0x51) GPIO26/UARTCTS1 AC15 IN DSP_UART1_CTS [12] GPIO25/UARTTXD1 AC14 OUT DSP_UART1_TX GPIO24/UARTRXD1 IN DSP_UART1_RX [12] R1962 R1963 R1964 R1965

4.7K 4.7K 4.7K 4.7K

B21 VCC1V8 2200pF 1 3 U255 SN74ALVC125PWR 1 14 DSP_SSPCK 2 1OE VCC 13 NOR_SSPCK R369 33E 3 1A 4OE 12 4 1Y 4A 11 2 5 2OE 4Y 10 GPIO R368 33E 6 2A 3OE 9 DSP_SSPCK [12] PH_SSPCK OUT 7 2Y 3A 8 R202 33E OUT FPGA_SSPCK [22] DSP1L GND 3Y TMS320C6657 VCC1V8

[23] DSP_GPIO_00 BI T25 R25 GPIO00/LENDIAN DSP_GPIO_01 [23] DSP_GPIO_01 BI R458 4.7K R23 GPIO01/BOOTMODE00 DSP_GPIO_02 R459 4.7K [23] DSP_GPIO_02 BI GPIO02/BOOTMODE01 C [23] DSP_GPIO_03 BI U25 DSP_GPIO_03 R460 4.7K C T23 GPIO03/BOOTMODE02 DSP_GPIO_04 R461 4.7K [23] DSP_GPIO_04 BI GPIO04/BOOTMODE03 [23] DSP_GPIO_05 BI U24 DSP_GPIO_05 R462 4.7K T22 GPIO05/BOOTMODE04 DSP_GPIO_06 [23] DSP_GPIO_06 BI R463 4.7K R21 GPIO06/BOOTMODE05 DSP_GPIO_07 R464 4.7K [23] DSP_GPIO_07 BI GPIO07/BOOTMODE06 [23] DSP_GPIO_08 BI U22 DSP_GPIO_08 R465 4.7K U23 GPIO08/BOOTMODE07 DSP_GPIO_09 R466 4.7K [23] DSP_GPIO_09 BI GPIO09/BOOTMODE08 [23] DSP_GPIO_10 BI V23 DSP_GPIO_10 R467 4.7K U21 GPIO10/BOOTMODE09 DSP_GPIO_11 UART to RS232 [23] DSP_GPIO_11 BI R468 4.7K T21 GPIO11/BOOTMODE10 DSP_GPIO_12 R469 4.7K [23] DSP_GPIO_12 BI GPIO12/BOOTMODE11 [23] DSP_GPIO_13 BI V22 DSP_GPIO_13 R470 4.7K R952 10E DSP_GPIO_R_14 W21 GPIO13/BOOTMODE12 DSP_GPIO_R_14 R471 4.7K [12,23] DSP_GPIO_14 BI GPIO14/PCIESSMODE0 [12,23] DSP_GPIO_15 BI R953 10E DSP_GPIO_R_15 V21 DSP_GPIO_R_15 R472 4.7K COM_SEL1 GPIO15/PCIESSMODE1 DSP_GPIO_00 R455 4.7K VCC3V3_AUX UART_FT_TX 1 2 UART_FT_RX [12,20] UART_FT_TX OUT IN UART_FT_RX [12,20] DSP_UART0_TX 3 4 DSP_UART0_RX VCC1V8 UART_MAX_TX 5 6 UART_MAX_RX

TSM-103-01-S-DV

C1367 C1368 U24 100nF JP-UART(1-3) & (2-4) : UART over USB Connector (Default) SN74AVC4T245PWR JP-UART(3-5) & (4-6) : UART over 3-Pin Header J5 100nF 16 1 VCCB VCCA 15 2 14 1OE 1DIR 3 TP134 Reset Control 2OE 2DIR DSP_UARTCTS_V1P8 13 4 DSP_UART0_CTS TP135 DSP_UARTRXD_V1P8 12 1B1 1A1 5 DSP_UART0_RX DSP_UARTRTS_V1P8 11 1B2 1A2 6 DSP_UART0_RTS DSP1J DSP_UARTTXD_V1P8 10 2B1 2A1 7 DSP_UART0_TX TMS320C6657 2B2 2A2

DSP_PORZ Y18 H5 DSP_RESETSTAT# 9 8 [22] DSP_PORZ IN OUT DSP_RESETSTAT# [22] DSP_RESETFULLZ J4 PORz RESETSTATz H3 DSP_BOOTCOMPLETE GND2 GND1 [22] DSP_RESETFULLZ IN OUT DSP_BOOTCOMPLETE [22] DSP_RESETZ H4 RESETFULLz BOOTCOMPLETE G2 DSP_HOUT [22] DSP_RESETZ IN RESETz HOUT OUT DSP_HOUT [22] DIR = 0 --> B to A DIR = 1 --> A to B B DSP_LRESETNMIENZ F1 B [22] DSP_LRESETNMIENZ IN DSP_CORESEL0 J5 LRESETNMIENz [22] DSP_CORESEL0 IN DSP_CORESEL1 G5 CORESEL0 VCC1V8 [22] DSP_CORESEL1 IN CORESEL1 DSP_LRESETZ G4 VCC3V3_AUX VCC3V3_AUX [22] DSP_LRESETZ IN DSP_NMIZ H1 LRESETz R2204 [22] DSP_NMIZ IN NMIz

4.7K C522 C472 1uF 100nF DSP_LRESETNMIENZ R329 R330 DSP_PORZ 4.7K 4.7K U249 DSP_RESETFULLZ MAX3221ECPWR DSP_RESETZ 12 15 R200 R188 R187 16 FORCEON VCC FORCEOFF# COM1 4.7K 4.7K 4.7K UART_MAX_RX 9 8 RS232_RX 22-23-2031 ROUT RIN 3 2 UART_MAX_TX 11 13 RS232_TX 1 DIN DOUT

R384 C154 100nF 2 5 C156 100nF 4.7K C1+ C2+ 4 6 C1- C2-

VCC1V8 C155 100nF 3 7 C157 100nF V+ V- 1 Reserved R2960 10 EN# 14 DSP1S INVALID# GND TMS320C6657 4.7K AA22 H22 R343NU 0E RSV01 RSV11 Project A R1601NU 0E J3 Y5 R344NU 0E Designed for TI by eInfochips A R1602NU 0E H2 RSV02 RSV12 Y4 R345NU 0E TMDSEVM6657 R358NU 0E AC18 RSV03 RSV13 F21 R349NU 0E R359NU 0E AB18 RSV04 RSV14 G21 R346NU 0E RSV05 RSV15 R356NU 0E B23 J20 R351NU 0E Title R357NU 0E A23 RSV06 RSV16 AA7 R352NU 0E R1603NU 0E Y19 RSV07 RSV17 AA11 R354NU 0E R1604NU 0E C23 RSV08 RSV18 AB3 R355NU 0E DSP MISC R342 0E G22 RSV09 RSV19 RSV10 Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 17of 29

5 4 3 2 1 5 4 3 2 1

DSP1H DSP CLOCK TMS320C6657 TP12

C494 100nF AD18 [19] CORECLKP IN C493 100nF AE19 CORECLKP 100.00MHz [19] CORECLKN IN CORECLKN C496 100nF A22 [19] DDRCLKP IN C495 100nF B22 DDRCLKP AA19 DSP_SYSCLKOUT 66.67MHz [19] DDRCLKN IN DDRCLKN SYSCLKOUT OUT DSP_SYSCLKOUT [22] C500 100nF AD13 [19] SRIOSGMIICLKP IN C499 100nF AE14 SRIOSGMIICLKP 250MHz [19] SRIOSGMIICLKN IN SRIOSGMIICLKN DSP_PCIECLKP C502 100nF AD14 D D DSP_PCIECLKN C501 100nF AE15 PCIECLKP 100.00MHz PCIECLKN C504 100nF C25 [19] HyperLink_CLKP IN C503 100nF B25 MCMCLKP 250MHz [19] HyperLink_CLKN IN MCMCLKN

All blocking capacitors to be placed near DSP to keep connecting routes short and minimize vias

PCI CLOCK MUX VCC3V3_AUX_ICS557 U1 IDT5V41068APGGI VCC3V3_AUX VCC3V3_AUX_ICS557 [11] 2 1 B22 PCIE_REF_CLK_P IN IN1 VDD_1 10 1 3 R450 100E VDD_2 11 (LVDS) VDD_3 3 C17 C16 C18 C421 C527 [11] PCIE_REF_CLK_N IN IN1 10nF 10nF 10nF 10uF 10uF 15 PCI-E_P R241% 33E DSP_PCIECLKP 2200pF C1225 100nF PCIECLKP_R 5 CLK 2 [19] PCIECLKP IN VCC3V3_AUX_ICS557 VCC3V3_AUX IN2 R372 100E (HCSL) R444 100E C 14 PCI-E_N R391% 33E DSP_PCIECLKN C R433 C1226 100nF PCIECLKN_R 6 CLK [19] PCIECLKN IN R453 IN2 R426 R425 NU 10K 9 R40 475E PCIECLKP_R 10K IREF 150E 150E CLK_MUX_SEL 16 8 [22] CLK_MUX_SEL IN SEL GND_1 CLK_MUX_SEL 12 SEL I/p PAIR SEL 4 GND_2 13 [22] CLK_MUX_PD# IN PCIECLKN_R 7 PD GND_3 [22] CLK_MUX_OE IN OE R486 LOW IN2/IN2# R434 R436 R442

10K 1.2K 10K 10K HIGH IN1/IN1#

SMART REFLEX

B VCC3V3_AUX B

VCC1V8 VCC1V8 VCC3V3_AUX VCC1V8 NU R475 VCC3V3_AUX R2130 0E [23] FPGA_VID_OE# IN 10K R2131 0E VID_OE# C175 R131 R130 C174 U19 100nF DSP1G R322 R323 R320 R321 100nF SN74AVC4T245PWR TMS320C6657 R326 R327 R324 R325 4.7K 4.7K Q6 3 16 1 10K 10K 10K 10K 2N7002 D 10K 10K 10K 10K VCCB VCCA DSP_VIDA E22 F22 DSP_VCL G 15 2 DSP_VIDB E23 VCNTL0 VCL D23 DSP_VD 1 VID_OE# 14 1OE 1DIR 3 [22,28] VCC1V8_PG IN DSP_VIDC F23 VCNTL1 VD S 2OE 2DIR DSP_VIDS G23 VCNTL2 DSP_VIDA 13 4 2 OUT UCD9222_VIDA [26] VCNTL3 DSP_VIDB 12 1B1 1A1 5 OUT UCD9222_VIDB [26] DSP_VIDC 11 1B2 1A2 6 OUT UCD9222_VIDC [26] DSP_VIDS 10 2B1 2A1 7 2B2 2A2 OUT UCD9222_VIDS [26]

9 8 GND2 GND1 DIR = 0 --> B to A DIR = 1 --> A to B

VCC1V8 VCC3V3_AUX VCC3V3_AUX

C521 C520 Project A Designed for TI by eInfochips A 100nF 100nF TMDSEVM6657 U248 R328 R129 R128 PCA9306DCUR 100K Reserved for future use 2 7 Not supported at this time Title VREF1 VREF2 8 4.7K 4.7K EN IN PCA9306_EN [22] DSP_VCL 3 6 DSP-CLOCK & SMART REFLEX OUT DSP_VCL_3V3 [22] DSP_VD 4 SCL1 SCL2 5 SDA1 SDA2 BI DSP_VD_3V3 [22] 1 Document Number Rev GND Size C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 18of 29

5 4 3 2 1 5 4 3 2 1

CLOCK GEN2

VCCPLLA2C

VCCPLLA2B

VCCPLLA2A VCC3V3_AUX TCLKB_P C604 100nF 10V NU VCC_VCO2B OUT TCLKB_P_R [22] TCLKB_N C598 100nF 10V NU D OUT TCLKB_N_R [22] VCC_VCO2A D These caps should be located near CDCE62005(CLK2) C320 1uF

CLK2 48 44 15 47 1 8 11 18 21 26 29 32 34 35 5 39 42

TP36 TP37 VBB

3

These caps should be located VCC_OUT1 VCC_OUT2 VCC_OUT3 VCC_OUT4 VCC_OUT5 VCC_OUT6 VCC_OUT7 VCC_VCO1 VCC_VCO2 SECREF+ VCC1_PLL1 VCC1_PLL2 VCC1_PLL3 VCC_AUXIN 2 VCC_IN_PRI 27 near CDCE62005(CLK2) SECREF- VCC_IN_SEC U0P OUT HyperLink_CLKP [18] VCC_AUXOUT 28 OUT HyperLink_CLKN [18] 250.00MHz C606 100nF 10V 45 U0N [11] TCLKB_P IN PRIREF+ [11] C605 100nF 10V 46 19 [18] TCLKB_N IN PRIREF- U1P 20 OUT SRIOSGMIICLKP [18] VCC3V3_AUX TP44 TP45 40 U1N OUT SRIOSGMIICLKN 250.00MHz EXT_LFP 41 16 [18] EXT_LFN U2P 17 OUT DDRCLKP OUT DDRCLKN [18] R170 R173 U2N 50.00MHz 33 9 NU [18] 10K 31 TEST_MODE U3P 10 OUT CORECLKP CDCE62005RGZT [18] 10K 14 REF_SEL U3N OUT CORECLKN 100.00MHz SYNC 6 U4P OUT PCIECLKP [18] 7 [18] 25 U4N OUT PCIECLKN 100.00MHz [23] CLOCK2_SSPCS1 IN 24 SPI_LE TP29 [23] C366NU 47pF CLOCK2_SSPCK IN 23 SPI_CLK [23] CLOCK2_SSPSI IN 22 SPI_MOSI 13 7A-25.000MAAJ-T [23] CLOCK2_SSPSO OUT SPI_MISO AUXOUT 43 REFCLK2_XTALIN Y5 12 AUXIN [23] REFCLK2_PD# IN 30 Power_Down# TESTOUTA 37 OUT CLOCK2_PLL_LOCK [23] R366 R172 C333 1uF 4 PLL_LOCK REG_CAP1 10K 1K C334 1uF 38 REG_CAP2

C 49 C EPAD 36 GND_VCO

VCC3V3_AUX VCC3V3_AUX

C310 C311 C312 C313 C314 C309 C315 C316 C317 C318 C319 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

VCC3V3_AUX VCC_VCO2A B11 VCC3V3_AUX VCCPLLA2C 1 3 B12 1 3 B B

C321 C322 2200pF 100nF 1uF C323 C324 2 2200pF 100nF 1uF 2

VCC3V3_AUX VCC_VCO2B B13 1 3

C329 C330 VCC3V3_AUX VCCPLLA2B 2200pF 100nF 1uF B14 2 1 3

C331 C332 2200pF 100nF 1uF 2 VCC3V3_AUX VCCPLLA2A B15 1 3

C335 C336 2200pF 100nF 1uF 2 Project A Designed for TI by eInfochips A TMDSEVM6657 Title CLOCK GENRATION

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 19of 29

5 4 3 2 1 5 4 3 2 1

VCC3V3_AUX USB, JTAG

C120 C121 C122 C123

100nF 100nF 100nF 100nF

VCC3V3_AUX VCC1V8_AUX VCC3V3_AUX VCC3V3_AUX U9 J4 VCC3V3_AUX FT2232HL 20 31 42 56 50 1 2 R1910 B4 12 C117 C118 C119 C2227 U259 VCC3V3_AUX 120_100MHz VCORE1 37 TSW-102-07-S-S U266 TS3L301DGG D VCORE2 4.7K D VCCIO1 VCCIO2 VCCIO3 VCCIO4 100nF 100nF 100nF SN74LVC1G08DCKR 100nF VPLL 9 VREGIN 64 R2107 R2108 R2109 R2110 VPLL VCORE3 1 5 1 C115 C116 49 A VCC VDD[1] 6 VREGOUT 4.7K 4.7K 4.7K 4.7K VDD[2] FT2232HL_RESET# 2 AND 4 24 12 C161 C365 C601 10nF 100nF B Y SEL VDD[3] 19 16 R88 22E FT_TDK 3 VDD[4] 36 100nF 100nF 10uF TCK 17 R89 22E FT_TDI GND VDD[5] TDI 18 R91 22E FT_TDO B5 TDO 19 R92 22E FT_TMS AMC_JTAG_TCK 48 2 3V3_TCK [11] AMC_JTAG_TCK IN 120_100MHz TMS 21 R93 22E FT_TRST# AMC_JTAG_TDI 47 0B1 A0 4 3V3_TDI [11] AMC_JTAG_TDI IN VPHY 4 GPIOL0 AMC_JTAG_TDO 42 1B1 A1 8 3V3_TDO [11] AMC_JTAG_TDO OUT VPHY R171 AMC_JTAG_TMS 41 2B1 A2 10 3V3_TMS [11] AMC_JTAG_TMS IN C126 C127 AMC_JTAG_RST# 35 3B1 A3 15 3V3_TRST# [11] AMC_JTAG_RST# IN VCC5_VBUS VCC3V3_AUX R908 4.7K 34 4B1 A4 17 3V3_EMU_00 10nF 100nF 1K VCC3V3_AUX VCC3V3_AUX R909 4.7K 29 5B1 A5 21 3V3_EMU_01 28 6B1 A6 23 22 GPIOL1 7B1 A7 R137 GPIOL1 R96 R97 FT_TDK 45 0E 23 GPIOL2 R98 FT_TDI 44 0B2 GPIOL2 U11D 4.7K FT_TDO 39 1B2 USB1 C129 100nF 24 GPIOL3 4.7K 4.7K SN74AHC00PWR FT_TMS 38 2B2 54819-0519 GPIOL3 12 FT_TRST# 32 3B2 14 6 11 U11B FT_EMU0 31 4B2 NC 1 13 SN74AHC00PWR FT_EMU1 26 5B2 VBUS 2 USB_DM 7 4 25 6B2 D- DM 7B2 PTH1 3 USB_DP 90 OHM DIFF. IMPEDANCE CONTROL 8 6 R100 22E FT_EMU0 3 D+ 4 DP 5 GND[1] 5 GND_1 5 GND[2] 7

PTH2 GND_2 GND[3] 9 VCC5_VBUS GND[4] 11 7 D4 D5 26 30 GND[5] 13 PGB1010603 PGB1010603 R95 4.7K FT2232HL_RESET# 14 GPIOH0 27 9 33 GND[12] GND[6] 16 RESET GPIOH1 28 8 R101 22E FT_EMU1 37 GND[13] GND[7] 18 R138 10K GPIOH2 29 10 40 GND[14] GND[8] 20 B6 120_100MHz GPIOH3 30 43 GND[15] GND[9] 22 GPIOH4 32 U11C 46 GND[16] GND[10] 27 GND_USB GPIOH5 33 SN74AHC00PWR GND[17] GND[11] GPIOH6 C 34 C C130 33pF 2 GPIOH7 GND_USB OSCI 1 38 [12,17] 2 BDBUS0/TXD 39 OUT UART_FT_RX Y2 [12,17] BDBUS1/RXD 40 IN UART_FT_TX 4 BDBUS2 41 Switch for JTAG emulation ABM3B-12.000MHZ-B2-T BDBUS3 43 FT2232HL_RESET# = 0 --> AMC BDBUS4 44 R204 FT2232HL_RESET# = 1 --> Mini USB 3 BDBUS5 C131 33pF 3 45 4.7K VCC3V3_AUX VCC3V3_AUX OSCO BDBUS6 46 BDBUS7 48 VCC3V3_AUX R103 BCBUS0 52 BCBUS1 53 C135 100nF C132 R956 U12 BCBUS2 54 100nF 4.7K AT93C46DN-SH-T 10K BCBUS3 55 U11A 8 1 63 BCBUS4 57 SN74AHC00PWR 7 VCC CS 2 62 EECS BCBUS5 58 1 14 6 NC SK 3 EECLK BCBUS6 59 TP10 TP11 3 5 ORG DI 4 R102 2.2K 61 BCBUS7 R104 4.7K 2 GND DO EEDATA 60 7 6 PWREN REF 36 SUSPEND R94 1% TEST GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 AGND 12.1K 1 5 13 11 15 25 35 47 51 10

B B VCC3V3_AUX

C2226 VCC3V3_AUX VCC1V8_AUX VCC3V3_AUX OR GATE U254 U267 100nF TS3L301DGG VCC3V3_AUX SN74LVC1G32DCKR 1 5 1 VCC1V8 [16] EXT_EMU_DET0 IN A VCC VDD[1] 6 C124 C125 2 4 24 VDD[2] 12 C133 C134 C396

1 2 OR B Y SEL VDD[3] 19 R955 100nF U10 100nF 3 VDD[4] 36 100nF 100nF 10uF TXS0108EPWR R1106 GND VDD[5] 19 J5 4.7K VCCB TSW-102-07-S-S 48 2 10 2 [16] [16] 4.7K EMU_TCK_BUF IN 47 0B1 A0 4 OUT DSP_TCK OE VCCA [16] EMU_TDI IN OUT DSP_TDI [16] 42 1B1 A1 8 3V3_TCK 20 1 1V8_TCK [16] EMU_TDO OUT IN DSP_TDO [16] 41 2B1 A2 10 3V3_TDI 18 B1 A1 3 1V8_TDI [16] EMU_TMS IN OUT DSP_TMS [16] 35 3B1 A3 15 3V3_TDO 17 B2 A2 4 1V8_TDO [16] EMU_TRST# IN OUT DSP_TRST# [16] 34 4B1 A4 17 3V3_TMS 16 B3 A3 5 1V8_TMS [16] EMU_EMU_00 BI 5B1 A5 BI DSP_EMU_00 [16] B4 A4 [16] EMU_EMU_01 BI 29 21 BI DSP_EMU_01 [16] 3V3_TRST# 15 6 1V8_TRST# 28 6B1 A6 23 3V3_EMU_00 14 B5 A5 7 1V8_EMU_00 7B1 A7 3V3_EMU_01 13 B6 A6 8 1V8_EMU_01 1V8_TCK 45 12 B7 A7 9 1V8_TDI 44 0B2 11 B8 A8 1V8_TDO 39 1B2 GND 1V8_TMS 38 2B2 1V8_TRST# 32 3B2 14 1V8_EMU_00 31 4B2 NC 1V8_EMU_01 26 5B2 25 6B2 7B2 3 GND[1] 5 GND[2] 7 GND[3] 9 GND[4] Project A 11 Designed for TI by eInfochips A 30 GND[5] 13 TMDSEVM6657 33 GND[12] GND[6] 16 37 GND[13] GND[7] 18 40 GND[14] GND[8] 20 Title 43 GND[15] GND[9] 22 46 GND[16] GND[10] 27 GND[17] GND[11] USB-JTAG

Size Document Number Rev Switch for JTAG emulation C 16_00132_02 2.9 EXT_EMU_DET = 0 --> External / Mezzanine Emulator EXT_EMU_DET = 1 --> On board emulation Date: Thursday, November 28, 2013 Sheet 20of 29

5 4 3 2 1 5 4 3 2 1

ETHERNET PHY ETHERNET JACK

LED (Colour) Link No Link

LOS (Orange/Green) ON OFF

D D

VCC2V5 VCC1V2 VCC2V5 AVCC2V5 C21 C22 ETH_LOS/LED R1130 100E 100nF 100nF VCC2V5 If both fiber (SGMII) and copper (1000BASE-X) cables are C24 470pF VCC2V5 R1657 R1656 VCC2V5 connected, the preferred media will be selected based on value of register 16_2.11:10. If it is: NU U264 LAN1 24LC02B-I/ST 4.7K 4.7K R2203 R26 R27 R28 R29 VCC2V5 13 8 PHY1 00: Link with 1st media to establish link

39 43 47 62 64 37 56 20 23 24 29 33 7 14 6 13 O/G VCC 6 ETH_SCL NU R764 R765 R146 88E1112 01: Prefer fiber media 14 C1372 1 SCL 5 ETH_SDA 10K 10: Prefer copper media 49.9E 49.9E 49.9E 49.9E 100nF 2 A0 SDA 11 3 A1 7 ETH_WP 10K 10K 10K MDI0_P A2 WP 4 12 VDDA_1 VDDA_2 VDDA_3 VDDA_4 VDDA_5 DVDD_1 DVDD_2 DVDD_3 DVDD_4 DVDD_5 VDDO_1 VDDO_2 P1_TCT VSS VDDAL_1 VDDAL_2 R2226 61 VDDAH_1 VDDAH_2 MDI0_N 1 [23] PHY_INT# OUT INIT 10 2 31 MDI3_P TX1+ MDI[3]_N 256 Bytes EEPROM 10K 49 30 MDI3_N 4 TX1- NORMAL MDI[3]_P 28 MDI2_P MDI1_P 60 MDI[2]_N 27 MDI2_N 6 Read Address: 1010 0001 (0x50) P1_TCT Write Address: 1010 0000 (0x50) SDET MDI[2]_P 22 MDI1_P MDI1_N 3 MDI[1]_N ETH_SCL 54 21 MDI1_N 5 6 ETH_SDA 53 SCL MDI[1]_P 19 MDI0_P TX2+ SDA MDI[0]_N 18 MDI0_N 3 MDI[0]_P TX2- MDI2_P 4 57 1 [13] ETH_MDC IN P1_TCT 58 MDC 8 DSP_SGMII_TXN_C C136 100nF MDI2_N [13] ETH_MDIO BI IN DSP_SGMII_TXN [13] MDIO SIN_N 9 DSP_SGMII_TXP_C C137 100nF 2 IN DSP_SGMII_TXP [13] SIN_P 1 DSP_SGMII_RXN OUT DSP_SGMII_RXN [13] LAN_RST 52 SOUT_N 2 DSP_SGMII_RXP 8 TX3+ RESET SOUT_P OUT DSP_SGMII_RXP [13] 5 4 R391 4.99K MDI3_P TX3- SCLK_N 5 7 7 R392 4.99K P1_TCT ETH_CONFIG0 48 SCLK_P MDI3_N ETH_CONFIG1 46 CONFIG[0] 9 ETH_CONFIG2 45 CONFIG[1] 40 STATUS_0 CONFIG[2] STATUS[0] 8 C ETH_CONFIG3 44 38 STATUS_1 VCC2V5 16 TX4+ H1 C ETH_CONFIG4 42 CONFIG[3] STATUS[1] R31 R32 R33 R34 G O 75R H2 TX4- ETH_CONFIG5 41 CONFIG[4] STATUS_0 R35 100E 17 H3 CONFIG[5] 15 AMC_SGMII_RXN_C C1370 100nF STATUS_1 R36 100E 15 H4 IN AMC_SGMII_RXN [11] 1000pF 2kV VCC2V5 TP133 FIN_N 16 AMC_SGMII_RXP_C C353 100nF 49.9E 49.9E 49.9E 49.9E IN AMC_SGMII_RXP [11] TP23 26 FIN_P 10 AMC_SGMII_TXN SHIELD GND OUT AMC_SGMII_TXN [11] HSDAC_N FOUT_N 11 AMC_SGMII_TXP J0G-0001NL or J0G-0003NL OUT AMC_SGMII_TXP [11] R431 25 FOUT_P C29 C30 GND_LAN HSDAC_P VCC2V5 100nF 100nF 1% NU 59 ETH_LOS/LED R1658 4.7K 1M LOS C25 33pF 36 XTAL1 TP162 1 2 34 Y3 35 TSTPT 50 4 XTAL2 PWRDN ABM3B-25.000MHZ-B2-T R1273 3

RSET S_VTT F_VTT POL_RST NC VSS_1 VSS_2 ePAD LED (Colour) VCC2V5 C23 33pF 1Gbps 100Mbps 10Mbps 4.7K 3 17 12 51 32 55 63 65 Activity No Activity Activity No Activity Activity No Activity U252 R99 R147 4.99K SN74LVC1G07DBVR Status 0 (Green) BLINK SOLID ON BLINK SOLID ON OFF OFF 1 VCC 5 1% 2 10K [23] PHY_RST IN 3 4 LAN_RST Status 1 (Orange) OFF OFF BLINKSOLID ON BLINK SOLID ON GND

Pin to Configuration Bit Mapping VCC2V5 P1_TCT VCC1V2 B37 120_100MHz B B C150 C149 C152 C151 C148 PIN BIT[1] BIT[0] PIN VALUE POL_RST RESET=0 RESET=1 C62 C58 C61 C57 C50 100nF 100nF 100nF 100nF 100nF 4.7uF 100nF 100nF 10nF 10nF CONFIG0 PHYADR[1] PHYADR[0] VDD0 11 0 Reset Normal

CONFIG1 PHYADR[3] PHYADR[2] STATUS[0] 10 1 or Floating Normal Reset CONFIG2 SGMII_CLK PHYADR[4] STATUS[1] 01

CONFIG3 SEL_TWSI SEL_VTT VSS 00 AVCC2V5 VCC2V5 CONFIG4 EEPROM[1] EEPROM[0] B7 FOR EMI 120_100MHz CONFIG5 MODE[1] MODE[0] B3 120_100MHz C142 C141 C1147 C1146 C1148 C1149 C140 C145 C144 C143

4.7uF 100nF 100nF 100nF 10nF 10nF 10nF 4.7uF 100nF 10nF

ETH_CONFIG4 R777 0E STATUS_1 GND_LAN 01 PIN VALUE CONNECTION INTERPRETATION ETH_CONFIG2 R775 0E 01 CONFIG0 00 VSS PHY Address[1:0] is 00 ETH_CONFIG5 R778 0E STATUS_0 10 CONFIG1 10 STATUS[0] PHY Address[3:2] is 10 ETH_CONFIG1 R774 0E 10 Project A Designed for TI by eInfochips A CONFIG2 01 STATUS[1] SGMII_CLK not supplied; PHY Address[4] is 1 TMDSEVM6657 ETH_CONFIG0 R779 0E 00 CONFIG3 00 VSS MDC/MDIO mode; S_VTT & F_VTT int supplied Title ETH_CONFIG3 R776 0E 00 CONFIG4 01 STATUS[1] Start reading from address 0 GIGABIT ETHERNET CONFIG5 10 STATUS[0] SGMII MAC Int to Auto Media select (Cu/SGMII) Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 21of 29

5 4 3 2 1 5 4 3 2 1

FPGA - POWER & RST CTRL, McBSP R409NU 0E DSP_VCL_FPGA FPGA - POWER, JTAG R410NU 0E DSP_VD_FPGA Reserved for PMBUS_CLK R394NU 0E future use IN DSP_VCL_3V3 [18] PMBUS_DAT R395NU 0E BI DSP_VD_3V3 [18]

FPGA1C A1 FPGA_DONE T15 GND_1 A16 [23] FPGA_DONE OUT FPGA_PROG A2 DONE GND_2 B7 D PROG GND_3 B11 D GND_4 C3 FPGA_JTAG_TCK A15 GND_5 C14 FPGA_JTAG_TDI R967 22E B1 TCK GND_6 E5 FPGA_JTAG_TDO B16 TDI GND_7 E12 VCC3V3_FPGA FPGA_JTAG_TMS B2 TDO GND_8 F2 TMS GND_9 F6 GND_10 G8 VCC3V3_FPGA GND_11 G10 R201 GND_12 G15 E11 GND_13 H9 F5 VCCAUX_1 GND_14 J8 10K FPGA1A C419 C418 C417 C425 C413 C412 C400 C391 L12 VCCAUX_2 GND_15 K2 M6 VCCAUX_3 GND_16 K7 R79 1K N14 C13 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF VCCAUX_4 GND_17 K9 [12] MMC_DETECT# IN IN DSP_RESETSTAT# [17] DSP N13 IO_L01N_1/LDC2 IO_L01N_0 D13 GND_18 L11 [12] MMC_RSTSTAT# R80 1K [16] OUT P15 IO_L01P_1/HDC IO_L01P_0 B14 IN TRGRSTZ VCC1V2_FPGA GND_19 L15 MMC [12] R81 1K [17] EEPROM MMC_POR_AMC# IN R15 IO_L02N_1/LDC0 IO_L02N_0 B15 OUT EEPROM_WP GND_20 M5 [12] R84 1K [17] NOR Flash MMC_WR_AMC# IN N16 IO_L02P_1/LDC1 IO_L02P_0/VREF_0_1 D11 OUT NOR_WP# G7 GND_21 M12 [12] MMC_BOOTCOMP OUT P16 IO_L03N_1/A1 IO_L03N_0 C12 G9 VCCINT_1 GND_22 P3 [18] PCA9306_EN OUT VCL/VDA Enable M14 IO_L03P_1/A0 IO_L03P_0 A13 TP13 TP14 C534 C476 C475 C535 C416 C415 C414 C394 H8 VCCINT_2 GND_23 P14 TP15 M13 IO_L05N_1/VREF_1_1 IO_L04N_0 A14 J9 VCCINT_3 GND_24 R6 [27] VCC5_PG IN IO_L05P_1 IO_L04P_0 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF VCCINT_4 GND_25 [28] K13 A12 R1379 0E [11] K8 R10 VCC2V5_PG IN L13 IO_L06N_1/A3 IO_L05N_0 B12 OUT McBSP_AMC_EN# K10 VCCINT_5 GND_26 T1 [27] VCC3V3_AUX_PG IN IO_L06P_1/A2 IO_L05P_0 IN DSP_SSPCS1 [12,17] VCCINT_6 GND_27 [28] M16 E10 [17] T16 VCC0V75_PG IN M15 IO_L07N_1/A5 IO_L06N_0/VREF_0_2 D10 IN FPGA_SSPCK XC3S200AN-4FTG256C GND_28 [27] R400 10E [12,17] C6657 SPI VCC1V5_PG IN L16 IO_L07P_1/A4 IO_L06P_0 A11 OUT DSP_SSPMISO TP16 IN DSP_SSPMOSI [12,17] R474 0E L14 IO_L08N_1/A7 IO_L07N_0 C11 R1185 33E Power Sequence [27] VCC1V5_EN OUT OUT DSP_McBSP0_SLCLK [12,13] DSP McBSP J13 IO_L08P_1/A6 IO_L07P_0 A10 R1187 33E [18] CLK_MUX_OE OUT OUT DSP_McBSP1_SLCLK [12,13] SCLK R477 0E J12 IO_L10N_1/A9 IO_L08N_0 B10 [28] VCC1V8_EN1 OUT OUT DSP_LRESETNMIENZ [17] R478 0E K14 IO_L10P_1/A8 IO_L08P_0 D9 [28] VCC0V75_EN OUT OUT DSP_CORESEL0 [17] R479 0E K15 IO_L11N_1/RHCLK1 IO_L09N_0/GCLK5 C10 [28] VCC2V5_EN OUT IO_L11P_1/RHCLK0 IO_L09P_0/GCLK4 OUT DSP_CORESEL1 [17] [27] VCC_5V_EN R480 0E J16 A9 OUT K16 IO_L12N_1/TRDY1/RHCLK3 IO_L10N_0/GCLK7 C9 [26] UCD9222_PG2 IN IO_L12P_1/RHCLK2 IO_L10P_0/GCLK6 60 Pin Header [26] UCD9222_ENA2 R481 0E H14 D8 [17] OUT J14 IO_L14N_1/RHCLK5 IO_L11N_0/GCLK9 C8 OUT DSP_NMIZ [26] UCD9222_PG1 IN OUT DSP_LRESETZ [17] C6657 R482 0E H16 IO_L14P_1/RHCLK4 IO_L11P_0/GCLK8 B8 [26] UCD9222_ENA1 OUT IO_L15N_1/RHCLK7 IO_L12N_0/GCLK11 IN DSP_HOUT [17] VCC1V2 VCC1V2_FPGA VCC3V3_AUX VCC3V3_FPGA C [26] H15 A8 [17] C PGUCD9222 IN F16 IO_L15P_1/IRDY1/RHCLK6 Bank1 Bank0 IO_L12P_0/GCLK10 C7 IN DSP_BOOTCOMPLETE UCD9222 [26] UCD9222_RST# OUT IN DSP_SYSCLKOUT [18] R153 0E G16 IO_L16N_1/A11 IO_L13N_0 A7 [26] PMBUS_CLK OUT IN VCC1V8_PG [18,28] R154 0E G14 IO_L16P_1/A10 IO_L13P_0 E7 DSP_PORZ B26 120_100MHz B25 120_100MHz [26] PMBUS_DAT BI OUT DSP_PORZ [17] R155 0E H13 IO_L17N_1/A13 IO_L14N_0/VREF_0_3 F8 DSP_RESETFULLZ [26] PMBUS_ALT IN OUT DSP_RESETFULLZ [17] R156 0E F15 IO_L17P_1/A12 IO_L14P_0 B6 DSP_RESETZ C392 C393 C385 C386 [26] PMBUS_CTL OUT OUT DSP_RESETZ [17] DSP_VCL_FPGA E16 IO_L18N_1/A15 IO_L15N_0 A6 OUT NAND_WP# [16] DSP_VD_FPGA F14 IO_L18P_1/A14 IO_L15P_0 C6 R1173 33E 10uF 100nF 10uF 100nF OUT DSP_McBSP0_TXCLK [12,13] SYS_PGOOD G13 IO_L19N_1/A17 IO_L16N_0 D7 R1174 33E OUT DSP_McBSP0_RXCLK [12,13] F13 IO_L19P_1/A16 IO_L16P_0 C5 R1175 33E [18] CLK_MUX_SEL OUT OUT DSP_McBSP1_TXCLK [12,13] FULL_RESET E14 IO_L20N_1/A19 IO_L17N_0 A5 R1176 33E OUT DSP_McBSP1_RXCLK [12,13] DSP McBSP WARM_RESET D15 IO_L20P_1/A18 IO_L17P_0 B4 OUT DSP_McBSP0_FST [12,13] CLK & FS Reset Switch Cold_RESET D16 IO_L22N_1/A21 IO_L18N_0 A4 OUT DSP_McBSP0_FSR [12,13] FPGA_JTAG_RST# D14 IO_L22P_1/A20 IO_L18P_0 B3 [12,13] E13 IO_L23N_1/A23 IO_L19N_0 A3 OUT DSP_McBSP1_FST [18] CLK_MUX_PD# OUT IO_L23P_1/A22 IO_L19P_0 OUT DSP_McBSP1_FSR [12,13] [11] C15 D5 FPGA_PUDC TCLKA_N IN C16 IO_L24N_1/A25 IO_L20N_0/PUDC C4 VCC3V3_AUX [11] TCLKA_P IN IO_L24P_1/A24 IO_L20P_0/VREF_0_4 OUT XDS560_IL [27] [19] K12 D6 TCLKB_N_R IN K11 IP_L04N_1/VREF_1_2 IP_0_1 D12 [19] TCLKB_P_R IN J11 IP_L04P_1 IP_0_2 E6 VCC3V3_FPGA AMC TCLK [11] TCLKC_N IN J10 IP_L09N_1 IP_0_3 F7 [11] TCLKC_P IN H11 IP_L09P_1/VREF_1_3 IP_0_4 F9 TAP_FPGA1 VCC1V8_AUX R370 R424 R414 R413 R371 [11] TCLKD_N IN IP_L13N_1 IP_0_5 VCC1V8_AUX VCC1V8_AUX TSW-108-07-S-S [11] H10 F10 NU TCLKD_P IN G11 IP_L13P_1 IP_0_6 E9 R159 0E G12 IP_L21N_1 IP_0_7/VREF_0_5 B5 B34 120_100MHz 1 4.7K 4.7K 4.7K 4.7K 1K VCC3V3_FPGA F11 IP_L21P_1/VREF_1_4 VCCO_0_1 B9 R181 2 F12 IP_L25N_1 VCCO_0_2 B13 3 R965 22E FPGA_JTAG_TCK R16 IP_L25P_1/VREF_1_5 VCCO_0_3 E8 C383 C533 C532 C531 4 FPGA_JTAG_TDI B33 120_100MHz E15 SUSPEND VCCO_0_4 100nF 100nF 100nF 100nF 10K 5 R966 22E FPGA_JTAG_TDO H12 VCCO_1_1 FPGA_PUDC 6 FPGA_JTAG_TMS VCCO_1_2 J15 XC3S200AN-4FTG256C 7 FPGA_JTAG_RST# C600 C599 C546 C384 N15 VCCO_1_3 R182 8 100nF 100nF 100nF 100nF VCCO_1_4 NU

PUDC (User I/O Pull-Up Control) 10K If its value during configuration is: C15 R315 4.7K B 0: enable PUs in all I/O pins to resp VCCO 100nF B 1: No pull-ups Place near FPGA

TCLKA_P R228 100E TCLKA_N VCC3V3_FPGA TCLKB_P_R R317 100E TCLKB_N_R TCLKC_P R318 100E TCLKC_N VCC3V3_FPGA TCLKD_P R319 100E TCLKD_N R217

1K R218

FPGA_DONE 4.7K

R219 NU FPGA_PROG

330E R220 1 D11 Must be High During Configuration NU G NU to allow configuration to start 100K GRN 2

VCC3V3_FPGA VCC3V3_FPGA VCC3V3_FPGA SYS_PGOOD

R5 R74 R139 R184 Cold_RESET WARM_RESET FULL_RESET 10K 10K 10K 330E Project A SW1-P1 R8 100E Cold_RESET SW7-P1 R68 100E WARM_RESET SW8-P1 R140 100E FULL_RESET Designed for TI by eInfochips A 1 SYSPG_D1 High active TMDSEVM6657 C9 B RST_COLD1 10nF RST_WARM1 C11 RST_FULL1 C13 A A 10nF A 10nF YEL

2 Title G1 G1 G1 G2 G2 G2 FPGA-POWER,RESET,McBSP EVQ-PF003M EVQ-PF003M EVQ-PF003M B B B Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 22of 29

5 4 3 2 1 5 4 3 2 1

BOOT STRAP CONFIGURATION

VCC1V8_AUX FPGA, BOOT MODE & SMART REFLEX SW3 SDA08H1SBD R209 10K BM_GPIO_00 1 ON 16 R211 100E R210 10K BM_GPIO_01 2 15 R212 100E R213 10K BM_GPIO_02 3 14 R214 100E R215 10K BM_GPIO_03 4 13 R216 100E VCC3V3_AUX R284 10K BM_GPIO_04 5 12 R285 100E R265 10K BM_GPIO_05 6 11 R289 100E R296 10K BM_GPIO_06 7 10 R283 100E VCC3V3_FPGA VCC3V3_FPGA B24 R264 10K BM_GPIO_07 8 9 R297 100E

SW5 Y7 D 120_100MHz SDA08H1SBD D R196 R195 R194 4 3 R178 33E MAIN_48MHZ_CLK_R R301 10K BM_GPIO_08 1 ON 16 R302 100E R189 R190 C387 2 VCC OUT 1 R299 10K BM_GPIO_09 2 15 R303 100E GND OE 4.7K 4.7K 100nF C382 R304 10K BM_GPIO_10 3 14 R300 100E 4.7K 4.7K 4.7K U26 ASFL1-48.000MHZ-EC-T R298 10K BM_GPIO_11 4 13 R305 100E FPGA_SPI_CS# 1 8 100nF R309 10K BM_GPIO_12 5 12 R310 100E FPGA_SPI_SO 2 CS VCC 7 FPGA_SPI_HD# R308 10K BM_GPIO_13 6 11 R311 100E FPGA_SPI_WP# 3 SO HOLD 6 FPGA_SPI_SCK R312 10K BM_GPIO_14 7 10 R307 100E 4 WP SCK 5 FPGA_SPI_SI R306 10K BM_GPIO_15 8 9 R313 100E GND SI AT25128B-SSHL-B SW9 R408 10K PCIESSEN 1 ON 4 R403 100E R407 10K User_define 2 3 R402 100E

SDA02H1SBD

FPGA1B XC3S200AN-4FTG256C Boot Configuration

BM_GPIO_00 C1 P4 FPGA_M0 IO_L01N_3 IO_L01N_2/M0 BM_GPIO_01 C2 N4 FPGA_M1 DIP Switch DSP BM_GPIO Primary Function BM_GPIO_02 D3 IO_L01P_3 IO_L01P_2/M1 T2 OUT FPGA_VID_OE# [18] VID Enable BM_GPIO_03 D4 IO_L02N_3 IO_L02N_2/CSO R2 FPGA_M2 BM_GPIO_04 E1 IO_L02P_3 IO_L02P_2/M2 T3 FPGA_VS2 R423 10K 0 - Big Endian BM_GPIO_05 D1 IO_L03N_3 IO_L03N_2/VS2 R3 BM_GPIO0 GPIO0 ENDIANESS 1 - Little Endian BOOT MODE IO_L03P_3 IO_L03P_2/RDWR BM_GPIO_06 E2 P5 FPGA_VS0 R422 10K BM_GPIO[4:1] GPIO[4:1] BOOTMODE[3:0] Boot Device SWITCH BM_GPIO_07 E3 IO_L05N_3 IO_L04N_2/VS0 N6 FPGA_VS1 R421 10K BM_GPIO_08 G4 IO_L05P_3 IO_L04P_2/VS1 R5 IN CLOCK2_PLL_LOCK [19] BM_GPIO_09 F3 IO_L07N_3 IO_L05N_2 T4 BM_GPIO[10:5] GPIO[10:5]BOOTMODE[9:4] Boot Device Config BM_GPIO_10 G1 IO_L07P_3 IO_L05P_2 T6 IN PHY_INT# [21] BM_GPIO[13:11] GPIO[13:11] BOOTMODE[12:10] PLL Multiplier/I2C BM_GPIO_11 F1 IO_L08N_3/VREF_3_1 IO_L06N_2/D6 T5 PHY 88E1112 OUT PHY_RST [21] BM_GPIO_12 H4 IO_L08P_3 IO_L06P_2/D7 P6 OUT CLOCK2_SSPCS1 [19] BM_GPIO_13 G3 IO_L09N_3 IO_L07N_2 N7 R397 10E BM_GPIO[15:14] GPIO[15:14] PCIESSMODE[1:0] Endpt/RootComplex IO_L09P_3 IO_L07P_2 OUT CLOCK2_SSPCK [19] C BM_GPIO_14 H5 N8 C OUT CLOCK2_SSPSI [19] CLOCK GEN BM_GPIO_15 H6 IO_L10N_3 IO_L08N_2/D4 P7 IO_L10P_3 IO_L08P_2/D5 IN CLOCK2_SSPSO [19] [17] DSP_GPIO_00 BI H1 T7 [19] G2 IO_L11N_3/LHCLK1 IO_L09N_2/GCLK13 R7 OUT REFCLK2_PD# [17] DSP_GPIO_01 BI J3 IO_L11P_3/LHCLK0 IO_L09P_2/GCLK12 T8 Boot Device [17] DSP_GPIO_02 BI IO_L12N_3/IRDY2/LHCLK3 IO_L10N_2/GCLK15 [17] DSP_GPIO_03 BI H3 P8 J1 IO_L12P_3/LHCLK2 IO_L10P_2/GCLK14 P9 [17] DSP_GPIO_04 BI J2 IO_L14N_3/LHCLK5 IO_L11N_2/GCLK1 N9 DSP GPIO [17] DSP_GPIO_05 BI BM_GPIO BM_GPIO K1 IO_L14P_3/LHCLK4 IO_L11P_2/GCLK0 T9 MAIN_48MHZ_CLK_R Boot Device Boot Device [17] DSP_GPIO_06 BI TO FPGA K3 IO_L15N_3/LHCLK7 IO_L12N_2/GCLK3 R9 [4:1] [4:1] [17] DSP_GPIO_07 BI [12] L2 IO_L15P_3/TRDY2/LHCLK6 IO_L12P_2/GCLK2 M10 OUT MMC_SPI_SCK [17] DSP_GPIO_08 BI [12] MMC SPI L1 IO_L16N_3 Bank3 Bank2 IO_L13N_2 N10 OUT MMC_SPI_STE 0 0 0 0 Sleep/EMIF16 X 1 0 1 I2C Master [17] DSP_GPIO_09 BI IO_L16P_3/VREF_3_2 IO_L13P_2 IN MMC_SPI_MISO [12] [17] DSP_GPIO_10 BI J6 P10 [12] J4 IO_L17N_3 IO_L14N_2/MOSI/CSI T10 OUT MMC_SPI_MOSI 0 0 0 1 SRIO 0 1 0 1 I2C Slave [17] DSP_GPIO_11 BI [26] L3 IO_L17P_3 IO_L14P_2 R11 OUT UCD9222_VID2A [17] DSP_GPIO_12 BI IO_L18N_3 IO_L15N_2/DOUT OUT UCD9222_VID2B [26] UCD9222 VID CTRL X 0 1 0 Ethernet X 1 1 0 SPI [17] DSP_GPIO_13 BI K4 T11 [26] L4 IO_L18P_3 IO_L15P_2/AWAKE N11 OUT UCD9222_VID2C [12,17] DSP_GPIO_14 BI IO_L19N_3 IO_L16N_2 OUT UCD9222_VID2S [26] Reserved for future use 0 0 1 1 NAND 0 1 1 1 Hyperlink [12,17] DSP_GPIO_15 BI M3 P11 DEBUG_LED_0 N1 IO_L19P_3 IO_L16P_2 P12 DEBUG_LED_1 PCIESSEN M1 IO_L20N_3 IO_L17N_2/D3 T12 FPGA_INIT# 0 1 0 0 PCIe 1 0 0 0 UART User_define P1 IO_L20P_3 IO_L17P_2/INIT R13 DEBUG_LED_2 IO_L22N_3 IO_L18N_2/D1 Note: GPIO[10:5] bit definitions depend on the boot N2 T13 DEBUG_LED_3 mode. P2 IO_L22P_3 IO_L18P_2/D2 P13 FPGA_SPI_CS# [12,17] DSP_TIMI0 OUT R1 IO_L23N_3 IO_L19N_2 N12 FPGA_SPI_SI [12,17] DSP_TIMI1 OUT FPGA EEPROM M4 IO_L23P_3 IO_L19P_2 R14 R396 10E FPGA_SPI_SCK [12,17] DSP_TIMO0 IN IO_L24N_3 IO_L20N_2/CCLK Boot PLL Settings [12,17] N3 T14 FPGA_SPI_SO DSP_TIMO1 IN F4 IO_L24P_3 IO_L20P_2/D0/DIN/MISO L7 R473 10E [22] E4 IP_L04N_3/VREF_3_3 IP_2_1 L8 IN FPGA_DONE G5 IP_L04P_3 IP_2_2 L9 For FPGA internal reset. BM_GPIO Input Clock BM_GPIO Input Clock G6 IP_L06N_3/VREF_3_4 IP_2_3/VREF_2_1 L10 J7 IP_L06P_3 IP_2_4/VREF_2_2 M7 [13:11] (in MHz) [13:11] (in MHz) H7 IP_L13N_3 IP_2_5/VREF_2_3 M8 VCC3V3_FPGA K6 IP_L13P_3 IP_2_6/VREF_2_4 M11 0 0 0 50.00 1 0 0 156.25 VCC1V8_AUX K5 IP_L21N_3 IP_2_7/VREF_2_5 N5 L6 IP_L21P_3 IP_2_8/VREF_2_6 M9 0 0 1 66.67 1 0 1 250.00 L5 IP_L25N_3/VREF_3_5 VCCO_2_1 R4 B36 D2 IP_L25P_3 VCCO_2_2 R8 120_100MHz 0 1 0 80.00 1 1 0 312.50 B35 H2 VCCO_3_1 VCCO_2_3 R12 B 0 1 1 100.00 B 120_100MHz C439 C436 C390 C389 J5 VCCO_3_2 VCCO_2_4 C388 C435 C530 C440 1 1 1 122.88 100nF 100nF 100nF 100nF M2 VCCO_3_3 100nF 100nF 100nF 100nF VCCO_3_4

PCIe Mode Selection PCIESSMODE[1:0]

BM_GPIO PCIe Mode [15:14] 0 0 End-point mode 0 1 Legacy End-point mode (support for legacy INTx) 1 0 Root complex mode 1 1 Reserved

PCIESSEN

BM_GPIO16 PCIe Status DEBUG_LED VCC3V3_FPGA VCC3V3_FPGA VCC3V3_FPGA VCC3V3_FPGA 0 PCIe module disabled

VCC3V3_FPGA 1 PCIe module enabled

FPGA_D1 GRN R205 330E 1 2 DEBUG_LED_0 R923 R191 R192 R193 B NU 1K 330E 330E 330E Project A FPGA_D2 GRN Designed for TI by eInfochips A R206 330E 1 2 DEBUG_LED_1 FPGA_INIT# FPGA_M0 FPGA_M1 FPGA_M2 TMDSEVM6657 B R924 R197 R198 R199 Title FPGA_D3 GRN NU NU NU R207 330E 1 2 DEBUG_LED_2 B 0E 0E 0E 0E FPGA & BM & SMART REFLEX

FPGA_D4 GRN Document Number Rev R208 330E 1 2 DEBUG_LED_3 Size B C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 23of 29

5 4 3 2 1 5 4 3 2 1

1.8V Place near to DSP VCC1V8 DSP1D VCC1V8 VCC1V8 TMS320C6657 VCC1V8 VCC1V8 A24 E21 DVDD18_1 G3 DVDD18_2 T7 G6 DVDD18_3 DVDD18_19 T19 C1176 C1177 C1178 C1706 C1179 C1700 C1708 C1197 C1194 C1184 C1185 C1704 C1707 C1709 C1186 C1187 C1188 C1189 C1190 C1191 C1192 H7 DVDD18_4 DVDD18_20 T24 H19 DVDD18_5 DVDD18_21 U6 100uF 100uF 10uF 10uF 2.2uF 2.2uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 560pF 560pF 560pF 560pF 560pF 560pF 560pF H24 DVDD18_6 DVDD18_22 U20 J6 DVDD18_7 DVDD18_23 V7 K3 DVDD18_8 DVDD18_24 V19 D K7 DVDD18_9 DVDD18_25 W6 D L6 DVDD18_10 DVDD18_26 W14 M7 DVDD18_11 DVDD18_27 W16 N3 DVDD18_12 DVDD18_28 W18 N6 DVDD18_13 DVDD18_29 W20 P7 DVDD18_14 DVDD18_30 Y3 VCC1V8 VCC1V8 R6 DVDD18_15 DVDD18_31 Y13 R20 DVDD18_16 DVDD18_32 Y17 T3 DVDD18_17 DVDD18_33 AB23 DVDD18_18 DVDD18_34 AC16 R364NU 0E G19 DVDD18_35 AC20 C1703 C1180 C1181 C1196 C1213 C1199 C1198 C1183 C1182 C1195 C1702 C1712 C1711 C1710 VCC1V8 R365NU 0E G20 RSV0A DVDD18_36 B132 RSV0B 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 1 3 VCC1V8_AVDD1 Y15 F20 AVDDA1 C1200 C1201 C1205 C1206 C1207 AVDDA2

100uF 4.7uF 100nF 10nF 560pF 2200pF 2

B131 1 3 VCC1V8_AVDD2

C1202 C1203 C1204

100nF 10nF 560pF 2200pF 2

C C 1.5V

VCC1V5 DSP1C VCC1V5 Place near to DSP TMS320C6657

B10 F9 VCC1V5 VCC1V5 VCC1V5 VCC1V5 VCC1V5 C6 DVDD15_1 DVDD15_12 F11 C17 DVDD15_2 DVDD15_13 F13 C21 DVDD15_3 DVDD15_14 F17 D2 DVDD15_4 DVDD15_15 F19 D4 DVDD15_5 DVDD15_16 G8 C1556 C1557 C1558 C1227 C1216 C1217 C1218 C1219 C1560 C1220 C1221 C1222 C1223 C1224 C1705 C1193 C1214 C1212 C1208 C1209 C1210 C1211 D8 DVDD15_6 DVDD15_17 G10 D13 DVDD15_7 DVDD15_18 G12 100uF 100uF 10uF 2.2uF 100nF 100nF 100nF 100nF 100nF 10nF 10nF 10nF 10nF 10nF 1000pF 1000pF 1000pF 1000pF 560pF 560pF 560pF 560pF D15 DVDD15_8 DVDD15_19 G14 D19 DVDD15_9 DVDD15_20 G16 F7 DVDD15_10 DVDD15_21 G18 DVDD15_11 DVDD15_22

0.9V - 1.1V (SMART REFLEX) Place near to DSP B CVDD B CVDD

C1570 C1571 C1266 C1568 C1273 C1272 C1271 C1270 C1269 C1258 C1259 C1260 C1261 C1262 C1263 C1274 C1278 C1279 10uF 10uF 2.2uF 2.2uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

CVDD DSP1A CVDD TMS320C6657

H9 N14 H11 CVDD_1 CVDD_27 N16 H13 CVDD_2 CVDD_28 N18 CVDD H15 CVDD_3 CVDD_29 P9 H17 CVDD_4 CVDD_30 P11 J10 CVDD_5 CVDD_31 P13 J12 CVDD_6 CVDD_32 P15 J14 CVDD_7 CVDD_33 P17 J16 CVDD_8 CVDD_34 P19 C1228 C1229 C1230 C1231 C1232 C1233 C1234 C1235 C1236 C1237 C1238 C1239 C1240 C1241 K11 CVDD_9 CVDD_35 R10 K13 CVDD_10 CVDD_36 R12 560pF 560pF 560pF 560pF 560pF 560pF 560pF 560pF 560pF 560pF 560pF 560pF 560pF 560pF K15 CVDD_11 CVDD_37 R14 L8 CVDD_12 CVDD_38 R16 L10 CVDD_13 CVDD_39 R18 L12 CVDD_14 CVDD_40 T11 L14 CVDD_15 CVDD_41 T13 L16 CVDD_16 CVDD_42 T15 L18 CVDD_17 CVDD_43 U10 M9 CVDD_18 CVDD_44 U12 M11 CVDD_19 CVDD_45 U14 CVDD M13 CVDD_20 CVDD_46 U16 CVDD_21 CVDD_47 Project A M15 V9 Designed for TI by eInfochips A M17 CVDD_22 CVDD_48 V11 TMDSEVM6657 N8 CVDD_23 CVDD_49 V13 N10 CVDD_24 CVDD_50 V15 N12 CVDD_25 CVDD_51 V17 C1255 C1254 C1248 C1249 C1250 C1251 C1252 C1253 C1256 C1257 C1281 C1282 C1286 C1290 CVDD_26 CVDD_52 Title 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF DSP POWER 1

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 24of 29

5 4 3 2 1 5 4 3 2 1

1.0V 1.0V & 1.5V for SERDES

VCC1V0 VDDT1 DSP1E VDDT2 DSP1B Place near to DSP TMS320C6657 VCC1V0 TMS320C6657 VCC1V0 K19 W8 L20 VDDT1_1 VDDT2_1 W10 J8 T9 C1283 C1284 C1280 C1277 C1493 C1267 M19 VDDT1_2 VDDT2_2 W12 J18 CVDD1_1 CVDD1_5 T17 N20 VDDT1_3 VDDT2_3 Y7 D K9 CVDD1_2 CVDD1_6 U8 100nF 100nF 10nF 10nF 1000pF 1000pF VDDT1_4 VDDT2_4 Y9 D K17 CVDD1_3 CVDD1_7 U18 VDDR1 VDDT2_5 Y11 VDDR2 VDDR3 VDDR4 CVDD1_4 CVDD1_8 VDDT2_6 M20 AA9 VDDR1 VDDR2 AA3 VDDR3 AA5 VDDR4

VDDT1 VCC1V0 VDDT2 VCC1V0

B110 B190 1 3 1 3

GROUND C1296 C1297 C1298 C1299 C1300 C1292 C1287 C1291 C1288 C1289 C1294 C1295 4.7uF 4.7uF DSP1F 100nF 10nF 560pF 560pF 2200pF 100nF 100nF 10nF 10nF 560pF 560pF 2200pF TMS320C6657 2 2 A1 P6 A10 VSS_1 VSS_88 P8 A25 VSS_2 VSS_89 P10 B6 VSS_3 VSS_90 P12 B17 VSS_4 VSS_91 P14 C2 VSS_5 VSS_92 P16 C4 VSS_6 VSS_93 P18 C8 VSS_7 VSS_94 P20 VDDR2 VCC1V5 C13 VSS_8 VSS_95 P21 VDDR1 VCC1V5 C15 VSS_9 VSS_96 P23 B128 VSS_10 VSS_97 C C19 P25 B127 1 3 C D21 VSS_11 VSS_98 R7 1 3 E11 VSS_12 VSS_99 R8 F3 VSS_13 VSS_100 R9 C1482 C1484 C1483 C1481 F6 VSS_14 VSS_101 R11 F8 VSS_15 VSS_102 R13 C1478 C1479 C1480 C1477 100nF 10nF 1000pF 560pF 2200pF F10 VSS_16 VSS_103 R15 2200pF 2 F12 VSS_17 VSS_104 R17 100nF 10nF 1000pF 560pF 2 F14 VSS_18 VSS_105 R19 F16 VSS_19 VSS_106 R22 F18 VSS_20 VSS_107 R24 G7 VSS_21 VSS_108 T2 G9 VSS_22 VSS_109 T6 G11 VSS_23 VSS_110 T8 VDDR3 VCC1V5 VDDR4 VCC1V5 G13 VSS_24 VSS_111 T10 G15 VSS_25 VSS_112 T12 B129 B130 G17 VSS_26 VSS_113 T14 1 3 1 3 H6 VSS_27 VSS_114 T16 H8 VSS_28 VSS_115 T18 H10 VSS_29 VSS_116 T20 C1490 C1491 C1492 C1489 H12 VSS_30 VSS_117 U7 C1486 C1488 C1487 C1485 H14 VSS_31 VSS_118 U9 2200pF 100nF 10nF 1000pF 560pF 2200pF H16 VSS_32 VSS_119 U11 100nF 10nF 1000pF 560pF 2 2 H18 VSS_33 VSS_120 U13 H20 VSS_34 VSS_121 U15 H21 VSS_35 VSS_122 U17 H23 VSS_36 VSS_123 U19 H25 VSS_37 VSS_124 V6 J7 VSS_38 VSS_125 V8 J9 VSS_39 VSS_126 V10 J11 VSS_40 VSS_127 V12 J13 VSS_41 VSS_128 V14 J15 VSS_42 VSS_129 V16 J17 VSS_43 VSS_130 V18 J19 VSS_44 VSS_131 V20 J22 VSS_45 VSS_132 W3 J23 VSS_46 VSS_133 W7 J24 VSS_47 VSS_134 W9 B K2 VSS_48 VSS_135 W11 B K6 VSS_49 VSS_136 W13 K8 VSS_50 VSS_137 W15 K10 VSS_51 VSS_138 W17 K12 VSS_52 VSS_139 W19 K14 VSS_53 VSS_140 Y6 K16 VSS_54 VSS_141 Y8 K18 VSS_55 VSS_142 Y10 K20 VSS_56 VSS_143 Y12 K23 VSS_57 VSS_144 Y14 L7 VSS_58 VSS_145 Y16 L9 VSS_59 VSS_146 AA4 L11 VSS_60 VSS_147 AA6 L13 VSS_61 VSS_148 AA8 L15 VSS_62 VSS_149 AA10 L17 VSS_63 VSS_150 AB2 L19 VSS_64 VSS_151 AB6 L21 VSS_65 VSS_152 AB9 L23 VSS_66 VSS_153 AB12 L25 VSS_67 VSS_154 AB20 M6 VSS_68 VSS_155 AB24 M8 VSS_69 VSS_156 AC1 M10 VSS_70 VSS_157 AC4 M12 VSS_71 VSS_158 AC7 M14 VSS_72 VSS_159 AC10 M16 VSS_73 VSS_160 AC13 M18 VSS_74 VSS_161 AD1 M22 VSS_75 VSS_162 AD2 M23 VSS_76 VSS_163 AD3 M24 VSS_77 VSS_164 AD6 N4 VSS_78 VSS_165 AD9 N7 VSS_79 VSS_166 AD12 N9 VSS_80 VSS_167 AD16 N11 VSS_81 VSS_168 AE1 N13 VSS_82 VSS_169 AE4 N15 VSS_83 VSS_170 AE7 N17 VSS_84 VSS_171 AE10 VSS_85 VSS_172 Project A N19 AE13 Designed for TI by eInfochips A N23 VSS_86 VSS_173 AE25 TMDSEVM6657 VSS_87 VSS_174 Title DSP POWER 2

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 25of 29

5 4 3 2 1 5 4 3 2 1

VCC3V3_AUX VCC3V3_AUX SMART REFLEX UCD9222_PG1 R418 10K UCD9222_PG2 R419 10K PMBUS1 R255 R256 R257 R439 TSW-105-07-S-S 2K 2K 100K 10K

VCC12 VCC3V3_AUX V33A_9222 1 PMBUS_CLK 2 PMBUS_DAT R566 2E 3 PMBUS_ALT R250 4 PMBUS_CTL VCC3V3_AUX 1% C607 C370 C372 5

10.2K 4.7uF 100nF 1uF U32 UCD9222RGZR R258 D D R259 C518 R252 6 FF-1A 34 FLT1A 12 PWM-1A 1M 10K 1000pF 33 V33A DPWM1A 13 OUT UCD9222_PG1 [22] PMBUS_RST# 1.5K 41 V33DIO PG1 25 IN UCD9222_ENA1 [22] V33FB ENA1 42 CS1A R416 100E Isense-1A 45 CS1A 1% C443 10nF R376 Vtrack R437 4 R251 22.1K 10K VinMon NU CVDD 8 FF-2A 1% Resistor Calculation for Isense FLT2A 14 PWM-2A 10K R338 10E R261 750E EAP1 37 DPWM2A 15 OUT UCD9222_PG2 [22] Rmon = Vmon/ (Imax x 20 uA/A) C446 560pF EAp1 PG2 26 IN UCD9222_ENA2 [22] Vmon = 12*1.5/(1.5+10.2) = 1.53V VCC1V0 R246 2K ENA2 3 CS2A R417 100E Isense-2A Place next to CS2A UCD9222 R260 10E NU EAN1 38 1% C447 10nF EAn1 R373 22.1K R404 Rmon1 = 1.53*1000/(2.7*20) K R411 10E R405 750E EAP2 39 VCC3V3_AUX 1% 10K = 28.49K C467 560pF EAp2 R262 R415 2K Rmon2 = 1.53*1000/(1.1*20) K R406 10E NU EAN2 40 VCC3V3_AUX = 69.93K EAn2 10K 17 PGUCD9222 [22] 16 PowerGood OUT [18] UCD9222_VIDA IN 18 VID1A 27 9222_TCK R440 10K [18] UCD9222_VIDB IN 21 VID1B JTAG_TCK 29 9222_TDI R452 10K [18] UCD9222_VIDC IN 7 VID1C JTAG_TDI/SYNC_IN 28 9222_TDO R451 10K [18] UCD9222_VIDS IN 22 VID1S JTAG_TDO/SYNC_OUT 30 9222_TMS R441 10K [23] UCD9222_VID2A IN 23 VID2A JTAG_TMS 31 9222_TRST# DSP UCD9222 Reserved for [23] R438 10K UCD9222_VID2B IN 24 VID2B JTAG_TRST PMBus Address Bins EAP1 future use [23] UCD9222_VID2C IN VID2C 10E 750E 9 CVDD EAP1 [23] UCD9222_VID2S IN VID2S 560pF 44 R2531% 100K EAN1 PMBus_ADDR0 10E EAN1 NU 43 R254 100K PMBus Address PMBus RESISTANCE ( K ohm ) GND PMBus_ADDR1 PMBUS Address: R247 0E PMBUS_RST# 5 1% [22] UCD9222_RST# IN RESET 78 (6*12+6) EAP2 10E 750E 10 OPEN -- VCC1V0 EAP2 [22] PMBUS_CLK IN PMBUS_CLK 560pF 11 EAN2 [22] PMBUS_DAT BI PMBUS_DATA 11 205 GND 10E EAN2 [22] 19 32 PMBUS_ALT OUT 20 PMBUS_ALERT DGND3 49 [22] PMBUS_CTL IN PMBUS_CNTRL PowerPad 10 178 C C608 10nF UCD9222_LINMON 1 C IinMon 35 C444 1uF 9 154 46 BPCAP C609 10nF TEMP1_2 2 Temp1/AuxADC1 8 133 Temp2/AuxADC2 36 C445 100nF 48 AGND2 47 7 115 ADC_REF AGND3 Corresponding "EA" Pins MUST be routed as differential signals and connected 6 100 next to DSP for specific rails 5 86.6 Series resistors on EA nets to be placed at the load for proper voltage feedback. 4 75

Provide min 25 thermal vias for IC 3 64.9 2 56.2 - C444 and C372 should be mounted adjacent to UCD9222 and connected without a via 1 48.7 - Components related to Isense pins should be located adjacent to UCD9222 with tightly coupled gnds. 0 42.2 SHORT --

VCC12 VCC12 CVDD/CVDD1

C449 C460 C602 C457 C450 B Each 10nF and 22uF cap needs to be tightly B 25V 25V 10nF 25V 25V coupled to Vin and PGND of the UCD7242. 22uF 10nF 10nF 22uF VCC3V3_AUX TEMP1_2

Q13 U34 30 32 31 19 27 29 28 4 3 UCD9222_LINMON VDD VOUT 1 NC1 5 C448 NC2

VIN_1 VIN_2 VIN_3 VIN_4 C603 TMON 100nF 10nF GND VCC3V3_AUX PWM-2A 1 NC-VIN_1 NC-VIN_2 26 PWM-1A VCC3V3_AUX PWM_B PWM_A MCP9700AT-E/LT R331 10K SRE_B 2 25 SRE_A R454 10K 2 SRE_B SRE_A FF-2A 9 18 FF-1A FLT_B FLT_A

Isense-2A 7 20 Isense-1A IMON_B IMON_A C451 0.22uF 3 24 C452 0.22uF BST_B BST_A CVDD VCC1V0 4 23 BSW_B BSW_A TP18 TP19 L15 2.3uH 13 14 L16 1.2uH SWB SWA - Vin cap, Pgnd connection and Vout bulk caps must all be connected by a continuous copper pour on 1.97A Irms 3.0 Irms CVDD @2.7A outer layer where UCD7242 is mounted. 1.0V@ 1.1A - If these connections are broken into islands, inductance of vias will degrade the performance of R420 C455 C453 C454 C459 C458 C461 C462 R263 power stage resulting in increased ripple 1% 10 15 10uF 47uF 47uF 12 PGND_1 PGND_3 17 100uF 100uF 47uF 47uF 1% 1K 11 PGND_2 PGND_4 16 1K NC-PGND_1 NC-PGND_2 testmode AGND VGG_DIS BP3 VGG

8 6 5 Project

A UCD7242RSJT 21 22 Designed for TI by eInfochips A TMDSEVM6657

C463 C464 Vin = 11.5V to 12.5V Inductor Calculation for CVDD 1uF Fsw = 750kHz Title 4.7uF L= ( 12.5 - 1 ) / (2.7) * (1/12.5) / 750K = 0.46 uH UCD9222RGZR Ref Ind for CVDD = 1.2uH Ref Ind for VCC1V0 = 2.3uH Document Number Rev Inductor Calculation for CVDD1 Size L= ( 12.5 - 1 ) / (1.1) * (1/12.5) / 750K C 16_00132_02 2.9 = 1.11 uH Date: Thursday, November 28, 2013 Sheet 26of 29

5 4 3 2 1 5 4 3 2 1

VCC12 12V to 3.3_AUX Generation

VCC12 VCC3V3_AUX

B165 120_100MHz R350

Over Current TVS C544 C545 C538 VCC12_AMC 25V 25V 25V U36 10K Protection VCC12 TP30 22uF 4.7uF 100nF TPS54620RGYR Voltage BreakDown = 13.3V 4 14 VCC3V3_AUX TP26 OUT VCC3V3_AUX_PG [22] DC_IN1 R374 5 PVIN1 PWRGD 13 C431 100nF 2 F6 RUEF300 1% PVIN2 BOOT 10V D D 1 6 12 L118 2.2uH 3.7A Irms F8 4A 3 31.6K VIN PH2 11 R2106 CT6 PH1 R1573NU 10E C1126 100nF R334 RAPC712X D18 + C549 R483 0E 10 NU 1% C432 C2325 EN 25V Snubber Circuit 10V 25V 3.3V_AUX @ 2.75A 2.2K 100uF 22uF 9 31.6K 22uF 10uF I(hold) = 3A R336 1 SS/TR 7 I(trip) = 6A SMBJ12A 1% RT/CLK VSENSE Trip time= 10.8s D17 C438 R332 2 10K 16V 1% 3 GND1 R335 10nF 15 GND2 8 1% 53.6K EPAD COMP LED R333 10K Vin = 11.5V to 12.5V 1% Fsw = 900kHz 2K

C32

10nF

Lmin = ((12.5 - 3.3)/(3 * 0.3) * (3.3 / (12.5 * 900kHz)) Ref Ind = 2.2uH = 2.96uH Ref Cap = 32uF Rrt = 48000 x 900^(-0.997) - 2 Co_min = (2*1) / (900kHz*0.0825) = 53.6K = 2.69uF

12V to 5V Generation

C C

Snubber Circuit

R1182NU 10E C1129 100nF VCC12 U29 NU VCC5 TP25 VCC5 VCC3V3_AUX TPS54231D 10V 1 C420 100nF B158 120_100MHz 2 BOOT 8 L2 22uH 2.2A Irms F9 1A R143 3 VIN PH U253 R136 C423 C426 4 EN 5 2 D7 C422 C1437 SN74LVC1G07DBVR SS VSENSE 25V 25V R237 10V 25V R238 5V @ 0.8A 1K 1 VCC 5 10uF 100nF NU 6 22uF 10uF 1% 2 10K C428 COMP 7 B340A-13-F 3 4 GND 1 OUT VCC5_PG [22] 33K 16V 10K GND 10nF C424

R2009 0E 1200pF [22] VCC_5V_EN IN Vin = 11.5V to 12.5V R239 C427 R240 Fsw = 570kHz 1% R241 56pF 1% Lmin = ((12.5 - 5)/(0.8 * 0.3) * (5 / (12.5 * 570kHz)) 22.6K Ref Ind = 22uH = 21.87uH 10K 1.87K Ref Cap = 32uF Co_min = 1/( 2 * 3.14 * (5/0.8)* 570kHz) = 44.7nF

B B 12V to 1.5V Generation XDS560 v2 Mezzanine Power VCC3V3_AUX

R314 VCC5 VCC12 VCC3V3_AUX U30 10K TPS54620RGYR B164 120_100MHz 4 14 VCC1V5 TP27 OUT VCC1V5_PG [22] 5 PVIN1 PWRGD 13 C429 100nF 10V C551 C553 C542 C541 C529 PVIN2 BOOT C537 C536 25V 25V 25V 6 12 L3 1.2uH 2.3A Irms F7 3A 10uF 100nF 100nF 10uF 22uF 4.7uF 100nF VIN PH2 11 PH1 R1181NU 10E C1127 100nF R243 560V2_PWR1 10 NU 1% C430 C539 1.5V @ 2A TSW-104-14-F-D EN Snubber Circuit 10V 6.3V 1 2 VCC3V3_AUX 9 9.09K 22uF 100uF 3 4 [22] 1 SS/TR 7 XDS560_IL IN 5 6 [22] VCC1V5_EN IN RT/CLK VSENSE 7 8 R242 2 R245 R375 C433 1% 3 GND1 1% 16V 15 GND2 8 10nF 53.6K EPAD COMP 10K 10K R244 Vin = 11.5V to 12.5V 1% Fsw = 900KHz 1.69K

C434

8200pF Project A Designed for TI by eInfochips A TMDSEVM6657 Title POWER SUPPLY 1 Rrt = 48000 x 900^(-0.997) - 2 = 53.6K Lmin = ((12.5 - 1.5)/(2 * 0.3)) * (1.5 / (12.5*900kHz)) Ref Ind = 1.2uH = 2.44uH Document Number Rev Ref Cap = 122uF Size Co_min = (2*1)/(900kHz*0.075) C 16_00132_02 2.9 = 29.62uF Date: Thursday, November 28, 2013 Sheet 27of 29

5 4 3 2 1 5 4 3 2 1

3.3V_AUX to 1.2V Generation 3.3V_AUX to 1.8V_AUX Generation

VCC3V3_AUX VCC1V8_AUX Q3 VCC1V2 TP28 TPS73701DRBT VCC3V3_AUX Q2 8 1 R2227 0E TP22 TPS73701DRBT VIN VOUT 8 1 R3226 0E VIN VOUT C397 C548 R25 10K 5 3 R222 C514 C515 1.8V_AUX @ 0.31A R221 C507 C506 2 EN FB 7 1% D D C395 C513 R21 10K 5 3 1.2V @ 0.6A 10uF 100nF 4 NC1 NC3 6 10uF 100nF 2 EN FB 7 R1 10uF 100nF 9 GND NC2 28K R1 10uF 100nF 4 NC1 NC3 6 0E EPAD 9 GND NC2 EPAD R223 1% R2 R224 1% 10K 56.2K R2

Vout = (R1+R2)/R2*1.204 Vout = (R1+R2)/R2*1.204 = (0+10k)/10k*1.204 = (28k+56.2k)/56.2k*1.204 = 1.204V = 1.804V

3.3V_AUX to 2.5V Generation 3.3V_AUX to 1.8V Generation

VCC3V3_AUX TP20 VCC2V5 C Q4 C TPS73701DRBT VCC3V3_AUX VCC1V8 8 1 R2228 0E Q5 VIN VOUT TPS73701DRBT 8 1 R2229 0E TP21 C399 C547 5 3 C509 C508 2.5V @ 0.35A VIN VOUT 2 EN FB 7 R225 C398 C554 10uF 100nF 4 NC1 NC3 6 1% 10uF 100nF 5 3 R385 C517 C523 9 GND NC2 10uF 100nF 2 EN FB 7 1% 1.8V @ 0.14A EPAD 39.2K 4 NC1 NC3 6 10uF 100nF R1 9 GND NC2 28K R1 EPAD

[22] VCC2V5_EN IN R386

R22 R227 [22] VCC1V8_EN1 IN 1% 1% 56.2K R2 10K 36.5K R2 R141

10K

Vout = (R1+R2)/R2*1.204 = (39.2k+36.5k)/36.5k*1.204 = 2.50V Vout = (R1+R2)/R2*1.204 = (28k+56.2k)/56.2k*1.204 = 1.804V VCC3V3_AUX

VCC2V5 U251 R75 SN74LVC1G07DBVR 1 VCC 5 R142 1K 2 10K B 3 4 B [22] GND OUT VCC2V5_PG

1.8V Superviser Circuit

3.3V_AUX to 0.75V Generation VCC3V3_AUX VCC1V8_AUX TP31 TP32 TP33 TP34

VCC1V8 R2231 C2556 U1131 TPS3808G18DBVR 100nF 4.7K 5 6 SENSE VDD VCC3V3_AUX 3 1 MR# RESET# OUT VCC1V8_PG [18,22] VCC3V3_AUX 4 2 CT GND 20 mil trace width C510 C2557 R230 Vth = 1.67V 100nF U27 100nF [14,15] DSP_VREFSSTL IN TPS51200DRCT C403 10 10K VCC0V75 TP24 VIN 9 [22] 10nF 1 PGOOD OUT VCC0V75_PG VCC1V5 REFIN 3 R2230 0E VO 2 4 C407 C408 C409 7 VLDOIN PGND [22] VCC0V75_EN IN C405 C406 EN 5 10uF 10uF 10uF 0.75V @ 0.16A 6 VOSNS REFOUT Project A 10uF 100nF R23 Designed for TI by eInfochips A C410 8 11 TMDSEVM6657 GND EPAD 10K 100nF Title POWER SUPPLY 2

Size Document Number Rev C 16_00132_02 2.9

Date: Thursday, November 28, 2013 Sheet 28of 29

5 4 3 2 1 5 4 3 2 1 TMDSEVM6657 - REVISION HISTORY

PCB REV.SCH. REV. CHANGE DESCRIPTION DATE AUTHOR

0.6 - CLK3 removed - Series Termination removed from GPIO0 to GPIO13 lines 3-FEB-2012 eInfochips 1.0

D D 1.1 - D9 and D10 part changed with one with higher current capacity. - R134 changed to 1K from 4.7K 20-MAR-2012 eInfochips - NU resistors R433 and R434 changed to 10K and 1.2K resp. They are to be mounted. - R12 and R17 replaced by 100nF caps C1225 and C1226 - R70 and R71 mounting status changed from NU to populated. - U6 (DDR3 ECC chip) made NU. - DDR3 Clock frequency from Clock Gen changed to 50 MHz (software change only).

- Clock buffer U1132 removed. 2 OR gates (U268, U269) and the corresponding circuitry to buffer EMU_TCK added. 02-APR-2012 eInfochips 0.1 - 4 Test Points for Gnd added. 2.0 - ETH_SCK net renamed to ETH_SDA - SIGDETunconnected with LOS; its directly pulled high. R145 and R146 removed - SYSPG_D1 LED changed to Yellow colour from Green

- 10 nF capacitors (C457 and C460) added on VCC12 input rail of U34. - Capacitors on CVDD rail optimized from two 220uF, two 100uF and four 47uF to two 100uF and two 47uF. - Capacitors on VCC1V0 rail optimized from one 220uF, three 47uF and one 10uF to two 47uF and one 10uF. 02-MAY-2012 eInfochips 0.2 - An additional 22uF cap (C549) added on VCC12 input for U29. C426 changed from 10nF to 100nF. - R183 changed to 1K from 4.7K.

C - SIGDET connected to VCC2V5 using R146. C - R1273 changed to 4.7K from 10K.

- L15 and L16 changed to 2.3uH and 1.2uH respectively - R251 and R373 changed to 22.1K - C549 moved before B158 on 12V plane 07-MAY-2012 eInfochips 0.3 - C2325 changed from 100nF to 10uF - R2203 made NU and R2226 to be mounted

0.4 - NOR Flash density label corrected to 32 Mb from 16MB. 20-JUL-2012 eInfochips

0.5 - DISCLAIMER Changed 26-JUL-2012 eInfochips

- Asthetical Change 06-DEC-2012 eInfochips 0.6 Name swap between LVDS and HCSL on page 18

0.7 - Asthetical Change Note for DDR3 Slew-Rate setting corrected on page 14 29-JAN-2013 eInfochips

0.8 - R82 and R83 changed to 10K 22-FEB-2013 eInfochips - R85 and R957 made NU B B 0.9 - The Resistors R896,R67 and capacitor C555 are redundant components on EMU_TCK and can be NU from design. - Pull-up resister R1119 on EMU_TCK change from 10K to 4.7K 28-NOV-2013 eInfochips

Dummy Components DM16 DM17 DM1 STC02SYAN STC02SYAN DM6 DM7 DM8 DM9 AS300-120-AQ250-E0902 DM2 DM3 DM4 AMC Hole

H5 Shorting Link Shorting Link Power Adaptor Board Screw Board Screw Board Screw Board Screw LAN cable Heat-Sink UART Custom Cable DM19 DM18 1 STC02SYAN STC02SYAN DM10 DM11 DM12 DM13 DM5 DM14 DM15 H27P35-MTH

Shorting Link Shorting Link Board Stud Board Stud Board Stud Board Stud USB miniB cable Universal Travel Adaptor US AC Mains Cable Project A Designed for TI by eInfochips A TMDSEVM6657 BRK1 Mounting Holes SOCKET_CSBGA625 On Board Fiducials NU H1 H2 Title 1 1 FM1 FM2 REVISION HISTORY H35-NPTH H35-NPTH Fiducial Fiducial Size Document Number Rev H4 H3 FM3 FM4 C 16_00132_02 2.9 1 1 H35-NPTH H35-NPTH Fiducial Fiducial Date: Thursday, November 28, 2013 Sheet 29of 29

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