A Pseudo-PMOS Logic for Realizing Wide Fan-In NAND Gates by Sherif M

Global Journal of Researches in Engineering: F Electrical and Electronics Engineering Volume 17 Issue 7 Version 1.0 Year 2017 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals Inc. (USA) Online ISSN: 2249-4596 & Print ISSN: 0975-5861

A Pseudo-PMOS Logic for Realizing Wide Fan-in NAND Gates By Sherif M. Sharroush Port Said University Abstract- Wide fan-in logic gates when implemented in static complementary CMOS logic consume a significant area overhead, consume a large power consumption, and have a large propagation delay. In this paper, a pseudo-PMOS logic is presented for the realization of wide fan-in NAND gates in a manner similar to the realization of wide fan-in NOR gates using the pseudo-NMOS logic. The circuit design issues of this family are discussed. Also, it is compared with the conventional CMOS logic from the points of view of the area, the average propagation delay, the average power consumption, and the logic swing using a proper figure of merit. The effects of technology scaling and process variations on this family are investigated. Simulation results verify the enhancement in performance in which the 45 nm CMOS technology is adopted.

Keywords: area, energy-delay product, power consumption, power-delay product, propagation delay, pseudo-PMOS logic, wide fan-in. GJRE-F Classification: FOR Code: 090699

APseudoPMOSLogicforRealizingWideFaninNANDGates

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© 2017. Sherif M. Sharroush. This is a research/review paper, distributed under the terms of the Creative Commons Attribution- Noncommercial 3.0 Unported License http://creativecommons.org/licenses/by-nc/3.0/), permitting all non commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

A Pseudo-PMOS Logic for Realizing Wide Fan-in NAND Gates

Sherif M. Sharroush

Abstract- Wide fan-in logic gates when implemented in static the long chain of the PMOS transistors is substituted by complementary CMOS logic consume a significant area an always-activated PMOS transistor. In this paper, the overhead, consume a large power consumption, and have a pseudo-PMOS logic-circuit family is adopted in a similar large propagation delay. In this paper, a pseudo-PMOS logic is manner in realizing wide fan-in NAND gates in which the presented for the realization of wide fan-in NAND gates in a long chain of the NMOS transistors is substituted by an manner similar to the realization of wide fan-in NOR gates using 201 the pseudo-NMOS logic. The circuit design issues of this always-activated NMOS transistor. The performance of

family are discussed. Also, it is compared with the this family is investigated and compared with the Year

conventional CMOS logic. The remainder of this paper is conventional CMOS logic from the points of view of the area, the average propagation delay, the average power organized as follows: A survey of the previous work 1 consumption, and the logic swing using a proper figure of related to the problem at hand is presented in Section II. merit. The effects of technology scaling and process variations The pseudo-PMOS logic is presented qualitatively in on this family are investigated. Simulation results verify the Section III. The circuit design issues and the comparison I ion enhancement in performance in which the 45 nm CMOS of this family with the conventional static CMOS technology is adopted. realization are presented quantitatively in Section IV. The Keywords: area, energy-delay product, power effects of the technology scaling and the process consumption, power-delay product, propagation delay, variations on this family are discussed in Sections V and pseudo-PMOS logic, wide fan-in. VI, respectively. The enhancement in performance is I. INTRODUCTION verified by simulation in Section VII. Finally, the paper is concluded in Section VIII. OS circuits that can be implemented using the universal NAND or NOR gates may contain a VDD large number of serially connected NMOS or M VII Vers olume XVII Issue

PMOS transistors if the fan-in is wide. Refer to Fig. 1 for V such a wide fan-in logic circuit with n inputs realized in An A2 A1 )

Qn Q2 Q1 CMOS logic. The main problem associated with such ( circuits is the large propagation delay. This is due to the large RC time constant associated with charging or C 1 A discharging the parasitic capacitances at the output 1 M1 node as well as the parasitic capacitances at the internal nodes. Also, the current-driving capability of the C A M 2 transistors degrades due to the reduction of their 2 2 effective-gate voltages and their drain-to-source voltages in addition to the threshold-voltage increase C 3 due to the body effect. To make the matter worse, such Researches in Engineering gates when realized in logic-circuit families such as domino CMOS and pseudo NMOS suffer from the contention current, thus requiring a large area for the pull-down network (PDN) in order to have an acceptable noise margin and speed. Multi-input exclusive-OR gates C n-1 A M that are required in applications such as parity-check n-1 n-1 of Journal lobal and error-correction circuits or some built-in testing G circuits and barrel-shifters [1] are types of applications C n An M that may include wide fan-in gates. n For realizing wide fan-in NOR gates, it is better to use the pseudo -NMOS logic -circuit family in which

Fig. 1: An n-input NAND gate using the static Author: Dept. of Electrical Engineering, Fac. of Engineering, Port Said, complementary CMOS logic circuit family with the Port Said Univ., Egypt. e-mail: [email protected] internal capacitances indicated.

II. PREVIOUS WORK order to obtain the inputs of the circuit at nearly the same instant. A. A George et al. achieved a better noise In this section, a review on some of the previous immunity and a reduced leakage current without any techniques for enhancing the performance of wide fan-in degradation in speed for wide fan-in domino gates by gates is presented. M. M. Khellah et al. [2] proposed a comparing the worst-case leakage current of the pull-up technique to lower both the dynamic-switching power network (PUN) with a mirrored version of this current [9]. consumption and the time delay of wide fan-in dynamic F. Moradi et al. proposed a technique that acts gates. This technique depends on generating a low to enhance the performance of wide fan-in domino

swing signal at the output node by charging and gates by employing a footer transistor that is initially off discharging a small dummy capacitor. By virtue of the in the evaluation phase, thus reducing leakage [10]. principle of charge sharing, a small swing is created on Also, his proposed scheme reduces the contention the gate output; finally, this swing is amplified to full rail betwe en the keeper transistor and the PDN during the

using a suitable sense amplifier. Several techniques for evaluation phase. K. Rajasri et al proposed a 256-bit

reducing the power consumption of wide fan-in gates comparator by adopting a novel technique called 201 can be found in [3, 4, and 5]. Lowering the power current-comparison domino circuit, thus reducing both consumption by reordering schemes is usually the time delay and the leakage-power consumption Year associated with a delay penalty as reordering is usually [11]. Anamika et al. adopted the stacking effect to

associated with a movement of the inputs that arrive 2 reduce the leakage-power consumption for wide fan-in lately farther away from the gate output. circuits [12]. A novel conditional isolation technique for Finally, the reader is referred to [13 and 14] for

ion I ion reducing the evaluation time of wide fan-in domino gates was proposed by W. H. Chiu et al. [6]. This techniques that depend on novel circuits having the technique also reduces both the subthreshold and the same output as the conventional wide fan-in circuit but gate-oxide leakage currents simultaneously. According with improved performance. In the next section, the to [6], reductions on total static power by 36%, dynamic pseudo-PMOS logic is presented. power by 49.14%, and delay time by 60.27% compared to the conventional domino gate can be achieved. H. III. THE PSEUDO-PMOS LOGIC-CIRCUIT Mostafa et al. proposed adopting novel negative- FAMILY capacitance circuits in order to reduce the delay variability under process variations [7]. According to this The idea of the pseudo-PMOS logic is simply as technique, the timing yield was improved from 50% to follows: It is well known from DeMorgan’s law that

olume XVII Issue VII Vers olume XVII Issue 100% for a 64-input wide dynamic OR gate at the V

) expense of an excess power overhead. ++= + (1) 21 .... n 1 AAAAA 2 ...... An

( In [8], K. Mohanram et al. proposed the reordering of the inputs exploiting the symmetry of the That is, logic “0” is obtained at the output of a circuit with respect to their inputs in order to minimize circuit if all the inputs are at logic “1” and logic “1” is

the switching activity and hence the power obtained at the output if any of the inputs is at logic “0.”

consumption. An average reduction of 16% was This can be implemented as well known by the series achieved in power consumption using this scheme. This connection of NMOS transistors in the PDN and the technique allows for a tradeoff between the complexity parallel connection of PMOS transistors in the PUN. of the computation and the quality of the final output. However, the right-hand side of Eq. (1) can be Also, in order to reduce the glitching-power implemented simply using a parallel connection of consumption, an extra dimension is added to the PMOS transistors in the PUN. Now, refer to Fig. 2 for Researches in Engineering complexity of the problem (specifically, the pipelining) in illustration of the pseudo-PMOS logic with n inputs.

VDD

lobal Journal of Journal lobal ...... G MPn MP2 MP1 An A2 A1

V out

M N VB

Fig. 2: The pseudo-PMOS logic for realizing wide fan-in NAND gates.

V DD swing at the output and to reduce the rise and fall times of the output waveform. This in turn reduces the short- circuit power consumption in the driven stages. If the ...... MPn MP2 MP1 previously mentioned parameters are properly chosen, An A2 A1 V then the voltage at the input of the first inverter, V , will out CL VCL be relatively high (larger than the threshold voltage of

M the first inverter, Vthinv1) in case only one input is N VB CL Cout Cout deactivated. If more than one input is deactivated, then more than one PMOS device will be activated with the result that the equivalent resistance of the upper part of Fig. 3: The pseudo-PMOS logic with the use of two the voltage divider decreases. The result is that the cascaded inverters. voltage at the input of the first inverter becomes larger

If at least one of the inputs is deactivated, then than that of the previous case and also the output voltage becomes at logic “1.” The price paid, however, the corresponding PMOS transistor will conduct. Due to 201 the continuous conduction of the NMOS transistor, M , is the dc current drawn through the first inverter, the N there is a voltage division between these two devices. short-circuit power consumption of the two inverters, Year

and the additional propagation delays of the two added The equivalent resistance of MN can be adjusted by inverters. Also, the change of VCL with respect to the 3 properly choosing the biasing voltage, VB, or adjusting threshold voltage of the first inverter due to the process its strength through the aspect ratio, (W/L)n, or the variations affects the reliability of the scheme; a point threshold voltage, Vthn. on I i Now, if all the inputs are activated, all the PMOS that is returned to in Section VI. Throughout this paper, devices will be deactivated. Thus, the parasitic the scheme of Fig. 3 is adopted unless otherwise capacitance at the output node is discharged with no specified. Note also that in order to inhibit the large contention from the PMOS parallel network and the power consumption in the standby state due to the output is at logic “0” as it must be. The main advantage continuous current drawn from VDD to ground, the signal, of the pseudo-PMOS logic is that increasing the number VB, must be connected to the standby signal. Thus, the of the inputs merely increases the parasitic capacitance path from VDD to ground becomes open during the at the output node, thus not affecting the performance standby interval. of this family significantly. On the other hand, increasing Two important notes are in order here. The first the number of the inputs in the CMOS logic has a one is that the pseudo-PMOS logic family can be used significantly deleterious effect on its performance; a in realizing any logic circuit with series or parallel point that was discussed in the preceding section and is connections in the PUNs or PDNs. In this case, the PUN VII Vers Volume XVII Issue

returned to in Section IV. is the same as that of the conventional CMOS logic. The () Instead of the application of a different biasing pseudo- PMOS logic is obviously not suitable for voltage, VB, a voltage equal to the adopted power realizing logic circuits containing serially connected supply, V , can be applied with either increasing the PMOS transistors in their PUNs as it requires a DD threshold voltage of MN or lowering its aspect ratio to significant area overhead. The second note is that the obtain a larger equivalent resistance at the lower arm of quantitative analysis of the next section can be applied the voltage divider. Lowering the aspect ratio can be equally well to the pseudo-NMOS logic after substituting implemented by connecting multi transistors in series as the acronyms associated with the NMOS devices by the aspect ratio of the transistor equivalent to n serially those of the PMOS ones and vice versa. connected transistors each with aspect ratio (W/L) is

V Researches in Engineering (W/nL) [15]. This is done in order to avoid the need to DD generate a separate voltage. An important note that is worth mentioning here is the proper choice of the M threshold voltage of MN, Vthn. Increa sing this voltage, P although certainly slows down the discharging process VCL Vout of CL, makes the equivalent resistance of MN larger.

Thus, the output voltage resulting from the voltage of Journal Global division is larger with the result that the output-high level M N VB CL Cout Cout and consequently the logic swing is larger. Also, the low-to-high transition is faster. These contradictions are returned to in Sections IV and VII. In order to resolve this contradiction, the scheme of Fig. 3 can be used in which two cascaded Fig. 4: The circuit schematic representing the worst-case inverters were added. The benefits gained from adding scenario these two inverters are to obtain a rail-to-tail voltage

IV. CIRCUIT DESIGN ISSUES Alternatively, each of the NMOS and PMOS

devices, M and M , can be replaced by its equivalent In this section, the circuit design issues of the N P resistance. The equivalent resistance, R , of M in the pseudo-PMOS logic are discussed quantitatively from MP P deep-triode region is [17] six aspects. The first one is the proper choice of the

strength of the NMOS transistor, M , and the threshold 1 1 N = = RMP (4) voltage of the first inverter, Vthinv1 (if used). The second, ' W  ' W  k p   ( SG − thp ) kVV p   ( DD − VV thp ) third, fourth, and fifth aspects concern the comparisons  L  p  L  p

between the pseudo-PMOS logic and the conventional However, the equivalent resistance of M , let it be R , CMOS logic from the points of view of the area, the N MN can be written as the ratio between the average drain-to - average propagation delay, the average power source voltage and the average drain current, thus consumption, and the logic swing. Finally, a figure of

merit that includes these metrics is defined and adopted 1 ()V + 0 CL1 V in comparing the performance of the pseudo-PMOS 2 CL1 RMN = = (5) 1 1 ' W  2  1 ' W  2 201 ( ) ( +− λ ) logic and conventional CMOS logic.  kn   ()()B VV thn 1 λnVCL1 ++− 0 kn   B VV thn 1 nVCL1 2 2 L  2  L n   n 

Year a) The Proper Choice of the Strength of the NMOS

The voltage, V , can be found simply from the Transistor CL1

4 In determining the proper range for the values voltage division between RMN and RMP as follows:

of Vthinv1, (W/L)n, Vthn, and VB, we adopt the worst-case scenario. The worst-case scenario is the assumption of MN VR DD (6) VCL1 = ion I ion + only one deactivated input because it represents the MN RR MP rs minimum strength for the PMOS parallel combination After substituting by R and R into Eq. (6), and thus the highest equivalent resistance. If the MN MP the expression for V can be obtained. Now, putting pseudo-PMOS logic operates properly under this CL1 V larger than V results in the following inequality condition, it can be ensured to operate properly for all CL1 thinv1 (from which the strength of the NMOS device can be possible input combinations. determined): Refer now to Fig. 4 for this scenario. M N operates in the saturation region for typical values of the W  1 W  2 k '   ()VV V −− k '   ()−VV adopted NMOS-transistor parameters in the worst case p  L  DD thp DD 2 n  L  B thn p n > V (7) just described. Since V , the final steady-state voltage thinv1 CL1 1 ' W  2 ' W  kn   ()B thn λ +− kVV pn   ()DD − VV thp across CL (the parasitic capacitance at the input of the 2  L   L  n p Volume XVII Issue VII VeVolume XVII Issue first inverter), is chosen to be larger than Vthinv1, it is

expected to be larger than VDD/2. Thus, for the typical Vthinv1 in turn can be evaluated from [17]

() values of the PMOS-transistor parameters, MP is ' W  expected to operate in the triode region as its VD (drain k p    L  p1 voltage) is larger than its VG + |Vthp|, where VG and Vthp [ DD thp1 || ]+− VVV thn1 ' W  are the gate and threshold voltages of MP, respectively. kn    L n1 If the PMOS device is assumed to operate in the deep- Vthinv1 = (8) ' W  triode region, then after equating the currents of the k p    L  1+ p1 NMOS and PMOS devices in which the Shichman - W  k '   Hodges square-law MOSFET model is adopted [16], we n  L n1 obtain

Researches in Engineering where (W/L)n1, (W/L)p1, Vthn1, and Vthp1 are the aspect ratios 1 W  2 W  k '   ()()V V 1+− λ = kV '   ()− ()−VVVV (2) and the threshold voltages of the constituting NMOS and

of n B thn n CL1 p DD thp DD CL1 2  L n  L  p PMOS transistors of the first inverter, respectively. Before leaving this subsection, an important where k ’, (W/L) , and V are the process- n n thn note follows: It is obvious from the qualitative discussion transconductance parameter, the aspect ratio, and the of the pseudo-PMOS logic that increasing the strength threshold voltage of NMOS devices, and kp’, (W/L)p, and of the NMOS device, MN, causes the low-to-high and the Global Journal Global V are their PMOS counterparts. λ is the channel- thp n high-to-low propagation delays to increase and length modulation effect parameter of NMOS devices. decrease, respectively, i.e. to change in opposite After simple mathematical manipulations, we readily directions. Thus, it can be concluded that there is an obtain optimum value for the parameters determining this

W  1 W  2 strength such as the threshold voltage and the aspect k '   ()VV V −− k '   ()−VV p DD thp DD n B thn  L  p 2  L n (3) ratio at which the average propagation delay is at its VCL1 = 1 ' W  2 ' W  minimum. This is really the case and this point is kn   ()B thn λ +− kVV pn   ()DD − VV thp 2  L n  L  p confirmed in Subsection C.

©2017 Global Journals Inc. (US) A Pseudo-PMOS Logic for Realizing Wide Fan-in NAND Gates b) The Area Comparison where t and t are the low-to-high and the high-to- PLHp PHLp In comparing the areas of the pseudo-PMOS low propagation delays according to the pseudo-PMOS logic with the CMOS logic, we adopt the approximation logic, respectively. To determine tPLHp, refer to the circuit that the area of a certain transistor is equal to its channel shown in Fig. 4. This circuit represents the worst case area [17]. Adopting the convention that the size of the from the point of view of the delay also as the charging

PMOS transistor is twice that of the NMOS one in order current of CL is the smallest one and thus the estimated to compensate for the mobility difference and that each value of tPLHp is the largest one. The time delay, tPLHp, of the n NMOS transistors in the series connection has contains there subcomponents, tPLHp1, tPLHp2, and tPLHp3, an aspect ratio of n in order to compensate for the respectively. These are the time delays required to degradation in delay [17], then the areas of the precharge CL to a certain steady-state value that

conventional and the proposed logic-circuit families, Ac depends on the relative strengths of the activated PMOS and A , can be approximated by device and the always activated NMOS device, the high- p to-low propagation delay of the first inverter, and the 2

A WL n += 2n low-to-high propagation delay of the second inverter, 201 c ( ) (9) respectively. The first subcomponent can be

approximated by [17] Year () nA += 72 WL (10) p

-13 5 x 10 C ∆V 1.8 t = L CL conventional CMOS PLHp 1 (12) 1.6 i proposed scheme chavg

1.4 I ion rs 1.2 where ΔVCL is the voltage change of VCL and ichavg is the 1 average charging current of CL. To determine CL, we 0.8 adop t the assumption that the aspect ratio of the PMOS 0.6 device is twice that of the NMOS one in order to

0.4 compensate for the difference in their mobilities and

oximated areas ofoximated the conventional areas CMOS assume that the parasitic capacitance associated with r 0.2 each terminal of the minimum-sized NMOS transistor is 0

logic and the proposed scheme, Ac and Ap, in m2. in Ap, and Ac scheme, proposed the and logic 1 2 3 4 5 6 7 8 The app The The number of the inputs, n. C [18], then CL can be approximated as

Fig. 5: The plots of the approximated areas of the CMOS  W   ++=   logic and the pseudo-PMOS logic versus the number of L  23 nC C (13) VII VeVolume XVII Issue

  L n  the inputs. where (W/L) is the aspect ratio of M . V is equal to () The plots of A and A versus n for W = L = 45 n N Δ CL c p 0.5V (adopting the 50% criterion) and i can be nm are shown in Fig. 5. It can be concluded from this CL1 chavg found from rough estimation of the area that the area overhead of the two-cascaded inverters is justified when the number chavg MPavg −= iii MNavg , (14) of the inputs exceeds 2. Had we adopted the version of Fig. 2 for the pseudo-PMOS logic, the area of this family wher e iMPavg and iMNavg are the average currents of MP and would have been smaller than that of the CMOS logic for MN, respectively. The last two currents can be found as all values of n. follows: c) The Average Propagation-Delay Comparison Researches in Engineering i ()()0 += = VatViatV

The average propagation delay according to the MP CL MP CL CL1 of i = (15) pseudo-PMOS logic is defined as MPavg 2 PLHp + tt PHLp t = (11) pavgp 2 Global Journal Global

1 1 W  2 W   1 2  ∴i =  k '   ()VV ()1 λ V ++− k '   ()V − () ()−−− VVVVV  (16) MPavg 2 2 p  L  DD thp p DD p  L   DD thp DD CL1 2 DD CL1   p p  iMNavg is given by

i MN ()()CL = 0 + MN CL = VatViatV CL1 i = (17) MNavg 2

Substituting by these two currents into Eqs. (12) 1 ' W  2 =∴ ki   ()()VV 1+− λ V . (18) and (14) results in MNavg 4 n  L  B thn n CL1 n

     W  23 n ++   ( 5.0 VC CL1 )   L      n  t PLHp1 = (19)   1 1  W  2  W   1  1  W   '     '     2  '   2  k p   V DD − Vthp  (1+ λ pV DD )+ k p   V DD − Vthp (V DD VCL1 )−− (V DD −VCL1 )  − k n   ()(VB −Vthn 1+ λ nVCL1 ) 2 2  L     L    2  4  L   p p  n

The other two subcomponents are given by 1 W  2 =∴ ki '   ()()VV 1+− λ V (26) disavg 4 n  L  B thn n CL1 ∆ n VC outout tPLHp2 = (20) iavg So, tPHLp1 is given by

201

where C , V , and iavg are the parasitic capacitance 2CLVCL1 Year out out tPHLp1 = (27)

  at the output of the first inverter, the voltage at the output ' W k   ()()V V 2 1+− λ V 6 of the first inverter, and the average discharging current n  B thn n CL1  L n of C , respectively. Keeping in mind that the logic “1” out tPHLp2 and tPHLp3 were estimimted in [17] and were found ion I ion feeding the first inverter is VCL1, then rs to be respectively.

1  W  i = k'   (V −V )2(1+ λ V )    avg n  CL thn11 n DD 2C Vthp 1 DD − 43 VV thp 4  L  (21) out    n1 tPHLp2 = + ln (28) ' W   − 2  V  DD VV thp  DD  k p   ()DD − VV thp   and are equal to 6C and V , respectively. So,  L  p Cout Vout DD and 6CVDD tPLHp2 = (22) 1 ' W  2 2C   − 43  kn   ()()CL1 VV thn 1+− λnVDD out Vthn 1 DD VV thn tPHLp3 =  + ln  4  L n   (29) ' W   DD −VV thn 2  VDD  kn   ()DD −VV thn  L n tPHLp3 is given by [17]

Volume XVII Issue VII VeVolume XVII Issue As discussed in Subsection A and illustrated in  V  −  2C thp 43 VV Figs. 6 and 7, there is an optimum value for the aspect out  1  DD thp  () t = + ln  PLHp3 W    (23) ratio and the threshold voltage of M at which t is at '  DD − VV thp 2 VDD  N pavgp k p   ()DD − VV thp     L  p its minimum . Figs. 6 and 7 show the plots of the average propagation delay of the pseudo-PMOS logic versus the

Cout is the parasitic capacitance at the output of aspect ratio and the threshold voltage of MN, the second inverter and is given by 3C + Cfan, where Cfan respectively, according to the scheme of Fig. 3 with Vthn is the parasitic capacitance due to the fan-out. = 0.25 V, Vthp = -0.32 V, VDD = 0.8 V, and C = 1 fF. As Now, tPHLp contains three subcomponents also; shown in these two figures, the optimum average

tPHLp1, tPHLp2, and tPHLp3 which are the time delays required propagation delay occurs at (W/L)n and Vthn equal to 5.2 to discharge C from V to 0 V, the low-to-high and 0.58 V, respectively. L CL1

Researches in Engineering -10 propagation delay of the first inverter, and the high-to- x 10

low propagation delay of the second inverter, 7 of respectively. t can be found from PHLp1 6

5 on delay of L ∆VC CL i tPHLp1 = (24) 4 i

disavg propagat 3 Global Journal Global age

where idisavg is the average discharging current through 2 aver e h the proposed scheme in Seconds. in scheme proposed the MN and is given by T 1

0 3 3.5 4 4.5 5 5.5 6 += = The aspect ratio of the NMOS transistor, MN. i MN ()()VCL CL1 MN atViVat CL 0 i = (25) disavg 2 Fig. 6: The plot of the average propagation delay of the pseudo-PMOS logic versus the aspect ratio of MN, (W/L)n.

-9 x 10 7 and

6 α p RP = (32) 5 W ()L p 4 respectively, where αn and αp are process-dependent propagation delay of 3 parameters for the NMOS and PMOS devices, age 2 respectively. Simulation results reveal that the best the proposed scheme in Seconds. in scheme proposed the The aver The 1 estimates for αn and αp are 2.5 Ωk and 18 kΩ, respectively, for the 45 nm CMOS technology. We adopt 0 0.5 0.55 0.6 0.65 0.7 0.75 the worst case in estimating the low-to-high propagation The thershold voltage of the NMOS transistor, MN, in volts. delay in that only one input is assumed to be at logic “0”

and corresponds to the lowermost NMOS transistor so Fig. 7: The plot of the average propagation delay of the

that all the internal capacitances will be charged. 201 pseudo-PMOS logic versus the threshold voltage of MN, Applying Elmore’s delay formula [20 and 21] to the

Vthn. conventional CMOS circuit shown in Fig. 1 results in the Year

following estimations for tPLHc and tPHLc: Now, refer to Fig. 8 for the plots of the average 7 propagation delay versus the number of the inputs tPLHc = ()()(ln 2 [ P 1 ++ NP 2 + RCRRCR RNP ) 3 ....2 P ( −++++ 1)( )CRnRC nN ] according to the analysis and the simulation results ion I ion

adopting the scheme of Fig. 2 and estimating the time (33) rs delays up to the 50% point. and

-10 x 10 t = ()()(ln 2 [nR 1 RnC C ) ....2 ++−+−+ CRCRn ] 8 PHLc N 1 N 2 N 3 nN analysis 7 (34) simulation results 6 According to the estimation of the parasitic

5 capacitances adopted in this paper, we have: C1 = Cfan

4 + 3nC, C2 = C3 = …. = Cn = 2nC. After substituting for the values of these capacitances into Eqs. (33) and (34), 3 we obtain ropagation delay of the proposed scheme ropagation delay of the proposed

p 2 VII VeVolume XVII Issue 1 2 (35) according to the analysis and simulation in Seconds. t = ()()(ln 2 nnCR 12 −+++ 1) CRnnCR

[ ]

The averageThe PLHc P fan P N 0 2 3 4 5 6 7 8 () The number of the inputs, n. and

Fig. 8: The average propagation delay versus the 2 t = ()ln 2 R [nC ()++ 2 Cnn ] (36) number of the inputs according to the analysis and the PHLc N fan simulation results. d) The Average Power-Consumption Comparison Now, the average propagation delay according The average power consumption is the average to the CMOS logic, tpavgc, can also be defined in a similar of the power consumptions in cases of low-to-high and way as the average of the low-to-high and the high-to- high-to-low transitions. The power consumption of the low propagation delays, tPLHc and tPHLc, respectively, as pseudo-PMOS logic contains the static and the dynamic Researches in Engineering follows: power components. The static-power consumption is that associated with the first inverter due to the of PLHc + tt PHLc activation of its two devices in case of low-to-high t pavgc = (30) transition and due to the current drawn through the 2 activated PMOS devices and the always activated Toward a simplified evaluation for these two NMOS device, MN, in case of low-to-high transition also. Global Journal Global time delays, each NMOS and PMOS transistor in the The input voltage of the first inverter certainly depends CMOS-logic circuit is represented by an equivalent on the number of the activated inputs. So, we, in order resistance, RN and RP, respectively. In [19], approximate to simplify the dc-power estimation, assume that the expressions for the equivalent resistances of the NMOS first-inverter’s input is at VDD/2 and that this inverter is and PMOS transistors are: matched so that its output will also be at VDD/2. The estimated dc-power consumption according to this α n R N = (31) evaluation is certainly overestimated as the dc current of W the first inverter is at its maximum when the inverter’s ()L n

input is at VDD/2 [17]. Thus, the range of the number of written as the inputs over which the pseudo-PMOS logic is better V W  2 than the CMOS logic is expected to be larger than that P = DD k '   ()()VV 1+− λ V (39) DCLH 2 n B thn n CL1 estimated. In case of low-to-high transition, the dc 2  L  n current of the first inverter is (where LH indicates low-to- In the other case (high-to-low transition), all the high transition) inputs are activated with the result that all the PMOS 2 devices in the parallel connection become equivalent to 1 ' W   VDD   VDD  I DCLH = kn    −Vthn  1 + λn  (37) an open circuit. So, there is no dc power consumption in 2  L   2   2  n this transition (HL indicates high-to-low transition),

The dc-power consumption of the first inverter i DCHL = 0 (40) in the low-to-high transition is thus 2 P = 0 (41) VDD ' W   VDD   VDD  (38) DCHL P DCLH1= kn    −Vthn  1+ λn 

201 2 L 2 2  n     The average dc power consumption is thus

Year Similarly, the dc-power consumption through M can be N

 2  8 DCLH +PP DCHL VDD ' W   VDD   VDD  2 (42) P DC = = kn    −Vthn  1+ λn  ()()B VV thn 1+−+ λnVCL1  2 4  L  n  2   2   The average dynamic-switching power average short-circuit power consumption is [21] rsion I rsion e consumption is the average of that associated in cases of low-to-high and high-to-low transitions. In case of ' W  3 kn   τα 1 ()DD − 2VVf thn worst-case low-to-high transition, all except one of the  L n (46) Pscavg1= inputs are activated, thus the dynamic-switching power 12 consumption associated with the charging of the where τ1 is the rise or fall time of the voltage that feeds parasitic capacitances at the input of the first inverter, the output of the second inverter, and the gate terminals the first inverter and is equal to twice the average of the low-to-high and the high-to-low propagation delays at can be written as the input of the first inverter. Pscavg2 can be written as 2 2 PdLHp = αfVDDC out + αfVDD CL1CV L + αfVDD []2( −1) Cn W  3 ' τα ()− Volume XVII Issue VII V Volume XVII Issue (43) kn   2 DD 2VVf thn  L  = n (47) where α is the switching activity and f is the frequency of Pscavg 2

() operation. The corresponding value in case of high-to- 12 low transition is where τ2 is the rise or fall time of the voltage that feeds 2 2 the second inverter and is equal to twice the average of = α +α (44) PdHLp fVDDCout fVDD ()2 Cn the low-to-high and the high-to-low propagation delays at the input of the second inverter. Certainly, the short- Thus, the average dynamic-switching power circuit power consumption is zero in case VDD is smaller consumption associated with the parasitic capacitances than V + |V | as there is no time interval during thn thp at the previously mentioned nodes is which both the NMOS and PMOS devices conduct simultaneously [21]. dLHp +PP dHLp

Researches in Engineering (45) Pdavgp = The average dynamic-switching power 2 consumption of the CMOS logic is also taken as the of average of that in cases of low-to-high and high-to-low nal Note that all these capacitances have the same switching activities and the same frequencies of transitions. Adopting the worst case in case of low-to-

operation. The second type of the dynamic-power high transition (illustrated in Subsection C), the power consumption is the short-circuit power consumption required to charge the internal capacitances at the gate terminals as well as at the internal nodes is Global Jour Global associated with the two inverters, Psc1avg and Psc2avg. Assuming that the two inverters are matched, then the

= α 2 +−+− α 2 +++ = α 2 + + +− PdLHc fVDD[ C()()n 12 nnC 1 ][fVDD 21 ... CCC n] . fVDD[Cfan 3 ( )(nnCnC 231 )] (48)

During the high-to-low transition, all the inputs 2  2  are activated and thus the associated power P = αfV  + 2nCCn  (49) dHLc DD  consumption is

The logic swing, LS, at the output node is Fig. 11 in which the performance of the conventional simply equal to the difference between the output high CMOS logic degrades faster than that of the pseudo- and low levels. Since CL is discharged to 0 V with no PMOS logic with increasing f. This is certainly due to the contention from the PMOS device, LS is equal to VCL1. need to deal with numerous parasitic capacitances in Refer to Fig. 9 for the plots of LS versus Vthn according to the conventional CMOS-logic realization. According to the analysis and the simulation results (of Fig. 2). Fig. 11, the pseudo-PMOS logic is better than the

Certainly, the logic swing of the CMOS logic is VDD. conventional CMOS when f exceeds 15 MHz. According

0.8 to Fig. 12, it is apparent that the pseudo-PMOS logic exhibits an optimum behavior versus VDD due to the 0.7 analysis obvious conflictions associated with changing VDD with 0.6 simulation results the optimum performance occurring at VDD = 0.7685 V. 0.5 Specifically, increasing VDD enhances the logic swing 0.4 and the propagation delay; however, at the expense of

201 0.3 worsening the power consumption. In a nutshell, the

0.2 pseudo-PMOS logic has a smaller area and average Year c swing at the output node in Volts. in output node the at swing c ogi propagation delay but larger power consumption and

0.1

The l The slightly smaller noise margin compared with the CMOS 9 0 0.6 0.62 0.64 0.66 0.68 0.7 0.72 0.74 0.76 0.78 0.8 logic. The threshold voltage of MN in Volts. 27 x 10 Fig. 9: The change of the logic swing with the threshold 15

conventional CMOS I rsion voltage of M , V , according to the analysis and the e N thn simulation results. proposed scheme f) The Figure of Merit 10 In order to evaluate the performance of the pseudo-PMOS logic compared to the CMOS logic, we define a figure of merit, FOM, that includes the four 5 previously estimated metrics; the area, the average ofres merit of the conventional gu propagation delay, the average power consumption, scheme. proposed the and CMOS he fi and the logic swing. Since these four metrics are T 0 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 preferred to be at their minimum except the logic swing The number of the inputs, n. which is preferred to be at its maximum, the FOM is VII V Volume XVII Issue

defined as follows according to the conventional and Fig. 10: The plots of FOMc and FOMp versus the number () proposed logic-circuit families: of the inputs, n.

27 x 10 LSc 7 (50) FOM c= conventional CMOS c avgc PtA avgc 6 proposed scheme and 5 LS 4 p (51) FOM p= 3 p PtA avgpavgp 2 Researches in Engineering respectively. Thus, the larger the FOM, the better the gures of merit of the conventional i

CMOS and the proposed scheme. proposed the and CMOS 1 performance will be. Refer to Figs. 10, 11, and 12 for the of

The f

0 nal plots of the figures of merit of the CMOS logic and the 1 2 3 4 5 6 7 8 9 10 7 pseudo-PMOS logic according to the version of Fig. 2 The frequency of switching, f, in Hz. x 10 versus n, f, and VDD, respectively. The parameters adopted with these plots are n = 8, Cfan = 10 fF, and f = Fig. 11: The plots of FOMc and FOMp versus the

10 MHz. As shown, the performance of the pseudo- frequency of switching, f. Jour Global PMOS logic is better than that of the CMOS logic when n exceeds 8. This can be attributed to the degradation of the performance of the CMOS logic when n exceeds this value due to the limitations discussed in Section I. However, the matter is not that bad with the pseudo-

PMOS logic as mentioned in Section III in which the degradation is merely due to the increased number of the PMOS transistors and the associated parasitic

27 x 10 4.5 proportional to the channel length [17]. So, it decreases 4 with technology scaling with the result that the drain 3.5 current increases. This effect is more pronounced in the

3 CMOS logic due to the division of the voltage across the stacked devices which has no counterpart in the 2.5 pseudo-PMOS logic. Also, the slope of the voltage- 2

erit of the proposed scheme. transfer characteristics of the inverters in the transition 1.5 m region decreases. So, for a certain difference that is 1 developed at the inverter input, there is a smaller value 0.5 for the logic swing at the inverter output. This indicates

The figure of 0 0.7 0.8 0.9 1 1.1 1.2 1.3 that a smaller propagation delay is associated with the The power-supply voltage, VDD, in Volts. two cascaded inverters.

Fig. 12: The plot of FOMp versus the power-supply VI. EFFECT OF PROCESS VARIATIONS 201 voltage, VDD. In this section, the effect of the process Year V. EFFECT OF TECHNOLOGY SCALING variations on the reliability of the pseudo-PMOS logic is

investigated quantitatively. Specifically, the variations of 10 In this section, the effect of technology scaling the aspect ratio and the threshold voltage of the NMOS on the pseudo-PMOS logic is investigated. The following and PMOS devices composing the voltage divider are effects are investigated: velocity saturation, mobility taken into account with their effects on the first inverter’s degradation, reduction of the VDD/Vthn ratio, increased input voltage quantified. The equation describing the process variations, and channel-length modulation. voltage at the input of the first inverter was derived in a) Velocity Saturation and Mobility Degradation Section IV and is repeated here for convenience as These two effects act to reduce the current of follows: the MOS transistor for the same applied voltages. Thus, W  1 W  2 the time required to develop a certain voltage at the first- k '   ()− − kVVV '   ()−VV p  L  DD thp DD 2 n  L  B thn inverter input or at the output of the circuit increases. p n VCL1 = (52) 1 W  2 W  However, this effect is common in both the CMOS logic k '   () λ +− kVV '   ()− VV 2 n  L  B thn pn  L  DD thp and the pseudo-PMOS logic. It must be noted that the n p mobility-degradation effect is more pronounced in Let the variation in the aspect ratio of the NMOS Volume XVII Issue VII Version I VII Version Volume XVII Issue NMOS transistors compared to PMOS ones. Thus, the sizing of the PMOS transistors is expected to decrease device be Δ(W/L)n, then after substituting (W/L)n by (W/L)n

() with technology scaling. Since most of the area of the + Δ(W/L)n into Eq. (52), neglecting the terms containing 2 pseudo-PMOS logic is due to the PMOS network, the (Δ(W/L)n) , using the approximation area advantage becomes more pronounced. 1 /V Ratio 1−≈ x for x << 1 (53) b) Reduction of the VDD thn + Due to the performance degradation with 1 x reducing VDD, Vthn also reduces with technology scaling and performing some algebraic manipulations, but at a smaller rate, thus the ratio, VDD/Vthn, is expected we get the percentage variation of the voltage, VCL1, due to decrease with technology scaling. This has the effect to the change of (W/L)n (let it be ΔVCL11/VCL1) as shown in of reducing the short-circuit power consumption which Eq. (54). Researches in Engineering enhances the performance of the pseudo-PMOS logic. The percentage variations of VCL1 due to each of c) Increased Process Variations ΔVthn, Δ(W/L)p, and ΔVthp can be evaluated in a similar The effect of the process variations increases manner and shown to be (let them be ΔVCL12/VCL1, with technology scaling. This has the effect of narrowing ΔVCL13/VCL1, and ΔVCL14/VCL1, respectively) as shown in Eqs. (55), (56) and (57). the range within which the threshold voltage of the first Refer to Figs. 13, 14, 15, and 16 for the plots of inverter lies for the proper operation of the pseudo- Global Journal of Journal Global PMOS logic. This seems to be the most important the percentage variations of VCL1 due to that in (W/L)n, degradation associated with the pseudo-PMOS logic as Vthn, (W/L)p, and Vthp, respectively. It is obvious that the it reduces its reliability if the version of Fig. 3 were used. variation in the threshold voltage of MP and MN has the This effect, however, has no counterpart in the CMOS largest effect on VCL1. If these variations cannot be logic. tolerated, the two inverters must be dispensed and the scheme of Fig. 2 can instead be adopted. d) The Channel-Length Modulation Effect The Early voltage modeling the dependence of the drain current on the drain-to-source voltage is

0.014 0.08

0.012 0.07 0.06 0.01 0.05 0.008 0.04 0.006 0.03 ercentage variation of the rcentage variation of the

p 0.02 e 0.004

The 0.01 The p

0.002 inverter. first the of input the at voltage 0 voltage at the input of the first inverter. first the of input the at voltage 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0 The percentage variation of the threshold voltage of the NMOS devices. 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 The percentage variation of the aspect ratio of the NMOS devices

Fig. 14: The percentage variation of the voltage, VCL1,

Fig. 13: The percentage variation of the voltage, VCL1, 201 versus that of the threshold voltage of MN. versus that of the aspect ratio of MN. Year

  1 2 1 2 11  ' ()−− VVk ' ()Vk −− V λ  ∆V W  Bn thn Bn thn n CL11 −= ∆   2 − 2  (54)   VCL1  L  n ' W  1 ' W  2 1 ' W  2 ' W  k p   ()DD − thp DD − kVVV n   ()B −VV thn k n   ()VB thn λ +− kV pn   ()DD − VV thp    L  p 2  L  n 2  L  n  L  p  ersion I ersion

 W  W    k '   ( −VV ) k '   ()V −V λ  ∆ n B thn n B thn n VCL12   L n  L n  = ∆Vthn + (55) ue VII V V  W  1 W  2 1 W  2 W   CL1 k '   −− kVVV '   ()−VV k '   (V ) λ +− kV '   − VV  p ()DD thp DD n B thn n B thn pn ()DD thp    L  p 2  L n 2  L n  L  p 

   ' '  ∆V W  p ()DD − thp VVVk DD p ()Vk DD − Vthp CL13 = ∆   −  (56)   Volume XVII Iss VCL1  L  p ' W  1 ' W  2 1 ' W  2 ' W  k p   ()DD thp DD −− kVVV n   ()B −VV thn kn   ()VB thn λ +− kV pn   ()DD − VV thp 

  L  p 2  L n 2  L n  L  p  ()

 ' W  ' W    − k p   VDD k p    ∆V  L  p  L  p CL14 = ∆V  +  (57) thp   VCL1 ' W  1 ' W  2 1 ' W  2 ' W  k p   ()DD thp DD −− kVVV n   ()VB −Vthn kn   ()VB thn λ +− kV pn   ()DD − VV thp    L  p 2  L n 2  L n  L  p 

0.016 0.25 Researches in Engineering 0.014

0.012 0.2

of nal

0.01 0.15 our 0.008

0.006 0.1

ercentage variation of the Global J Global ercentage variation of the

0.004 p p 0.05 The

The 0.002 voltage at the input of the first inverter. first the of input the at voltage

voltage at the input of the first inverter. first the of input the at voltage 0 0 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 The percentage variation of the threshold voltage of the PMOS devices. The percentage variation of the aspect ratio of the PMOS devices.

Fig. 15: The percentage variation of the voltage, VCL1, Fig. 16: The percentage variation of the voltage, VCL1, versus that of the aspect ratio of MP. versus that of the threshold voltage of MP.

VII. IMULATION ESULTS -9 S R x 10

1.5 In this section, the pseudo-PMOS logic (Fig. 2) conventional CMOS

is verified by simulation adopting the 45 nm CMOS proposed scheme

technology with VDD = 0.8 V [22]. Assume minimum- 1 sized devices and a frequency of operation equal to 500 MHz. As a compromise between the enhancement of

the logic swing and the degradation in the high-to-low 0.5

propagation delay with increasing Vthn, MN is chosen with a threshold voltage equal to 0.7 V and biased by VB = igh-to-low propagation according delays

V . In evaluating the low-to-high or the high-to-low h DD 0 2 3 4 5 6 7 8 The The number of the inputs, n. propagation delays, the 50% criterion is adopted. The Seconds. in schemes conventional and proposed to the

worst-case scenarios are also adopted.

Refer to Figs. 17, 18, and 19 for the low-to-high, Fig. 18: The plots of the high-to-low propagation delays 201 the high-to-low, and the average propagation delays, according to the conventional CMOS logic and the respectively, versus the number of the inputs, n, for the pseudo-PMOS logic versus the number of the inputs. Year conventional and pseudo-PMOS logic families. The low-

12 to-high propagation delay according to the pseudo- -9 x 10 PMOS logic is found to be smaller than that of the 1 conventional one for all values of n. The superiority in conventional CMOS performance of the pseudo-PMOS logic during the low- 0.8 proposed scheme

ersion I ersion to-high transition is attributed to the need to charge all 0.6 the internal capacitances of the pull-down network in the

conventional CMOS stack. Although the contention 0.4

current of MN slows down the charging of CL in the ue VII V pseudo-PMOS logic, it does not affect the performance 0.2 considerably. propagation torage according the delays ave 0 2 3 4 5 6 7 8 proposed and conventional schemes in Seconds. in schemes conventional and proposed On the other hand, the high-to-low transition of The The number of the inputs, n. the pseudo-PMOS logic is faster than that of the

conventional CMOS logic when n exceeds 4. The Fig. 19: The plots of the average propagation delays average propagation delay of the pseudo-PMOS logic is according to the conventional CMOS logic and the

Volume XVII Iss smaller than that of the conventional CMOS logic when pseudo-PMOS logic versus the number of the inputs.

n exceeds 3. Finally, note that the degradation in the () logic swing compared to the conventional CMOS logic -6 x 10 is approximately 63 mV, i.e. only 7.8%, in the worst case. 8 conventional CMOS 7 proposed scheme

-10 x 10 6 4

s in Seconds. Seconds. in s 3.5 conventional CMOS proposed scheme 4

cheme 3 ays according according ays 3 2.5 on del 2 2 rage power consumption according to the Researches in Engineering ave 1 1.5 Watts. in schemes conventional and proposed 2 3 4 5 6 7 8 The The number of the inputs, n. 1 nal of nal oposed and conventional s conventional and oposed ow-to-high propagati 0.5 Fig. 20: The plots of the average power consumption our 2 3 4 5 6 7 8

The l The The number of the inputs, n. to the pr to the according to the conventional CMOS logic and the pseudo-PMOS logic versus the number of the inputs. Fig. 17: The plots of the low-to-high propagation delays Global J Global according to the conventional CMOS logic and the pseudo-PMOS logic versus the number of the inputs.

-15 x 10 4 conventional CMOS 3.5 proposed scheme 3

2.5 2 1.5

0.5 rage power-delay products according to the

ave 0 2 3 4 5 6 7 8 proposed and conventional schemes in Joules. Joules. in schemes conventional and proposed The The number of the inputs, n.

Fig . 21: The plots of the average power-delay products according to the conventional CMOS logic and the pseudo- 201 PMOS logic versus the number of the inputs.

Year -24

x 10 3.5 propagation delay but larger average power 13 conventional CMOS consumption and slightly smaller noise margin (by 3 proposed scheme about 7.8% in the worst case compared to the 2.5 conventional CMOS logic). According to the estimation 2 performed in this paper using a proper figure of merit, the pseudo-PMOS logic is better than the CMOS logic I ersion 1.5 when the number of the inputs exceeds 8. 1 References Références Referencias

0.5 ue VII V rage energy-delay products according to the 1. K. Martin, Digital Integrated Circuit Design, Oxford

ave 0 2 3 4 5 6 7 8

The University Press, New York, 2000. proposed and conventional schemes in Joule-Seconds. Joule-Seconds. in schemes conventional and proposed The number of the inputs, n. 2. M. M. Khellah and M. I. Elmasry, “Use of Charge Fig. 22: The plots of the average energy-delay products Sharing to Reduce Energy Consumption in Wide according to the conventional CMOS logic and the Fan-In Gates,” Proceedings of the IEEE International pseudo-PMOS logic versus the number of the inputs. Symposium on Circuits and Systems, 31 May - 3 Jun. 1998. Volume XVII Iss The average power consumption, the average

3. S. C. Prasad and K. Roy, “Transistor Reordering for power-delay products (PDPs), and the average energy- () Power Minimization under Delay Constraint,” ACM delay products (EDPs) are plotted versus n in Figs. 20, Transactions on Design Automation Elect. Syst., Vol. 21, and 22, respectively, for the conventional and 1, No. 2, Pages: 280 - 300, Apr. 1996. proposed logic families. The average power 4. E. Musoll and J. Cortadella, “Optimizing CMOS consumption of the CMOS logic rises with n at a faster Circuits for Low Power Using Transistor rate compared to that of the pseudo-PMOS logic due to Reordering,” Proceedings of European Design and the need to charge the internal capacitances of the Test Conference, Pages: 219 - 223, 1996. CMOS logic circuit. The PDP and the EDP, however, of 5. C. Tan and J. Allen, “Minimization of Power in VLSI the pseudo-PMOS logic are smaller than their Circuits Using Transistor Sizing, Input Ordering, and counterparts of the CMOS logic when n exceeds 6 and Statistical Power Estimation,” Proceedings of Researches in Engineering 5, respectively. International Workshop Low-Power Design, Pages:

VIII. CONCLUSIONS 75 – 80, 1994. of nal 6. W. H. Chiu and H. R. Lin, “A Conditional Isolation our The pseudo-PMOS logic family was adopted for Technique for Low-Energy and High-Performance realizing wide fan-in CMOS circuits containing long Wide Domino Gates,” IEEE Region 10 Conference, stacks of NMOS transistors. The area, propagation 30 Oct. - 2 Nov. 2007. J Global delay, power consumption, power-delay and energy- 7. H. Mostafa, M. Anis, and M. Elmasry, “Novel Timing delay products of this family were compared with those Yield Improvement Circuits for High-Performance of the conventional CMOS logic. The pseudo-PMOS Low-Power Wide Fan-In Dynamic OR Gates,” IEEE logic showed superior performance from the points of Transactions on Circuits and Systems I: Regular view of the average propagation delay, power-delay Papers, Vol. 58, Issue: 8, Pages: 1785 – 1797, Aug. product, and energy-delay product when the number of 2011. the inputs exceeds 3, 6, and 5, respectively. In fact, the 8. K. Mohanram and N. A. Touba, “Lowering Power pseudo-PMOS logic had a smaller area and average Consumption in Concurrent Checkers via Input

Ordering,” IEEE Transactions on Very Large Scale 21. J. E. Ayers, Digital Integrated Circuits: Analysis and Integration (VLSI) Systems, Vol. 12, Issue: 11, Design, CRC Press, Boca Raton, USA, 2005. Pages: 1234 - 1243, Nov. 2004. 22. Predictive Technology Model (PTM), http://ptm. 9. A. A. George and A. R. Sankar, “Current asu.edu. Comparison Based High Speed Domino Circuits,” National Conference on Science, Engineering, and Technology (NCSET), Vol. 4, Issue: 6, Pages: 102 – 105, 2016. 10. F. Moradi, D. T. Wisland, H. Mahmoodi, and T. V. Cao, “High Speed and Leakage-Tolerant Domino Circuits for High Fan-in Applications in 70nm CMOS Technology,” Proceedings of the 7th International Caribbean Conference on Devices, Circuits, and

201 Systems, Mexico, 28 - 30 Apr., 2008. 11. K. Rajasri, M. Manikandan, A. J. Dhanaseely, and

Year M. Nishanthi, “Low Leakage High Speed Domino

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ue VII V 13. X. Kavousianos and D. Nikolos, “Novel Single and Double Output TSC Berger Code Checkers,” Proceedings of VLSI Test Symposium, Pages: 348 – 353, 1998. 14. C. Metra, M. Favalli, and B. Ricco, “Tree Checkers for Applications with Low Power-Delay Requirements,” Proceedings of International Volume XVII Iss Symposium on Defect and Fault Tolerance VLSI

Systems, Pages: 213 – 220, 1996. () 15. B. Razavi, Design of Analog CMOS Integrated Circuits, Second Edition, McGraw-Hill, New York, 2016. 16. H. Shichman and D. Hodges, “Modeling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuit,” IEEE Journal of Solid-State Circuits, Vol. sc-13, No. 3, Pages: 285 - 289, Sep. 1968. 17. A. S. Sedra and K. C. Smith, Microelectronic Researches in Engineering Circuits, Seventh Edition, Oxford University Press, New York, 2015.

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