Frequency Compensation Techniques for Op-Amps and Ldos: a Tutorial Overview

Frequency Compensation Techniques for Op-Amps and LDOs: A Tutorial Overview

Annajirao Garimella and Paul M. Furth Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA Email: [email protected], [email protected]

Today's op-amp is not just a stand-alone IC, rather r------,-- Vi" it Abstract-is more custom and complex, catering the needs of highly integrated SoC. Tighter line and load regulation, low quiescent current operation, capacitor-free and wide-range output capac itor specifications are some of the contradicting requirements in an which drive newer topologies and newer frequency VaUT compensationLDO, techniques. The objective of this paper is to provide a tutorial treatment of some of the basics and recent advances in frequency compensation. Transistor level implementation of efficient zero techniques and design examples are detailed. COUT LHP r Rj2 I. INTRODUCTION Fig. 1. Schematic of a simple two-stage LDO (compensation network not Several op-amp and LDO architectures have evolved, from shown). a simple two-stage topology using Miller compensation with nulling resistor to a complex multi-stage op-amp with feed forward and nested/reverse-nested feedback paths which uti LHP Zero due to ESR: Wz, ESR = -RESR I eOUT lize active capacitance multiplication techniques. This tutorial LHP Zero due to Compensation Capacitor Gm: attempts to highlight some of the recent advances in compen wZ,e = +rc::;f Rm = sation techniques after revisiting with some basics. or 0 Rest of the paper is organized a follows In Section II, a l : , -R Ie Rm Wze::::: Tn Tn ; f r _g simple two-stage LDO is analyzed, focusing on the necessity o » rnP Output Impedance: ROUT = (Rf + Rf2) to compensate an LDO. Section III details various topologies rapassll l for frequency compensation, starting from basic Miller's theo Feedback Factor: j3 = Rf2/ (Rfl+ Rf2) rem to advanced inverting current buffer using current mirror and impedance degeneration techniques. Several efficient LHP External Compensation using Output Capacitor and ESR A. zero techniques are detailed. In the case of external compensation with an output ca

II. NECESSITY OF FREQUENCY COMPENSATION IN LDOs pacitor, the output pole WPOUT is dominant and WZ,ESR compensates the LDO [1], [2]. Consider the schematic of a two-stage low dropout voltage regulator (LDO) , shown in Fig. 1. The circuit consists of B. Internal Compensation using Capacitance Multiplication a PMOS pass transistor a sampling network formed Mpass, In the case of an output capacitor-free LDO architecture by Rf and Rf2' a single-stage error amplifier gmEA, an l with internal compensation, the dominant pole is Wp EA, output capacitor GOUT with equivalent series resistance (ESR) , R created internally at the output of error amplifier [3]. ESR· Often op-amps are designed to operate for a particular The small signal equivalent of Fig. 1 (using Miller com loading condition and hence the location of poles are fixed. In pensation capacitor G and a nulling resistor between m Rm case of an LDO, the output load current is designed to vary nodes VEA and VOUT) is shown in Fig. 2. After solving the and the location of the poles of LDO P and P OUT Kirchhoff's current law nodal equations, the locations of poles W ,EA W , move, as illustrated in Fig. 3. and zeros are given by For an internally-compensated LDO, at low load currents,

Closed Loop DC Gain: ADe = j3gmEAREAgmpROUT the non-dominant output pole moves to lower frequencies First P ole: WPl::::: REAe 9� RoUT since r a,pass of the PMOS pass transistor is inversely pro "' p portional to the load current, given by pe"' Output Pole: WPOUT = -e e e e e EA Tn+ gc Tn OUT + OUT EA 1 = (1) Parasitic RHP Zero: Wz, e 9 = + ro,pass \1 d � LOAD cgd,pass /\

978-1-61284-857-0/11/$26.00 (02011 IEEE B. Miller RHP Zero Rill Fig. 5(a) shows a Miller compensation capacitor, used to VOUT split the poles associated with nodes X and Y. In addition to pole splitting, the Miller capacitor Gm forms a feedforward path resulting in an RHP zero, located at [5], [6]

Cut Loop 9mY __ .... Wz = + (3) L-_� !:I" !"""*- --I Gm . (a) Shifting the Miller zero fro m RHP to LHP C. Compensation The Miller RHP zero can either be cancelled or shifted to Network

Pllrasitic CUJXlcillmcC the LHP by choosing an appropriate value for the series nulling e,i orJ\lp�. resistor Rm shown in Fig. 5(b). The equation for W becomes: "OUT z

11[1 1 = (4) + IIESR Wz II vfo " oul Gm - Rm COUT , II" (g�y )

(b) Fig. 2. (a) Simplified block diagram representation and (b) small signal equivalent model of the LOO of Fig. I. � Vy

Light load current (Eg. �A) • I Heavy load current (Eg. IOOmA) " • = Lighlload to heavy load = Zc� ---+ ZcI " Zc Z-our 1+ \ Zc IN ___ � Heavy load to liglllioad Z f 1 + Av Av Av

Fig. 4. Illustration of the Miller's theorem. Frequency (Hz)

x0 yc II Wz =+ gmY Cm (a) �,�------_ . em . I Wz "'--- xc . Fig. 3. Movement in the location of poles at different loading conditions. 't\\ Ir------X RmCm Rm Cm __ 1 (b) II",» gill}' The movement of the output pole below the unity-gain (ror J Fig. 5. (a) Miller compensation (b) Miller compensation with nulling resistor. frequency jeopardizes stability of the closed-loop amplifier. Hence, proper compensation is required to ensure stability over LHP RHP a wide range of loading conditions. U ncom pen sated

III. OVERVIEW OF FREQUENCY COMPENSATION TECHNIQUES

Miller's Theorem A. If an impedance Zc is connected between its input and out ••••• put nodes of an ideal voltage amplifier of gain -Av, Miller's Wp2 � (UP) ""'" .----_ ... '" --_ .. - ... _ .. _-_ ... - .. theorem [4] states that the input and output impedances of the ( . . .. circuit, of Fig. 4, are given by Increasing Rm Fig. 6. Pole-Zero diagram showing movement of Zero for various values of Zc Zc nulling resistor ZIN = � ---l+Av -Av Rm. Zc - When Rm = 1/ 9m the RHP zero gets cancelled. For ZOUT - � Z c (2) y, 1 +l/ Av Rm 1 / 9m the zero shifts to LHP and is approximately y, located» at If the impedance Zc is replaced by a capacitor Zc = 1 1/ sGc, then the input capacitance GIN � AvGc gets multi (5) Wz�- -- plied by the gain of the op-amp and feels "big". The output RmGm capacitance GOUT � Gc, implying that the Miller capacitance as shown in Fig. 6. Similarly a voltage or current buffer can loads the output. On the contrary, if Zc is replaced by a be placed in series with the Miller capacitor in order to move resistor Rc, the input resistance gets divided by the gain. the RHP zero to the LHP [7], as described below. D. Miller Compensation using Current Buffers

Current buffers can be loosely classified as non-inverting or Rc Cc I----<>y I inverting. Wz�- 1 RcCc I) Cascode Compensation: As shown in Fig. 7, a non 9mcG Vbiasl� r-y M inverting current buffer, implemented with a common-gate am X CG RC» (a) plifier transistor gmCG, can be used to obviate the feedforward (for _I_gll/CG J path [5], [6], [8], [9] and introduce a LHP zero at

� gmCG Cc y � ---1 -- (6) Wz=- t--o W Cc Z RcCc This cascode compensation topology is popularly known as 1x _ Ahuja compensation. A cascode transistor MCG inherent in I (b) a folded-cascode or a telescopic op-amp introduces an LHP (fOrl?c.»gll/BU J Fig. 9. (a) Modified Ahuja cascode compensation (b) Resistor Rc in series zero without additional bias circuitry or quiescent current [9], with current mirror. [10].

The significance of adding resistor Rc is illustrated in gmCG Fig. 10, in which the zero moves to lower frequencies as the Wz=- 1 Cc value of Rc increases. 9mCG

Fig. 7. llIustration of Ahuja cascode compensation. 1m Increasing lie ------2) Compensation using a Current Mirror: A current mirror . is an ubiquitous component, and is inherent in a differential, Re folded-cascode and telescopic op-amps. A simple, yet efficient Miller compensation network can be formed with a current _ g",CBIIC» 1 - gmen I mirror of unity current gain, as shown in Fig. 8 [10]-[12]. 0) � - Z,OLD flJZ.NEIf" Cc This inverting current buffer can be used in series with IIcCc compensation capacitor to introduce an LHP zero at Fig. 10. Significance Rc: Diagram illustrating the movement of the current buffer zero as a function of Rc [13]. gm,BU W --- (7) z =- Cc Fig. 12 shows a design example of LDO of [10] and Fig. 11 shows the corresponding small signal diagram. In this circuit, two LHP zeros are formed by positive and inverting current gmBU Wz=- buffers in a reverse nested Miller compensation implementa Cc tion.

Fig. 8. Miller compensation using inverting current buffer topology. E. Effective Placement of LHP Zeros Often LHP zeros are used to cancel poles and improve phase response. To make the LHP zero more dominant, either the value of the transconductance (of Eqns. 6 or 7), or the compensation capacitance Cc has to be modified. However changing these values for a given design significantly affects other small signal and large signal parameters and may not form a feasible solution. A simple and effective solution for accurately placing the LHP zero is to place a resistor Rc in series with the current Fig. II. SmaU signal diagram of reverse nested Miller Compensation scheme buffers as shown in Fig. 9 [10], [13]. The new location of the using current buffers implemented in the LDO. LHP zero is given by 1 1 (8) WZ,CB =- - Passive LHP zero at Internal Node Cc (l/gmCB +Rc ) � RcCc F. Equation 8 illustrates the new location of the LHP zero, Similar to the LHP zero of an output capacitor with ESR, independent of transconductance, giving an additional degree a LHP zero can be introduced with small on-chip capacitance of freedom with the choice in value of resistor Rc. Ci and series resistance Ri as shown in Fig. 13. Common-gate transistor as current buffer

Mp+-----, !

gmP

Vi v�

Rf2 GND

First stage: Folded cascade Second-stage: Common Power Output Current mir�or implements Load Amplifier Source Amplifier Stage Capacitor inverting current buffer

Fig. 12. Schematic of LDO, based on [10] highlighting inverting current buffer and modified cascode compensation.

REFERENCES i?esr i?i I . 11-;,111OJ z s fl1l11ernOIOJ - ,e r c = - Re = -- [l] G. A. Rincon-Mora and E. Allen, "A low-voltage, low quiescent srColi Z,' R;Ci l C current, low drop-out regulator,"P. IEEE of Solid-State Circuits, vol. 33, L.1rgccxtcm.1\ Tsma'� ol�-chip 1. cap.1cltor 1 capacItor no. I, pp. 36-44, Jan. 1998. [2] G. A. Rincon-Mora, Analog IC Design with Low-Dropout Regulators. 0111 (a) (b) I McGraw-Hili Professional, 2009, United States., 2009. Fig. 13. LHP zero with (a) ESR (b) internal capacitor and series resistance. [3] Y. Man, K. Mok, and M. Chan, "A high slew-rate push-pull T.output amplifierP. forT. low-quiescent current low-dropout regulators with transient-response improvement," IEEE Trans. Cir. Syst. vol. 54, no. 9, pp. 755-759, Sept. 2007. II, [4] M. Miller, "Dependence of the input impedance of a three-electrode 1.vacuum tube upon the load in the plate circuit," Scientific Papers of the Bureau of Standards, vol. 15, no. 351, pp. 367-385, 1920. [5] P. R. Gray and R. G. Meyer, "MOS operational amplifier design-a tutorial overview," IEEE Solid-State Circuits, vol. 17, no. 6, pp. 969- 982, Dec. 1982. 1. [6] B. K. Ahuja, "An Improved Frequency Compensation Technique for Fig. 14. Impedance degeneration differential pair creating LHP zero. CMOS Operational Amplifiers," IEEE Solid-State Circuits, vol. 18, no. 6, pp. 629-633, Dec. 1983. 1. [7] G. Palumbo and S. Pennisi, Feedback Amplifiers: Theory and Design. Kluwer Academic Publishers: Boston, 2002. G. LHP Zero from Source Impedance Degeneration [8] R. Reay and G. A. Kovacs, "An unconditionally stable two-stage CMOS1. amplifier," IEEET. Solid-State Circuits, vol. 30, no. 5, pp. 591- The combination of source degeneration resistor and Rs 594, May 1995. 1. capacitor Cs in Fig. 14 introduces a LHP zero at [9] D. Ribner and M. Copeland, "Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range," IEEE Solid-State Circuits, vol. 19, no. 6, pp. 919-925, Dec. 1984. 1 WZI = - (9) [10] 1.A. Garimella, M. Rashid, and P. M. Furth, "Reverse Nested Miller RsCs Compensation UsingW. Current Buffers in a Three-Stage LDO," IEEE This impedance degeneration technique is utilized in [14] Trans. on Circuits and Syst. vol. 57, pp. 250-254, Apr. 2010. II, to obtain a high power supply rejection response in an LDO. [II] G. Rincon-Mora, "Active capacitor multiplier in miller-compensated circuits," IEEE Solid-State Circuits, vol. 35, no. I, pp. 26-32, Jan. 2000. 1. IV. SUMMARY [12] Hurst, S. H. Lewis, P. Keane, Aram, and K. C. Dyer, "Miller compensationP. 1. using current1. buffers inF. fully differential CMOS two Several LHP zero techniques for op-amps and LDOs are stage operational amplifiers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 275-285, Feb. 2004. elucidated. Current buffers embedded in the op-amp can be [l3] A. Garimella, M. Rashid, and P. M. Furth, "Single-Miller Compensa utilized to implement the compensation network, obviating the tion using InvertingW. Current Buffer for Multi-Stage Amplifiers," in Proc. need for additional circuitry and power consumption. IEEE International Symposium on Circuits and Systems, ISCAS May 2010, pp. 1579-1582. 2011, [14] A. P. Patel and G. A. Rincon-Mora, "High power-supply-rejection (PSR) ACKNOWLEDGMENTS current-mode low-dropout (LDO) regulator," IEEE Trans. on Circuits and Syst. Express Briefs, vol. 57, no. II, pp. 868-873, Nov. 2010. II: Sincere thanks to Punith R. Surkanti for typesetting the paper.