arXiv:1812.04077v1 [cs.PL] 7 Dec 2018 ecl RS- mltr(B Emulator BRISC-V call we h 8 rhtcueasml agaei yial consid typically is language assembly architecture x86 The eoe o h ups ftahn optrognzto a organization computer teaching of purpose the for veloped h ecigtoshv e octhup. catch to yet have tools alternat teaching RISC the modern more a as classes college-level in increasi used is It emulators. software and designs, fabricated support software growing extensio implementations, of public number a posals, with years, recent the in It adoption architectures. broad CISC and RISC proprietary to alternative finished. has re or the paused point of is instruction state program the the the when showing with memory tables code and as the well as of visible, view clearly emulato a The student line-by-line. the program fers the ei through then user steps The or calls. system runs of number the small initializing a with providing wrap tasked and then is kernel is The which kernel. small editor, a external in an in a inte an written loading user program first by bly graphical emulator a the uses in student The wrapped (GUI). face eit or emulators line, RISC command using the hand by through assembly write set to instruction learn small dent relatively their to due choice common class architectu RISC entry-level Instead, college organization. a computer in or sembly taught be to complex and large optracietr classes. bee architecture has computer and emulators, RISC-based existing by inspired is It INTRODUCTION 1 tool. web-based, emulation, simulation, assembly, ISA, RISC-V, KEYWORDS extensibil and usage, emulator. workings, BRISC-V the the present i we any or Here systems lation. operating re different not for does support it maintaining as javascrip deployment, pure simplify to web-based, meant a plementation is emulator The RI emulators. existing by CISC inspired emulator RISC-V a tool, teaching and (B BRISC-V the a present writing We to bly. students introduce to used tool Emulato teaching architectures. common and ISAs RISC a proprietary as to architecture native RISC-V clas the adopting architecture started computer recently have and organization computer Many ABSTRACT nti ae,w rsn u rwe-ae ICVemulator RISC-V browser-based our present we paper, this In an as seen widely architecture RISC open-source an is RISC-V RS- mltr tnaoe Installation-Free, Standalone, A Emulator: BRISC-V so nvriyRISC-V University oston so nvriyRISC-V University oston dpieadScr optn ytm AC)Laboratory (ASCS) Systems Computing Secure and Adaptive rwe-ae ecigTool Teaching Browser-Based eateto lcrcladCmue Engineering Computer and Electrical of Department ial skvadMce .Kinsy A. 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The single_step function takes the instruction at space, heap segment, data segment, and text segment. Each line the current instruction pointer (IP) and depending on the type of represents one word (32 bits). The address is shown on the left instruction, updates the registers, memory, and IP. How each in- in hexadecimal format (light blue), and the value is shown on the struction is handled (ADD, JALR, AUIPC, etc.) is hardcoded in the right. Lines belonging to the text segment also contain a comment emulator. The run instruction repeatedly calls the single_step specifying which instruction is stored at that location. Same as instruction until it detects that the PC has hit the backend kernel with labels in the code (middle) column, each of the segments can infinite loop or breakpoint. The setup_emulator is used to initial- be folded. Figure 3 depicts the memory management layout. ize or reset the emulator. It calls the appropriate parser functions, stores parsers outputs, and initializes the registers and memory. Stack User Emulator state & user commands Higher GUI Bottom Addresses Stack Segment Parsing errors Stack User Parser Emulator Free Space Top code Variable Size Kernel code Registers Memory Free Space

Figure 1: The emulator pipeline. Heap Segment

Data Segment 3 USING THE BRISC-V EMULATOR Fixed Figure 2 shows a screenshot of the current version of the emula- Lower Text Segment Size tor web-page. The page is split into three columns. In the middle Addresses column, we have buttons for loading assembly, running the loaded code, stepping through one instruction, and restarting the emu- Figure 3: Emulator program memory management. lator 1 . Below the buttons is a code editor 2 (though currently read-only). The editor shows both the kernel lines 3 (with a grey background), as well as user’s code 4 (with a white background). 4 EXTENSIBILITY The current instruction is highlighted blue 5 . Each instruction has While there exist more mature RISC-V emulators like the RISC-V an instruction pointer before it 6 (shown here in decimal). Right- Angel [1], we choose to write our own for multiple reasons: (1) clicking on an instruction opens a context menu where the user RISC-V Angel seems focused more on performance (booting Busy- can set or remove a breakpoint at the selected instruction. When Box in seconds) than on showing the state of the processor at every running the code (not stepping through it), the run will stop when instruction, (2) RISC-V Angel is harder for students to modify. We hitting a breakpoint. This allows the user to skip large parts of as- aim to provide students with a simple, ‘hackable’ tool which they sembly and quickly debug regions of interest. The editor allows can use in computer organization classes to get familiar with as- code-folding, where the user can hover left of any label and a + sembly, in computer architecture classes to test out existing ISA symbol appears. Clicking the symbol folds/unfolds the instructions extensions (i.e. floating point or vector instructions) and confirm between the specified and the next label. their compiled code behaves as expected, and in hardware security On the left-hand column, the user can monitor registers 7 and classes to quickly test out new security ISA extensions. view the instruction at the current IP in binary 8 . The register file As an example, to implement the multiplication operations MUL, displays the values of all 32 registers in decimal, hexadecimal or bi- MULH, MULHU, MULHSU proposed in the RISC-V specification [2], one nary representations. As the IP progresses through the code, some needs to: registers will change values, and this change will be highlighted by changing the background of the appropriate register to red. At (1) Add the MUL, MULH, MULHU, MULHSU to the instructions.js the same time, each new (non-pseudo) instruction will be broken file containing instruction names. down to its 32bit instruction format, shown on the bottom-left side (2) Edit the parser.js file so that these instructions are parsed of Figure 2 8 . The elements in the top row of this table signify the with the two source registers and a destination register. This bitrange of the column. The middle row specifies which part of the requires minimal coding as the registers are already extracted instruction is shown in the column, and changes with instruction by the parser. type, i.e., R-type instructions will have columns funct7, rs2, rs1, (3) Add a new case condition in the emulator.js that on a MUL* funct3, rd, opcode, while I-type instructions will have one less instruction (1) updates the IP by 4, and (2) puts the correct column, as funct7 and rs2 are replaced with imm. multiplication result in the correct register. The emulator On the right column is the memory visualization 9 table. It is already has the registers as local variables, so the user just a descending list with 5 foldable regions: the stack segment, free needs to refer to the appropriate ones. 2 Figure 2: A screenshot of the BRISC-V emulator user interface.

5 CONCLUSION REFERENCES We introduced in this brief the BRISC-V emulator that targets the [1] RISC-V Foundation. 2018. RISC-V Angel Emulator. (2018). https://riscv.org/software-tools/riscv-angel/ RISC-V architecture. The emulator is meant to be used as a teach- [2] "RISC-V Foundation". 2018. RISC-V Specification. (2018). ing tool, as currently many computer organization and computer https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf architecture classes are migrating to RISC-V. The emulator is writ- ten in vanilla javascript, and the user only needs to open an HTML page to use it. It does not require any installation, simplifying class setup as no admin access is needed on student machines. The em- ulator will be made available at the following address upon publica- tion: http://ascslab.org/research/briscv/emulator/emulator.html.

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