PHD34NQ10T N-Channel Trenchmos Standard Level FET Rev

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PHD34NQ10T N-channel TrenchMOS standard level FET Rev. 03 — 14 December 2010 Product data sheet

1. Product profile

1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.

1.2 Features and benefits

Higher operating power due to low Suitable for high frequency thermal resistance applications due to fast switching Low conduction losses due to low characteristics on-state resistance

1.3 Applications

DC-to-DC converters Switched-mode power supplies

1.4 Quick reference data

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175°C--100V

ID drain current Tmb =25°C; VGS =10V--35A

Ptot total power dissipation Tmb =25°C --136W Static characteristics

RDSon drain-source on-state VGS =10V; ID =17A; - 3540mΩ resistance Tj =25°C Dynamic characteristics

QGD gate-drain charge VGS =10V; ID =34A; -18-nC VDS =80V; Tj =25°C NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

2. Pinning information

Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 G gate mb D 2 D drain[1] 3Ssource G mb D mounting base; connected to drain mbb076 S 2 1 3 SOT428 (DPAK)

[1] It is not possible to make connection to pin 2.

3. Ordering information

Table 3. Ordering information Type number Package Name Description Version PHD34NQ10T DPAK plastic single-ended surface-mounted package (DPAK); 3 leads SOT428 (one lead cropped)

4. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V

VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS =20kΩ - 100 V

VGS gate-source voltage -20 20 V

ID drain current VGS =10V; Tmb =25°C - 35 A

VGS =10V; Tmb = 100 °C - 25 A

IDM peak drain current pulsed; Tmb = 25 °C - 140 A

Ptot total power dissipation Tmb = 25 °C - 136 W

Tstg storage temperature -55 175 °C

Tj junction temperature -55 175 °C Source-drain diode

IS source current Tmb =25°C - 35 A

ISM peak source current pulsed; Tmb = 25 °C - 140 A Avalanche ruggedness

EDS(AL)S non-repetitive drain-source avalanche VGS =10V; Tj(init) =25°C; ID =26A; - 170 mJ energy Vsup ≤ 25 V; unclamped; tp = 100 µs; RGS =50Ω

IAS non-repetitive avalanche current Vsup ≤ 25 V; VGS =10V; -35A Tj(init) =25°C; RGS =50Ω; unclamped

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 2 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

003aae599 003aae600 100 100 Pder ID (%) (%) 80 80

60 60

40 40

20 20

0 0 050 100 150 200 050 100 150 200 Tmb (°C) Tmb (°C)

Fig 1. Normalized total power dissipation as a Fig 2. Normalized continuous drain current as a function of mounting base temperature function of mounting base temperature

003aae601 003aae613 103 102 IDM (A) l R = V / I AS DS(on) DS D (A) 102 25 °C tp = 10 μs 10 100 μs 10 Tj prior to avalanche = 150 °C DC 1 ms 10 ms 100 ms 1 1 11010 102 3 10−3 10−2 10−1 1 10 VDS (V) tAV (ms)

Tmb = 25 °C; IDM is single pulse unclamped inductive load Fig 3. Safe operating area; continuous and peak drain Fig 4. Single-shot avalanche rating; avalanche currents as a function of drain-source voltage current as a function of avalanche period

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 3 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

5. Thermal characteristics

Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to --1.1K/W mounting base

Rth(j-a) thermal resistance from junction to mounted on printed-circuit -50-K/W ambient board ; minimum footprint

003aae602 10 Zth(j-mb) (K/W) 1 δ = 0.5

0.2 −1 0.1 10 tp 0.05 P δ = 0.02 T

− 10 2 single pulse

tp t T 10−3 10−6 10−5 10−4 10−3 10−2 10−1 1 tp (s)

Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 4 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

6. Characteristics

Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics

V(BR)DSS drain-source breakdown ID =0.25mA; VGS =0V; Tj =-55°C89--V voltage ID =0.25mA; VGS =0V; Tj = 25 °C 100 - - V

VGS(th) gate-source threshold ID =1mA; VDS =VGS; Tj =-55°C--4.4V voltage ID =1mA; VDS =VGS; Tj =175°C1--V

ID =1mA; VDS =VGS; Tj =25°C234V

IDSS drain leakage current VDS = 100 V; VGS =0V; Tj = 175 °C - - 500 µA

VDS = 100 V; VGS =0V; Tj = 25 °C - 0.05 10 µA

IGSS gate leakage current VGS =10V; VDS =0V; Tj = 25 °C - 10 100 nA

VGS =-10V; VDS =0V; Tj = 25 °C - 10 100 nA

RDSon drain-source on-state VGS =10V; ID =17A; Tj = 175 °C - - 108 mΩ resistance VGS =10V; ID =17A; Tj = 25 °C - 35 40 mΩ Dynamic characteristics

QG(tot) total gate charge ID =34A; VDS =80V; VGS =10V; -40-nC Tj =25°C QGS gate-source charge - 7 - nC

QGD gate-drain charge - 18 - nC

Ciss input capacitance VDS =25V; VGS =0V; f=1MHz; - 1704 - pF Tj =25°C Coss output capacitance - 227 - pF

Crss reverse transfer capacitance - 140 - pF

td(on) turn-on delay time VDS =50V; RL =1.5Ω; VGS =10V; -12-ns RG(ext) =5.6Ω; Tj =25°C tr rise time - 55 - ns

td(off) turn-off delay time - 48 - ns

tf fall time - 38 - ns

LD internal drain inductance measured from mounting base to -3.5-nH centre of die ; Tj =25°C

LS internal source inductance measured from source lead to source -7.5-nH bond pad ; Tj =25°C Source-drain diode

VSD source-drain voltage IS =17A; VGS =0V; Tj = 25 °C - 0.85 1.2 V

trr reverse recovery time IS =17A; dIS/dt = -100 A/µs; -76-ns VGS =0V; VDS =25V; Tj =25°C Qr recovered charge - 0.24 - µC

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 5 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

003aae603 003aae604 50 0.1 I R 4.8 5 5.2 5.4 D V (V) = 10 8 DS(on) (A) GS (Ω) 40 0.08 6

30 0.06 6

5.4 20 0.04 8 5.2 5 10 0.02 VGS (V) = 10 4.8 4.6 4.4 0 0 020.4 0.8 1.2 1.6 05010 20 30 40 VDS (V) ID (A)

Tj = 25 °C Tj = 25 °C Fig 6. Output characteristics: drain current as a Fig 7. Drain-source on-state resistance as a function function of drain-source voltage; typical values of drain current; typical values

003aae605 003aae606 40 30 I D T = 25 °C (A) gfs j (S) 30 Tj = 25 °C Tj = 175 °C 20

20 Tj = 175 °C

10 10

0 0 0102 4 6 8 04010 20 30 VGS (V) ID (A)

VDS > ID x RDSon VDS > ID x RDSon Fig 8. Transfer characteristics: drain current as a Fig 9. Forward transconductance as a function of function of gate-source voltage; typical values drain current; typical values

003aae607 003aae608 2.9 5 VGS(th) a (V) 4 maximum

2.1 3 typical

2 minimum 1.3

0.5 0 −6020 100 180 −6020 100 180 Tj (°C) Tj (°C)

ID = 1 mA; VDS = VGS

Fig 10. Normalized drain-source on-state resistance Fig 11. Gate-source threshold voltage as a function of factor as a function of junction temperature junction temperature

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 6 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

003aae609 003aae610 10−1 104 lD (A) C −2 (pF) 10 Ciss

103 10−3

minimum typical maximum Coss 10−4 102 Crss 10−5

10−6 10 051 234 10−1 1 10 102 VGS (V) VDS (V)

Tj = 25 °C; VDS = VGS VGS = 0 V; f = 1 MHz Fig 12. Sub-threshold drain current as a function of Fig 13. Input, output and reverse transfer capacitances gate-source voltage as a function of drain-source voltage; typical values

003aae611 003aae612 16 50 I VGS F (V) (A) 40 12

V = 20 V V = 80 V DD DD 30 8 20 Tj = 175 °C Tj = 25 °C 4 10

0 0 06020 40 00.4 0.8 1.2 QG (nC) VSDS (V)

Tj = 25 °C; ID = 34 A VGS = 0 V Fig 14. Gate-source voltage as a function of gate Fig 15. Source (diode forward) current as a function of charge; typical values source-drain (diode forward) voltage; typical values

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 7 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

7. Package outline

Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428

E A A

b2 A1 E1

mounting base D2

2 L L2 13 L1

b1 b wAM c

0 5 10 mm scale

DIMENSIONS (mm are the original dimensions) D E L y UNIT AbA bcDb 2 Ee1 e H Lw1 L 1 1 2 1 min min 1 D min 2 max 2.38 0.93 0.89 1.1 5.46 0.56 6.22 6.73 10.4 2.95 0.9 mm 4.0 4.45 2.285 4.57 0.5 0.2 0.2 2.22 0.46 0.71 0.9 5.00 0.20 5.98 6.47 9.6 2.55 0.5

OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 06-02-14 SOT428TO-252 SC-63 06-03-16

Fig 16. Package outline SOT428 (DPAK)

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 8 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

8. Revision history

Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHD34NQ10T v.3 20101214 Product data sheet - PHB_PHD_PHP34NQ10T v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Type number PHD34NQ10T separated from data sheet PHB_PHD_PHP34NQ10T v.2. PHB_PHD_PHP34NQ10T v.2 20031101 Product data sheet - PHB_PHD_PHP34NQ10T v.1

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 9 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

9. Legal information

9.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or Draft — The document is a draft version only. The content is still under safety-critical systems or equipment, nor in applications where failure or internal review and subject to formal approval, which may result in malfunction of an NXP Semiconductors product can reasonably be expected modifications or additions. NXP Semiconductors does not give any to result in personal injury, death or severe property or environmental representations or warranties as to the accuracy or completeness of damage. NXP Semiconductors accepts no liability for inclusion and/or use of information included herein and shall have no liability for the consequences of NXP Semiconductors products in such equipment or applications and use of such information. therefore such inclusion and/or use is at the customer’s own risk.

Short data sheet — A short data sheet is an extract from a full data sheet Quick reference data — The Quick reference data is an extract of the with the same product type number(s) and title. A short data sheet is intended product data given in the Limiting values and Characteristics sections of this for quick reference only and should not be relied upon to contain detailed and document, and as such is not complete, exhaustive or legally binding. full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales Applications — Applications that are described herein for any of these office. In case of any inconsistency or conflict with the short data sheet, the products are for illustrative purposes only. NXP Semiconductors makes no full data sheet shall prevail. representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Customers are responsible for the design and operation of their applications NXP Semiconductors and its customer, unless NXP Semiconductors and and products using NXP Semiconductors products, and NXP Semiconductors customer have explicitly agreed otherwise in writing. In no event however, accepts no liability for any assistance with applications or customer product shall an agreement be valid in which the NXP Semiconductors product is design. It is customer’s sole responsibility to determine whether the NXP deemed to offer functions and qualities beyond those described in the Semiconductors product is suitable and fit for the customer’s applications and Product data sheet. products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their 9.3 Disclaimers applications and products.

Limited warranty and liability — Information in this document is believed to NXP Semiconductors does not accept any liability related to any default, be accurate and reliable. However, NXP Semiconductors does not give any damage, costs or problem which is based on any weakness or default in the representations or warranties, expressed or implied, as to the accuracy or customer’s applications or products, or the application or use by customer’s completeness of such information and shall have no liability for the third party customer(s). Customer is responsible for doing all necessary consequences of use of such information. testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and In no event shall NXP Semiconductors be liable for any indirect, incidental, the products or of the application or use by customer’s third party punitive, special or consequential damages (including - without limitation - lost customer(s). NXP does not accept any liability in this respect. profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such Limiting values — Stress above one or more limiting values (as defined in damages are based on tort (including negligence), warranty, breach of the Absolute Maximum Ratings System of IEC 60134) will cause permanent contract or any other legal theory. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in Notwithstanding any damages that customer might incur for any reason the Recommended operating conditions section (if present) or the whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards Characteristics sections of this document is not warranted. Constant or customer for the products described herein shall be limited in accordance repeated exposure to limiting values will permanently and irreversibly affect with the Terms and conditions of commercial sale of NXP Semiconductors. the quality and reliability of the device.

Right to make changes — NXP Semiconductors reserves the right to make Terms and conditions of commercial sale — NXP Semiconductors changes to information published in this document, including without products are sold subject to the general terms and conditions of commercial limitation specifications and product descriptions, at any time and without sale, as published at http://www.nxp.com/profile/terms, unless otherwise notice. This document supersedes and replaces all information supplied prior agreed in a valid written individual agreement. In case an individual to the publication hereof. agreement is concluded only the terms and conditions of the respective

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 10 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

agreement shall apply. NXP Semiconductors hereby expressly objects to product for such automotive applications, use and specifications, and (b) applying the customer’s general terms and conditions with regard to the whenever customer uses the product for automotive applications beyond purchase of NXP Semiconductors products by customer. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any No offer to sell or license — Nothing in this document may be interpreted or liability, damages or failed product claims resulting from customer design and construed as an offer to sell products that is open for acceptance or the grant, use of the product for automotive applications beyond NXP Semiconductors’ conveyance or implication of any license under any copyrights, patents or standard warranty and NXP Semiconductors’ product specifications. other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may 9.4 Trademarks be subject to export control regulations. Export might require a prior authorization from national authorities. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, the product is not suitable for automotive use. It is neither qualified nor tested FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, in accordance with automotive testing or application requirements. NXP ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, Semiconductors accepts no liability for inclusion and/or use of QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, non-automotive qualified products in automotive equipment or applications. TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

In the event that customer uses the product for design-in and use in HD Radio and HD Radio logo — are trademarks of iBiquity Digital automotive applications to automotive specifications and standards, customer Corporation. (a) shall use the product without NXP Semiconductors’ warranty of the

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

PHD34NQ10T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 December 2010 11 of 12 NXP Semiconductors PHD34NQ10T N-channel TrenchMOS standard level FET

11. Contents

1 Product profile ...... 1 1.1 General description ...... 1 1.2 Features and benefits...... 1 1.3 Applications ...... 1 1.4 Quick reference data ...... 1 2 Pinning information...... 2 3 Ordering information...... 2 4 Limiting values...... 2 5 Thermal characteristics ...... 4 6 Characteristics...... 5 7 Package outline ...... 8 8 Revision history...... 9 9 Legal information...... 10 9.1 Data sheet status ...... 10 9.2 Definitions...... 10 9.3 Disclaimers ...... 10 9.4 Trademarks...... 11 10 Contact information...... 11

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 December 2010 Document identifier: PHD34NQ10T