DOCSLIB.ORG

Ft. Irwin New Express Ft

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Ft. Irwin New Express Ft MECHANICAL/ELECTRICAL MANUAL FOR THE Army & Air Force Exchange Service Ft. Irwin New Express Ft. Irwin, CA PN: 4742-20-000002 Bldg. #973 Facility #4742 0000 000 July 15, 2021 100% Construction Documents Architects West PN: 20014 Signatures: Project Manager _____________________________________ Date ____________________ Contracting Officer ___________________________________ Date ____________________ Architect ___________________________________________ Date ____________________ Contractor __________________________________________ Date ____________________ MECHANICAL/ELECTRICAL MANUAL ARMY & AIR FORCE EXCHANGE SERVICE Ft. Irwin Express PN: 4742-20-000002 Bldg. #973 Facility #4742 0000 000 EXCHANGE PROJECT MANAGER: David Ivey 3911 S. Walton Walker Blvd. Dallas, TX 75236 (214) 312-4727 Architect: Architects West, INC 210 E. Lakeside Ave. Coeur d’ Alene, ID 83814 Ph (208) 667-9402 Structural, Mechanical, Electrical, Civil Engineer: & Fire Protection Engineer: DCI Engineers Coffman Engineers 707 W 2nd Ave. 10 N. Post St., Ste. 500 Spokane, WA 99201 Spokane, WA 99201 Ph (509) 455-4448 Ph (509) 328-2994; Fx (509) 328-2999 AW #20014 July 15, 2021 Mechanical Specifications for ARMY & AIR FORCE EXCHANGE SERVICE Ft. Irwin Express PN: 4742-20-000002 Bldg # 973 Facility # 4742 0000 000 MECHANICAL ENGINEER: COFFMAN ENGINEERS 10 N. Post Street, Ste. 500 Spokane, WA 99201 Ph (509) 328-2994; Fx (509) 328-2999 07/15/2021 MECHANICAL TABLE OF CONTENTS DIVISION 22 – SPECIFICATIONS 22 00 00 - Plumbing General Provisions 22 05 00 - Common Work Results for Plumbing 22 05 19 - Meters and Gages for Plumbing 22 05 23 - General-Duty Valves for Plumbing Piping 22 05 29 - Hangers and Supports for Plumbing Piping Equipment 22 05 53 - Identification for Plumbing Piping and Equipment 22 07 00 - Plumbing Insulation 22 11 16 - Domestic Water Piping 22 11 19 - Domestic Water Piping Specialties 22 13 16 - Sanitary Waste and Vent Piping 22 13 19 - Sanitary Waste Piping Specialties 22 14 13 - Facility Storm Drainage Piping 22 14 23 - Storm Drainage Piping Specialties 22 34 00 - Fuel-Fired Domestic Water Heaters 22 40 00 - Plumbing Fixtures DIVISION 23 – SPECIFICATIONS 23 00 00 - HVAC General Provisions 23 05 48 - Vibration and Seismic Controls for Plumbing Piping and HVAC Equipment 23 05 53 - Identification for HVAC Piping and Equipment 23 05 93 - Testing, Adjusting, and Balancing for HVAC 23 07 00 - HVAC Insulation 23 09 00 - Instrumentation and Controls for HVAC 23 11 26 - Liquified Petroleum Gas Piping 23 31 13 - Metal Ducts 23 33 00 - Air Duct Accessories 23 34 23 - HVAC Power Ventilators 23 37 13 - Diffusers, Registers, and Grilles 23 74 13 -Packaged, Outdoor, Rooftop Units END OF TABLE OF CONTENTS 07/15/21 MECHANICAL TABLE OF CONTENTS Ft. Irwin Express (20014) 000100 - 1 SECTION 22 00 00 - PLUMBING – GENERAL PROVISIONS PART 1 - GENERAL 1.1 CONDITIONS AND REQUIREMENTS A. Refer to BIDDING REQUIREMENTS, CONDITIONS OF THE CONTRACT, SUPPLEMENTARY CONDITIONS and DIVISION 01 of these specifications, which govern work under DIVISION 23. Refer to other sections of these specifications for additional related requirements. 1.2 SCOPE OF REQUIREMENTS A. The work covered by Division 22 of the specifications shall include but not be limited to: 1. Furnishing all materials and supplying all labor, equipment and services to install the complete mechanical system as shown on the accompanied drawings and specified herein. 1.3 DESCRIPTION OF WORK A. The contract documents including specifications and construction drawings are intended to provide all material and labor to install complete plumbing, heating ventilating and air conditioning systems for the building. B. Every effort has been made on the design to meet or exceed the minimum requirements of the Codes; therefore, unless Contractor before signing his Contract, shall have notified the Architect, in writing, of any items in conflict with said Codes, he shall thereafter make any minor adjustments necessary to meet said Codes at no cost to the Owner. C. The Contractor shall refer to the architectural interior detail, floor plans, elevations, and the structural and other Contract Drawings and he shall coordinate his work with that of the other trades to avoid interference. The plans are diagrammatic and show generally the locations of the equipment and are not to be scaled; all dimensions shall be checked at the building. D. The Contractor shall comply with the project close-out requirements as detailed in General Requirements of Division 01. 1.4 DESCRIPTION OF BID DOCUMENTS A. Specifications: 1. Specifications, in general, describe quality and character of materials and equipment. 2. Specifications are of simplified form and include incomplete sentences. B. Drawings: 1. Drawings in general are diagrammatic and indicate sizes, locations, connections to equipment and methods of installation. 2. Scaled and figured dimensions are approximate and are for estimating purposes only. 07/15/21 Plumbing – General Provisions Ft. Irwin Express (20014) 220000 - 1 3. Before proceeding with work check and verify all dimensions. 4. Assume all responsibility for fitting of materials and equipment to other parts of equipment and structure. 5. Make adjustments that may be necessary or requested in order to resolve space problems, preserve headroom, and avoid architectural openings, structural members and work of other trades. 6. If any part of Specifications or Drawings appears unclear or contradictory, apply to Architect or Engineer for his interpretation and decision as early as possible. 1.5 CODES PERMITS AND FEES A. Mechanical work shall be in accordance with the following: 1. The Contractor at his expense shall obtain permits and inspections required for the mechanical work on this project. Deliver all inspection certificates to the Owner’s Representative prior to final acceptance of the work. 2. Contractor shall pay all costs levied by utility companies and/or governing agencies associated with gas connections and include these costs within his bid. This shall include but not be limited to tap fees, service mains, meter, and vault charges. 1.6 DEFINITIONS A. The terms “The Contractor”, when used in Division 22 shall mean the Contractor for mechanical work. B. The term “Owners Representative” as used in Division 22 generally refers to the Architect or his designated representative in accordance with the General Conditions. C. The term “Provide” shall mean furnish and install. 1.7 TEMPORARY HEATING A. See Section 015000 Temporary Facilities and Controls. 1.8 SAFETY AND PROTECTION A. Safety Measures: The Engineer has not been retained to provide design and construction services relating to the Contractor’s safety precautions, or means, methods, techniques, sequences or procedures required for the Contractor to perform his work. The Contractor shall be solely and completely responsible for conditions of the job site, including safety of all persons and property during performance of the work. This requirement applies continuously and is not limited to normal working hours. Provide all required safety measures and consult with the State or Federal safety inspector for interpretation whenever in doubt as to whether safe conditions do or do not exist or whether compliance with State or Federal regulations exist. B. Head protection: Where pipe hangers, equipment support angles, etc., are exposed in access ways for any maintenance, cover all such potentially injurious protrusions less than 7’-0” above the floor with padding; secure and permanently fasten, and finish to match adjacent finishes. 07/15/21 Plumbing – General Provisions Ft. Irwin Express (20014) 220000 - 2 1.9 MECHANICAL COST BREAKDOWN A. Cost breakdown not required. 1.10 GUARANTEE A. The Mechanical equipment and installation shall be guaranteed for a period of one (1) year from the date of acceptance unless and individual item or specification is otherwise noted as longer. The Contractor shall make-good at his own expense all defects in his work, and/or equipment furnished by him, which shall develop at any time during the one year guarantee period and shall stand any expense of cutting and patching and repairing made necessary by his corrections of unsatisfactory work or equipment operation. PART 2 - PRODUCTS 2.1 DUCTWORK AND PIPING COORDINATION A. Prior to installation of the new Division 22 systems, the Contractor shall coordinate the proposed installation with the Architectural and Structural requirements, and all other trades (including HVAC, Plumbing, Fire Protection, Electrical, Ceiling Suspension and Tile systems), and provide reasonable maintenance access requirements. B. Provide means of access to all valves, dampers, controllers, operable devices and other apparatus which may require adjustment or servicing. C. Verify in field exact size, location, invert, and clearances regarding all existing material, equipment and apparatus, and advise the Owners Representative of any discrepancies between that indicated on the Drawings and that existing in the field prior to any installation. Contractor shall be responsible for all costs associated with the removal or relocation of installed systems that have been installed without prior notification of the Owners Representative. 2.2 SHOP DRAWINGS AND SUBMITTALS A. Submit Shop Drawings and Product Data per the requirements of Section 013300 Submittals Procedures. B. See individual Division 22 specification sections for additional submittal requirements. C. Submittals of Product Data shall be bound in a black 3-ring binder with
Load more

Recommended publications
  • Software Problems of an Experimental Robot
    PERIODICA POLITECHHICA SER EL ENG. VOL 46, NO J-J. PP. 151-16112002) SOFTWARE PROBLEMS OF AN EXPERIMENTAL ROBOT CONTROLLER BASED ON QNX REAL-TIME OPERATING SYSTEMS Istvan OLAH and Gdbor TEVESZ Department of Auiomation and Applied Informatics Budapest University of Technology and Economics H-l 111 Budapest, Goldmann Gyorgy tc"r 3. Hungary Phone: (+36-1)463-2870, Fax: (436-1)463-2871 e-mail: [email protected]; [email protected] Received: July 1,2003 Abstract At the Department of Automation and Applied Informatics an experimental robot control system has been developed. The purpose of this research is to study modern robot control algorithms and their realization in a real environment. The project focuses on the problems of multiprocessor systems including the task distribution and communication. Another field of this research is to integrate a six-component forcc-torquc sensor into the robot control system and making use of this information in new robot control algorithms. Another purpose of this study is to examine the software problems of an IBM PC-based multiprocessor system controlling a NOKIA-PUMA 560 humanoid robot arm. The features and system services of the new QNX Neutrino operating system is presented in comparison with the previously used QNX v4. The main areas of the version upgrade will be shown focusing on the interprocess communication questions. The processing components of this multiprocessor robot control system with its external interfaces will be discussed later and some further system level development possibilities will be outlined. This final part of the study gives the summary of the architectural and communication requirements of a hybrid position and force control system in the above environment.
    [Show full text]
  • Μc/OS-II User's Manual 1
    µC/OS-II TM The Real-Time Kernel User’s Manual Jean J. Labrosse Weston, FL 33326 µC/OS-II User's Manual 1. µC/OS-II User Manual . 2 1.1 Preface . 3 1.2 Getting Started with µC/OS-II . 8 1.3 Real-Time Systems Concepts . 45 1.4 Kernel Structure . 94 1.5 Task Management . 151 1.6 Time Management . 183 1.7 Timer Management . 193 1.8 Event Control Blocks . 205 1.9 Semaphore Management . 219 1.10 Mutual Exclusion Semaphores . 235 1.11 Event Flag Management . 256 1.12 Message Mailbox Management . 285 1.13 Message Queue Management . 305 1.14 Memory Management . 333 1.15 Porting µC/OS-II . 350 1.16 80x86 Port with Emulated FP Support . 413 1.17 80x86 Port with Hardware FP Support . 460 1.18 Thread Safety of the Compiler’s Run-Time Library . 492 1.19 µC/OS-II API Reference . 500 1.20 µC/OS-II Configuration Manual . 670 1.21 PC Services . 697 1.22 C Coding Conventions . 724 1.23 Licensing Policy for µC/OS-II . 739 1.24 µC/OS-II Quick Reference . 740 1.25 TO Utility . 750 1.26 Bibliography . 752 µC/OS-II User Manual µC/OS-II User's Manual µC/OS-II User Manual This book describes the design and implementation of µC/OS-II (pronounced “Micro C O S 2”), which stands for Micro-Controller Operating System Version 2. µC/OS-II is a completely portable, ROMable, scalable, preemptive, real-time, multitasking kernel. µC/OS-II is written in ANSI C and contains a small portion of assembly language code to adapt it to different processor architectures.
    [Show full text]
  • CV Full Version
    CURRICULUM VITAE M C Willett Name : Mike Willett Online CV at : http://vsmt.21-dc.com Address : 16011 Arenzano (GE), Italy. Poole, Dorset, BH16 5LF, England Telephone : t. +44 1212 886044 (24/7) m. +39 348 002 0847 E-mail : [email protected] Nr. of Years in Industry : 39 years Nationality : English Marital Status : Married with a son. Date of Birth : 6th October 1960 Languages : Italian and basic German. Summary of Experience I have over 30 years of embedded software experience and consider myself an expert in developing real-time embedded software using the C programming language. When I refer to real-time embedded software, I mean true multi-tasking software on a proper pre-emptive operating system with interfaces to the event driven world of hardware control and user interfaces. I have in-depth knowledge of device drivers, software control of system hardware components and product specific electro-mechanical devices. Additionally, I have a good understanding of hardware at the device level. I also have enthusiasm and expertise in requirements capture and specification. Key to any project is communication and I feel this is something that I am good at both in the written and spoken word – most importantly, I enjoy helping to bring clarity and visibility to a project, a pre- requisite for success. Specialist Skills Real-time, multi-tasking operating systems and device drivers for embedded products. Software development, firmware and 'bare metal' programming. SoCs and ASICs. Software architecture, technical auditing, project management of full product lifestyle, SW porting and reverse/re-engineering. Excellent communicator and documentation skills.
    [Show full text]
  • Intel80386ex Emulator/Analyzer Installation/Service
    Installation/Service/Terminal Interface Guide Intel80386EX Emulator/Analyzer (HP 64789B) Notice Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material. Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Hewlett-Packard. © Copyright 1995, 1996 Hewlett-Packard Company. This document contains proprietary information, which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced or translated to another language without the prior written consent of Hewlett-Packard Company. The information contained in this document is subject to change without notice. UNIX(R) is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company Limited. Intel386, Intel80386, Intel486, and Intel80486 are U.S. trademarks of Intel Corporation. Hewlett-Packard Company P.O. Box 2197 1900 Garden of the Gods Road Colorado Springs, CO 80901-2197, U.S.A. RESTRICTED RIGHTS LEGEND. Use, duplication, or disclosure by the U.S. Government is subject to restrictions set forth in subparagraph (C) (1) (ii) of the Rights in Technical Data and Computer Software Clause at DFARS 252.227-7013. Hewlett-Packard Company, 3000 Hanover Street, Palo Alto, CA 94304 U.S.A. Rights for non-DOD U.S. Government Departments and Agencies are as set forth in FAR 52.227-19(c)(1,2).
    [Show full text]
  • 4. Instruction Tables Lists of Instruction Latencies, Throughputs and Micro-Operation Breakdowns for Intel, AMD and VIA Cpus
    Introduction 4. Instruction tables Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs By Agner Fog. Technical University of Denmark. Copyright © 1996 – 2016. Last updated 2016-01-09. Introduction This is the fourth in a series of five manuals: 1. Optimizing software in C++: An optimization guide for Windows, Linux and Mac platforms. 2. Optimizing subroutines in assembly language: An optimization guide for x86 platforms. 3. The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers. 4. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs. 5. Calling conventions for different C++ compilers and operating systems. The latest versions of these manuals are always available from www.agner.org/optimize. Copyright conditions are listed below. The present manual contains tables of instruction latencies, throughputs and micro-operation breakdown and other tables for x86 family microprocessors from Intel, AMD and VIA. The figures in the instruction tables represent the results of my measurements rather than the offi- cial values published by microprocessor vendors. Some values in my tables are higher or lower than the values published elsewhere. The discrepancies can be explained by the following factors: ● My figures are experimental values while figures published by microprocessor vendors may be based on theory or simulations. ● My figures are obtained with a particular test method under particular conditions. It is possible that different values can be obtained under other conditions. ● Some latencies are difficult or impossible to measure accurately, especially for memory access and type conversions that cannot be chained.
    [Show full text]
  • ~ ARTISAN® with Experienced Engineers and Technicians on Staff
    Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Honeywell / BendixKing 200-08825-0000 at our website: Click HERE MAINTENANCE MANUAL KLN 94 GPS NAVIGATION SYSTEM MANUAL NUMBER 006-15599-0000 REVISION 0 SEPTEMBER, 2000 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com MAINTENANCE MANUAL KLN 94 GPS NAVIGATION SYSTEM Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com The binder(s) required to hold this publication(s) are available at an additional cost and may be ordered from: Honeywell One Technology Center 23500 West 105th Street Olathe, Kansas, 66061 Telephone 1-800-757-8999 Orders must specify part number, description, and the quantity. Use the following list to complete the order PART NUMBER DESCRIPTION 006-03140-0001 (1) inch Binder. 006-03140-0002 (1.5) inch Binder. 006-03140-0003 (2) inch Binder. 006-03140-0004 (3) inch Binder. 006-03140-0005 (4) inch Post Binder. WARNING Prior to the export of this document, review for export license requirement is needed.
    [Show full text]
  • Intel80386ex Emulator/Analyzer Installation/Service/Terminal
    About this Manual We’ve added this manual to the Agilent website in an effort to help you support your product. This manual is the best copy we could find; it may be incomplete or contain dated information. If we find a more recent copy in the future, we will add it to the Agilent website. Support for Your Product Agilent no longer sells or supports this product. Our service centers may be able to perform calibration if no repair parts are needed, but no other support from Agilent is available. You will find any other available product information on the Agilent Test & Measurement website, www.tm.agilent.com. HP References in this Manual This manual may contain references to HP or Hewlett-Packard. Please note that Hewlett-Packard's former test and measurement, semiconductor products and chemical analysis businesses are now part of Agilent Technologies. We have made no changes to this manual copy. In other documentation, to reduce potential confusion, the only change to product numbers and names has been in the company name prefix: where a product number/name was HP XXXX the current name/number is now Agilent XXXX. For example, model number HP8648A is now model number Agilent 8648A. Installation/Service/Terminal Interface Guide Intel80386EX Emulator/Analyzer (HP 64789B) Notice Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material.
    [Show full text]
  • Random and Exhaustive Testing of Instruction Parsers
    Random and Exhaustive Testing of Instruction Parsers Nathan Jay Paradyn Project Scalable Tools Workshop Granlibakken, California August 2016 Motivation Lots of tools parse binaries GNU Instruction Parser Testing 2 Motivation Parsers rely on a disassembly step: Converting object code into a higher-level language with semantic information Hex Assembly 00: 55 push %rbp 01: 48 89 e5 mov %rsp, %rbp 04: 89 7d fc mov %edi, -0x4(%rbp) 07: 8b 45 fc mov –x4(%rbp), %eax 0a: 83 c0 0a add $0xa, %eax 0d: 0f af 45 fc imul –x04(%rpb), %eax 11: 5d pop %rbp 12: c3 retq Instruction Parser Testing 3 Motivation Size field Operation Converting object code to assembly is Immediate easy for a single format, like this from Source Register Dest. Register ARMv8: Condition Fixed Value Compare and branch (immediate) No single format is difficult to decode. Just extract the fields and translate binary to assembly for each field. Instruction Parser Testing 4 Motivation Size field Operation Unfortunately, the format varies between Immediate instructions. Source Register Dest. Register Condition Fixed Value Compare and branch (immediate) Test and branch (immediate) Conditional branch (immediate) Instruction Parser Testing 5 Motivation Size field Operation And there are a lot of formats: Immediate Source Register Dest. Register Condition Fixed Value Instruction Parser Testing 6 Motivation These formats only partially cover: o load/store o branching The manual specifies more than 5 times as many different, general formats. ARM can vary between implementations: Apple, Samsung, AMD, Nvidia, Broadcom, Applied Micro, Huawei, Cavium… Instruction Parser Testing 7 Motivation x86 has other challenges with variable length instructions.
    [Show full text]
  • Jeffrey R. Stone Wilton Softworks
    Jeffrey R. Stone Wilton Softworks Consulting Software Engineer Specializing in Embedded Real-time, Scientific and Industrial Applications 41 Tremont St. · Wilton, NH 03086 (603) 654-2994 [email protected] Member: Consultants' Consortium ____________________________________________________ Summary of Experience Technologies: Ion Mobility Spectrometry AWK Embedded Real-Time Electro-Medical Devices FORTRAN and variants Systems FDA Good Development- BASIC Event-driven Systems Procedures Guidelines Most assembly languages Multitasking Systems Model-Based Software- Data Acquisition Engineering Hardware: Digital Filtering IBM PCs and compatibles Neural Networks Operating Systems: Intel 80x86 family Automated Measurement AT&T Unix System-V Analog Devices ADMC- Speech Synthesis MS Windows XP, 2000, 300 DSP Laser Ablation NT, 95, 3.1, MS-DOS NSC-32000 Sonar DEC OS/8, RT-11, RSX- Sun 50 work-station Gas Chromatography 11/M,M+, RSTS/E, Motorola MC68000 (NCR Capillary Electrophoresis VAX/VMS, ULTRIX Tower) Pneumatic Controls DGC RTOS, RDOS DEC PDP /7, /8, /9, /11, Thin-film Fabrication & Kadak AMX Micro-VAX-II Testing Phar Lap ETS DGC Nova, Nova 1200 DNA- and Peptide- AVR micro-controllers Synthesis Languages: C, C++, MS Visual C++ ____________________________________ Consulting Experience January 1975 - Present: Independent software consultant on projects including the following: Monadnock Art X Tech, Peterborough, NH, 8/15 – present Conduct classes/workshops for hobbyists in use & programming of Arduino/AVR-based monitoring and control devices for home automation. Select & purchase hardware components. Design, write, prototype hardware software, and lesson-plans for class-work. (AVR, C++, Thermal measurement, Internet connectivity, external device control, ArduinoIDE) Wilton Softworks, Wilton, NH, 4/11 – present Software and hardware development for AVR-based monitoring and control devices.
    [Show full text]
  • Hardware Is the New Software
    Hardware is the new software Andrew Baumann, Microsoft Research Abstract 10,000 2.5 2 Moore’s Law may be slowing, but, perhaps as a result, 1,000 other measures of processor complexity are only acceler- 1.5 ating. In recent years, Intel’s architects have turned to an 100 alphabet soup of instruction set extensions such as MPX, 1 SGX, MPK, and CET as a way to sell CPUs through new 10 (millions) Words security features. Unlike prior extensions, which mostly (millions) Transistors CPU transistor count 0.5 focused on accelerating user-mode data processing, these Words in architecture manual new features exhibit complex interactions and give system 1 0 designers plenty to think about. 1999 2003 2007 2011 2015 This calls for a rethink of how we approach the instruc- tion set. In this paper we highlight some of the challenges Figure 1: Complexity growth of Intel x86 CPUs and ISA arising from recent security-focused extensions, and spec- ulate about the longer-term implications. complex interactions with other extensions and prior ar- chitectural features. 1 Introduction We take a detailed look at two of the most complex re- cent extensions: software guard extensions (SGX, x3) and An instruction set architecture (ISA) is the key interface control-flow enforcement technology (CET, x4), before between the lowest-levels of software and the CPU. The deriving some implications for systems developers and re- x86 ISA is a complex but enduring set of semantics for in- searchers (x5). We argue that these extensions are now structions, registers, memory, and core devices that must approaching software-like levels of complexity, yet carry be respected by CPUs, emulators and virtual machines, all the attendant drawbacks of a hardware implementation and all the software that runs on top.
    [Show full text]
  • 4. Instruction Tables Lists of Instruction Latencies, Throughputs and Micro-Operation Breakdowns for Intel, AMD, and VIA Cpus
    Introduction 4. Instruction tables Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD, and VIA CPUs By Agner Fog. Technical University of Denmark. Copyright © 1996 – 2021. Last updated 2021-08-17. Introduction This is the fourth in a series of five manuals: 1. Optimizing software in C++: An optimization guide for Windows, Linux, and Mac platforms. 2. Optimizing subroutines in assembly language: An optimization guide for x86 platforms. 3. The microarchitecture of Intel, AMD, and VIA CPUs: An optimization guide for assembly programmers and compiler makers. 4. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD, and VIA CPUs. 5. Calling conventions for different C++ compilers and operating systems. The latest versions of these manuals are always available from www.agner.org/optimize. Copyright conditions are listed below. The present manual contains tables of instruction latencies, throughputs and micro-operation breakdown and other tables for x86 family microprocessors from Intel, AMD, and VIA. The figures in the instruction tables represent the results of my measurements rather than the offi- cial values published by microprocessor vendors. Some values in my tables are higher or lower than the values published elsewhere. The discrepancies can be explained by the following factors: ● My figures are experimental values while figures published by microprocessor vendors may be based on theory or simulations. ● My figures are obtained with a particular test method under particular conditions. It is possible that different values can be obtained under other conditions. ● Some latencies are difficult or impossible to measure accurately, especially for memory access and type conversions that cannot be chained.
    [Show full text]
  • A Study on the Impact of Instruction Set Architectures on Processor's
    Western Michigan University ScholarWorks at WMU Master's Theses Graduate College 8-2017 A Study on the Impact of Instruction Set Architectures on Processor’s Performance Ayaz Akram Follow this and additional works at: https://scholarworks.wmich.edu/masters_theses Part of the Electrical and Computer Engineering Commons Recommended Citation Akram, Ayaz, "A Study on the Impact of Instruction Set Architectures on Processor’s Performance" (2017). Master's Theses. 1519. https://scholarworks.wmich.edu/masters_theses/1519 This Masters Thesis-Open Access is brought to you for free and open access by the Graduate College at ScholarWorks at WMU. It has been accepted for inclusion in Master's Theses by an authorized administrator of ScholarWorks at WMU. For more information, please contact [email protected]. A Study on the Impact of Instruction Set Architectures on Processor’s Performance by Ayaz Akram A thesis submitted to the Graduate College in partial fulfillment of the requirements for the degree ofMaster of Science in Emgineering Electrical and Computer Engineering Western Michigan University August 2017 Thesis Commitee: Dr. Lina Sawalha, Chair Dr. Janos Grantner Dr. Steven Carr A Study on the Impact of Instruction Set Architectures on Processor’s Performance Ayaz Akram, M.S.E. Western Michigan University, 2017 The recent advances in different instruction set architectures (ISAs) and the way those ISAs are implemented have revived the debate on the role of ISAs in overall performance of a processor. Many people in the computer architecture community believe that with current compiler and microarchitecture advances, the choice of ISA does not remain a decisive matter anymore.
    [Show full text]