Intel Celeron /Intel Pentium III Processor

Intel® Celeron®/Intel® Pentium® III Processor - Low Power/Ultra Low Power (BGA2) and Intel® 815E Chipset

Design Guide

May 2002

Document Number: 273630-001 Introduction

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2 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Introduction

Revision History

Rev. No. Description Rev. Date

001 Initial Release May 2002

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 3 Introduction

Table of Contents

1 Introduction ...... 5 1.1 Audience...... 5 1.2 Notation and Terminology ...... 6 1.3 Reference Documents...... 8 2 General Design Considerations ...... 9 2.1 Nominal Board Stack-up ...... 9 3 Processor Host Bus Design ...... 10 3.1 Initial Timing Analysis ...... 10 3.2 General Topology and Layout Guidelines...... 13 3.3 Simulation Methodology...... 13 3.3.1 Pre-Layout Simulation...... 13 3.3.2 Post-Layout Simulation ...... 14 3.4 Layout Rules for GTL+ Signals ...... 14 3.5 Layout Rules for Non-GTL+ (CMOS) Signals ...... 16 3.5.1 Additional Routing and Placement Considerations ...... 16 3.6 Undershoot/Overshoot Requirements...... 16 3.7 Processor Reset Requirements...... 17 3.8 Debug Port Routing Guidelines ...... 18 3.9 PLL Filter Recommendations...... 19 3.9.1 Topology...... 19 3.9.2 Filter Specification ...... 21 3.10 Decoupling Guidelines for BGA2-based Processors ...... 23 3.11 Catastrophic Thermal Protection ...... 23 4 Clocking...... 24 4.1 General Clocking Considerations ...... 24 4.2 Single-Ended Host Bus Clocking Routing...... 24 4.2.1 CLKREF Filter Implementation...... 26 4.2.2 Single-Ended Clocking BSEL[1:0] Implementation ...... 27 4.2.3 Clock Driver Decoupling and Power Delivery ...... 27 5 Processor Host Bus Design Checklist...... 28 5.1 Introduction...... 28 5.2 GTL+ Checklist ...... 28 5.2.1 CMOS (Non-GTL+) Checklist...... 29 5.3 TAP Checklist ...... 29 5.3.1 Miscellaneous Checklist ...... 30 6 Reference Schematic...... 31

4 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Introduction

1 Introduction

This document provides design guidelines for developing systems based on the Intel® Celeron® Processor – Low Power or Ultra Low Power or Intel® Pentium® III - Low Power in a BGA2 packageandtheIntel® 815E chipset. Special design recommendations and concerns are presented. Likely design errors have been listed here in a checklist format. These are recommendations only.

These design guidelines and recommendations have been simulated and validated and strongly recommended to meet the timing and signal quality specifications. It is recommended that simulations be performed to meet design-specific requirements.

Note: The system bus speed supported by the design is based on the capabilities of the processor, chipset, and clock driver.

1.1 Audience

This document is intended to be used by Intel® Celeron® or Intel® Pentium® III – LP/ULP/815E system developers.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 5 Introduction

1.2 Notation and Terminology

This section describes some of the terms used in this document.

Term Description

AGP Accelerated Graphics Port

GTL+ Refers to processor bus signals that are implemented open drain GTL+ interface signal.

Bus Agent A component or group of components that, when combined, represent a single load on the AGTL bus.

Crosstalk The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks. • Backward Crosstalk–coupling that creates a signal in a victim network that travels in the opposite direction as the aggressor signal. • Forward Crosstalk–coupling that creates a signal in a victim network that travels in the same direction as the aggressor signal. • Even Mode Crosstalk–coupling from single or multiple aggressors when all the aggressors switch in the same direction that the victim is switching. • Odd Mode Crosstalk–coupling from single or multiple aggressors when all the aggressors switch in the opposite direction that the victim is switching.

GMCH Graphics and Memory Controller Hub. A component of the Intel® 815 chipset platform for use with Intel® Pentium III-Low Power and Intel® Celeron-Ultra Low Power/Low Power

ICH2 Intel® 82801BA I/O Controller Hub component.

ISI Inter-symbol interference is the effect of a previous signal (or transition) on the interconnect delay. For example, when a signal is transmitted down a line and the reflections due to the transition have not completely dissipated, the following data transition launched onto the bus is affected. ISI is dependent upon frequency, time delay of the line, and the reflection coefficient at the driver and receiver. ISI can impact both timing and signal integrity.

Network Length The distance between agent 0 pins and the agent pins at the far end of the bus.

Pad The electrical contact point of a semiconductor die to the package substrate. A pad is only observable in simulation.

Pin The contact point of a component package to the traces on a substrate such as the motherboard. Signal quality and timings can be measured at the pin.

Ringback The voltage that a signal rings back to after achieving its maximum absolute value. Ringback may be due to reflections, driver oscillations, or other transmission line phenomena.

Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of bus agent in the system.

6 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Introduction

Term Description

SSO Simultaneous Switching Output (SSO) Effects refers to the difference in electrical timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., low-to-high) or in the same direction (e.g., high-to-low). These are respectively called odd-mode switching and even-mode switching. This simultaneous switching of multiple outputs creates higher current swings that may cause additional propagation delay (or “push-out”), or a decrease in propagation delay (or “pull-in”). These SSO effects may impact the setup and/or hold times and are not always taken into account by simulations. System timing budgets need to include margin for SSO effects.

Stub The branch from the bus trunk terminating at the pad of an agent.

System Bus The system bus is the processor bus.

Trunk The main connection, excluding interconnect branches, from one end agent pad to the other end agent pad.

Undershoot Minimum voltage observed for a signal to extend below VSS at the device pad.

Victim A network that receives a coupled crosstalk signal from another network is called the victim network.

In this document, a ‘#’ symbol after a signal name identifies the signal as active low; that is, a signal that is in the active state, based on the name of the signal, when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a non-maskable interrupt has occurred. When a signal name does not imply an active state, a # symbol indicates that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

The term “BGA2-based processor(s)” refers to the Intel® Celeron® processor-Ultra Low Power and Low Power in a BGA2 package and the Intel® Pentium® III processor-Low Power in a BGA2 package.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 7 Introduction

1.3 Reference Documents

The reader of this document needs to be familiar with the material and concepts presented in the following documents.

Document Document Number / Location

Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for 298351 use with the Universal Socket 370 Datasheet

Intel® 82802AB/82802AC Firmware Hub (FWH) Datasheet 290658

Intel® 82801BA I/O Controller Hub (ICH2) and Intel® 82801BAM I/O Controller Hub 290687 (ICH2-M) Datasheet

Intel® Pentium® III Processor-Low Power Datasheet 273500

Intel® Celeron® Processor-Ultra Low Power/Low Power Datasheet 273509

Intel® 815EM Chipset: 82815EM Graphics and Memory Controller Hub (GMCH2- 290689 M)

Intel® 815EM Chipset Platform Design Guide 298241

Intel® 815E Chipset Platform Design Guide 298234

Intel® 815E Chipset Platform For Use With Universal Socket 370 Design Guide 298350

Accelerated Graphics Port Interface Specification, Revision 2.0

PCI Local Bus Specification, Revision 2.2

AC’97 2.1 Specification http://developer.intel.co m/pc- supp/platform/ac97/inde x.htm.

82562EH HomePNA 1 Mb/s Physical Layer Interface Datasheet (Doc # 278313) http://developer.intel.co m

82562EH HomePNA 1 Mb/s Physical Layer Interface Brief Datasheet (Doc # 278314) http://developer.intel.co m

Communication Network Riser Specification, Revision 1.1 http://developer.intel.co m/technology/cnr/

Universal Serial Bus, Revision 1.0 Specification

8 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide General Design Considerations

2 General Design Considerations

This section documents the example of a nominal board stack up for BGA2-based processor with the 815E platform. Make sure the impedance for all signal layers is 60 Ω±15%. That is, the impedance of the trace when not subjected to fields created by changing current in neighboring traces. When calculating flight times, it is important to consider the minimum and maximum impedance of a trace, based on the switching of neighboring traces. The use of wider spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce crosstalk and settling time. Coupling between two traces is a function of the coupled length, the distance separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects of trace-to-trace coupling, follow the routing guidelines documented in this section. The routing guidelines in this design guide have been created using a PCB stack-up similar to that in Figure 1. When this stack-up is not used, thorough simulations of every interface must be completed. Using a thicker dielectric (prepreg) makes routing very difficult or impossible. 2.1 Nominal Board Stack-up

The BGA2-based processor/815E platform requires a board stack-up yielding a target impedance of 60 Ω ± 15% with a 5 mil nominal trace width. Figure 1 shows an example stack-up achieving this. It is a 6-layer printed circuit board (PCB) construction using 53%-resin FR4 material.

Figure 1. Board Construction Example for 60 Ω Nominal Stack-up

Signal/Power plane layer ½ oz Cu., 1 oz Plating Prepreg = 3 mils Ground Layer 1 oz Cu. Core = 6 mils Signal layer 1 oz Cu. Total thickness: Prepreg = 34 mils 62 mils Signal layer 1 oz Cu. Core = 6 mils Ground layer 1 oz Cu. Prepreg =3 mils Signal/Power layer ½ oz Cu., 1 oz Plating

Dieletric Constant for FR4 = 4.2 4 mils trace width for outer layers gives a 50 Ω signal impedance. 5 mils trace width for inner layers gives a 60 Ω signal impedance

Additional guidelines on board stack-up, placement, and layout include the following. − The board impedance (Z) is 60 Ω ± 15%. − The dielectric process variation in the PCB fabrication is minimized. − The ground plane is not split on the ground plane layer. − Keep vias for decoupling capacitors as close to the capacitor pads as possible.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 9 Processor Host Bus Design

3 Processor Host Bus Design

This section documents the layout and routing guidelines using the BGA2-based processor with the Intel® 815E chipset platform. The solution covers system bus speeds of 100 MHz only. The processor must also be configured to 56.2 Ω ± 1% on-die termination. The document does not discuss the functional aspect of any bus or the layout guideline for an add-in device. When the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations be completed for each design. Even when the guidelines are followed, simulate critical signals to ensure proper signal integrity and flight time. As bus speeds increase, it is imperative that the guidelines documented are followed precisely. Simulate any deviation from these guidelines. 3.1 Initial Timing Analysis

To determine the available flight time window, perform an initial timing analysis. Analysis of setup and hold conditions determine the minimum and maximum flight time bounds for the system bus. Use the following equations to establish the system flight time limits. Table 1. System Timing Equations Equation

Tflight,min >= Thold –Tco,min +Tskew

Tflight,max <= Tcycle –Tco,max –Tsu –Tskew –Tjit –Tadj Table 2. System Timing Terms Term Description

Tcycle System cycle time, defined as the reciprocal of the frequency.

Tflight,min Minimum system flight time.

Tflight,max Maximum system flight time.

Tco,max Maximum driver delay from input clock to output data.

Tco,min Minimum driver delay from input clock to output data.

Tsu Minimum setup time. Defined as the time for which the input data must be valid prior to the input clock.

Thold Minimum hold time. Defined as the time for which the input data must remain valid after the input clock.

Tskew Clock generator skew. Defined as the maximum delay variation between output clock signals from the system clock generator, the maximum delay variation between clock signals due to system board variation and chipset loading variation.

Tjit Clock jitter. Defined as maximum edge to edge variation in a given clock signal.

Tadj Multi-bit timing adjustment factor. This term accounts for the additional delay that occurs in the network when multiple data bits switch in the same cycle. The adjustment factor includes such mechanisms as package and PCB crosstalk, high inductance current return paths, and simultaneous switching noise.

10 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design

Table 3 lists the GTL+ component timings of the processors and GMCH defined at the pins for the Intel® 815E platform. Note: These timings are for reference only. Obtain the processor specifications from respective processor datasheet and chipset values from the appropriate Intel® 815E chipset datasheet.

Table 3. Intel® Celeron® - Ultra Low Power and 82815E GMCH GTL+ Parameters for Example Calculations

IC Parameters Intel® Celeron®-Ultra 82815E GMCH Notes Low Power processor core at 100 MHz System Bus

Clock to Output maximum (TCO_MAX) 3.40 4.10 1,2

Clock to Output minimum (TCO_MIN) 0.20 1.05 1,2

Setup time (TSU_MIN) 1.20 2.65 1,2

Hold time (THOLD) 1.20 0.10 1

NOTES: 1. All time in nanoseconds 2. Numbers in table are for reference only. These timing parameters are subject to change. Check the appropriate component documentation for valid timing parameter values. Table 4 provides an example GTL+ initial maximum flight time and Table 5 is an example minimum flight time calculation for a 100 MHz, uni-processor system using the Intel® Celeron® -Ultra Low Power processor/Intel® 815E chipset system bus. Note that assumed values for clock skew and clock jitter were used. Clock skew and clock jitter values are dependent on the clock components and distribution method chosen for a particular design and must be budgeted into the initial timing equations as appropriate for each design.

Table4andTable5arederivedassuming: • CLKSKEW = 0.20 ns (Note: Assumes clock driver pin-to-pin skew is reduced to 50 ps by tying two host clock outputs together (“ganging”) at clock driver output pins, and the PCB clock routing skew is 150 ps. System timing budget must assume 0.175 ns of clock driver skew and 150 ps PCB clock routing skew if outputs are not tied together and a clock driver that meets the CK815E Clock Synthesizer/ Driver Specification is being used.) • CLKJITTER = 0.250 ns See the appropriate Intel® 815E chipset documentation, and CK815E Clock Synthesizer/Driver Specification for details on clock skew and jitter specifications. Exact details of host clock routing topology are provided with the platform design guideline.

Table 4. Example TFLT_MAX Calculations For 100 MHz Bus

2 Driver Receiver Clk Period TCO_MAX TSU_MIN ClkSKEW ClkJITTER TADJ Recommended TFLT_MAX

Processor GMCH 10.00 3.40 2.65 0.20 0.25 0.50 3.000

GMCH Processor 10.00 4.10 1.20 0.20 0.25 0.50 3.750

NOTES: 1. All times in nanoseconds 2. BCLK period = 10.00ns @ 100MHz

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 11 Processor Host Bus Design

Table 5. Example TFLT_MIN Calculations (Frequency Independent)

Driver Receiver THOLD ClkSKEW TCO_MIN Recommended TFLT_MIN

Processor GMCH 0.10 0.20 0.200 0.100

GMCH Processor 1.20 0.20 1.050 0.350

The flight times in Table 4 include margin to account for the following phenomena that Intel observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect the flight time and signal quality and sometimes are not accounted for during simulation. Accordingly, the maximum flight times depend on the baseboard design, and additional adjustment factors or margins are recommended.

• SSO push-out or pull-in

• Rising or falling edge rate degradation at the receiver caused by inductance in the current return path, requiring extrapolation that causes additional delay

• Crosstalk on the PCB and inside the package which can cause variation in the signals

Additional effects exist that may not necessarily be covered by the multi-bit adjustment factor and need to be budgeted as appropriate to the baseboard design. These effects are included as TADJ in the example calculations in Table 4. Examples include:

• The effective board propagation constant (SEFF), which is a function of:

- Dielectric constant (εr)ofthePCBmaterial

- Type of trace connecting the components (stripline or microstrip)

- Length of the trace and the load of the components on the trace. Note that the board propagation constant multiplied by the trace length is a component of the flight time, but not necessarily equal to the flight time.

12 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design

3.2 General Topology and Layout Guidelines

Figure 2. Topology for BGA2 Designs with Single-Ended Termination (SET)

16 GMCH BGA2-based Processor

= Ω ± Z O 60 15%

Table 6. Trace Guidelines Recommedation1, 2, 3

Description Min. Length (inches) Max. Length (inches)

GMCH to BGA2-based processor 3.50 5.00 trace

NOTES: 1. Reference all GTL+ bus signals to the ground plane for the entire route. 2. Use an intragroup GTL+ spacing : line width : dielectric thickness ratio of at least 2:1:1 for microstrip geometry. If εr = 4.5, this limits coupling to 3.4%. For example, intragroup GTL+ routing could use 10 mils spacing, 5 mils trace width, and a 5 mils prepreg between the signal layer and the plane it references (assuming a 6-layer board design) 3. The recommended trace width is 5 mils, but not greater than 6 mils.

3.3 Simulation Methodology

3.3.1 Pre-Layout Simulation

Analog simulations are recommended for high-speed system bus designs. Start simulations prior to layout. Pre-layout simulations provide a detailed picture of the working “solution space” that meets flight time and signal quality requirements. By basing board layout guidelines on the solution space, the iterations between layout and post-layout simulations can be reduced.

Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis. However, simulation results at the device pins may be used later to correlate simulation performance against actual system measurements.

The BGA2-based processor and 815E I/O buffer models are available from Intel through your Intel representative.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 13 Processor Host Bus Design

3.3.2 Post-Layout Simulation

From the following layout, extract the traces and run simulations to verify that the layout meets timing and noise requirements. A small amount of trace “tuning” may be required, but experience at Intel has shown that a sensitivity analysis significantly reduces the amount of tuning required.

Take into account the expected variation for all interconnect parameters for the post layout simulations. Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis. However, simulation results at the device pins may be used later to correlate simulation performance against actual system measurements.

3.4 Layout Rules for GTL+ Signals

Ground Reference

It is strongly recommended that GTL+ signals be routed on the signal layer next to the ground layer (referenced to ground). It is important to provide an effective signal return path with low inductance. The best signal routing is directly adjacent to a solid GND plane with no splits or cuts. Eliminate parallel traces between layers not separated by a power or ground plane. Routing signals between two signals layers not separated by ground plan need to be implemented as showninFigure3.

Figure 3. Top view of a PCB layout

900 Traces in layer A

Traces in layer B

When a signal has to go through routing layers, the recommendations are:

Note: Following these layout rules is critical for GTL+ signal integrity, particularly for 0.18 micron and smaller process technology. • For signals going from a ground reference to a power reference, add capacitors between ground and power near the vias to provide an AC return path. Use one capacitor for every three signal lines that change reference layers. Capacitor requirements are as follows: C=100nF, ESR=80mΩ,ESL=0.6nH. • For signals going from one ground reference to another, separate ground reference, add vias between the two ground planes to provide a better return path.

14 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design

Reference Plane Splits

Splits in reference planes disrupt signal return paths and increase overshoot/undershoot due to significantly increased inductance. Eliminate routing signal across split/cut plane. When a signal has to route across split plane, add capacitors between the split planes to ground.

Important note: It is strongly recommended NOT to route GTL+ signals across split/cut plane or changing reference plane resulted by traversing layers.

Processor Breakout

It is strongly recommended that GTL+ signals do not traverse multiple signal layers. Intel recommends breaking out all signals from the processor on the same layer. When routing is tight, break out from the processor on the opposite routing layer over a ground reference and cross over to main signal layer near the processor.

Minimizing Crosstalk

The following general rules minimize the impact of crosstalk in a high-speed GTL+ bus design: • Maximize the space between traces. Where possible, maintain a minimum of 10 mils (assuming a 5 mil trace) between trace edges. It may be necessary to use tighter spacing when routing between component pins. When traces must be close and parallel to each other, minimize the distance that they are close together and maximize the distance between the sections when the spacing restrictions are relaxed. • Avoid parallelism between signals on adjacent layers, when there is no AC reference plane between them. As a rule of thumb, route adjacent layers orthogonally. • Since GTL+ is a low-signal-swing technology, it is important to isolate GTL+ signals from other signals by at least 25 mils. This avoids coupling from signals that have larger voltage swings (e.g., 5 V PCI). • GTL+ signals must be well isolated from system memory signals. GTL+ signal trace edges must be at least 30 mils from system memory trace edges within 100 mils of the ball of the Intel® 82815 GMCH. • Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the nominal characteristic impedance within the GTL+ specification. This can be done by minimizing the height of the trace from its reference plane, which minimizes crosstalk. • Route GTL+ address, data, and control signals in separate groups to minimize crosstalk between groups. Keep at least 15 mils between each group of signals. • Minimize the dielectric used in the system. This makes the traces closer to their reference plane and thus reduces the crosstalk magnitude. • Minimize the dielectric process variation used in the PCB fabrication. • Minimize the cross-sectional area of the traces. This can be done by means of narrower traces and/or by using thinner copper, but the trade-off for this smaller cross-sectional area is higher trace resistivity, which can reduce the falling-edge noise margin because of the I*R loss along the trace.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 15 Processor Host Bus Design

3.5 Layout Rules for Non-GTL+ (CMOS) Signals

Table 7. Routing Guidelines for Non-GTL+ Signals

Signal Trace Width Spacing to Other Traces Trace Length

A20M# 5 mils 10 mils 1” to 9”

FERR# 5 mils 10 mils 1” to 9”

FLUSH# 5 mils 10 mils 1” to 9”

IERR# 5 mils 10 mils 1” to 9”

IGNNE# 5 mils 10 mils 1” to 9”

INIT# 5 mils 10 mils 1” to 9”

LINT[0] (INTR) 5 mils 10 mils 1” to 9”

LINT[1] (NMI) 5 mils 10 mils 1” to 9”

PICD[1:0] 5 mils 10 mils 1” to 9”

PREQ# 5 mils 10 mils 1” to 9”

PWRGOOD 5 mils 10 mils 1” to 9”

SLP# 5 mils 10 mils 1” to 9”

SMI# 5 mils 10 mils 1” to 9”

STPCLK 5 mils 10 mils 1” to 9”

NOTE: Route these signals on any layer or combination of layers.

3.5.1 Additional Routing and Placement Considerations

• Distribute VTT with a wide trace. A 0.050 inch minimum trace is recommended to minimize DC losses. Route the VTT trace to all components on the host bus. Be sure to include decoupling capacitors.

• The VTT voltage need to be 1.25 V ± 3% for static conditions, and 1.25 V ± 9% for worst- case transient conditions.

• Place resistor divider pair for VREF generation at the GMCH component. VREF also is delivered to the processor.

3.6 Undershoot/Overshoot Requirements

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot events on buffers when the charge is large enough (i.e. when the overshoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. Violating the overshoot/undershoot guideline also makes satisfying the ringback specification difficult.

16 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design

When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and do not provide overshoot or undershoot protection. Refer to Intel® Celeron® Processor Low Power/Ultra Low Power and Intel® Pentium® III – Low Power datasheet for detailed undershoot/overshoot requirements.

3.7 Processor Reset Requirements

The BGA2-based processor designs must route the GTL+ reset signal from the chipset to the processor as well as to the debug port connector. The A6 (RESET) signal is connected to this pin for the Intel® Pentium® III processor (CPUID=068xh), Intel® Celeron® processor (CPUID=068xh)

Note: The GTL+ reset signal must always terminate to VTT on the motherboard.

Designs that do not support the debug port will not utilize the 240 Ω series resistor or the connection of RESET# to the debug port connector.

The routing rules for the GTL+ reset signal are shown in Figure 4.

Figure 4. RESET# Routing Guidelines

VTT

86 Ω

L1 L2 L0

Processor GMCH

Table 8. RESET# Routing Guidelines (see Figure 4)

Parameter Minimum (in) Maximum (in)

L0 2.0 4.1

L1 0.5 1.5

L2 0.9 1.5

L0+L2 3.5 5.0

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 17 Processor Host Bus Design

3.8 Debug Port Routing Guidelines

The Test Access Port (TAP) interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to voltage levels supported by the TAP interface, Intel recommends that the Intel® Celeron® Processor-LP/ULP and Intel® Pentium® III Processor-LP and the other 1.5V JTAG specification compliant devices be last in the JTAG chain after any devices with 3.3 V or 5 V JTAG interfaces within the system. A translation buffer needs to be used to reduce the TDO output voltage of the last 3.3/5 V device down to the 1.5 V range that the processors can tolerate. Multiple copies of TMS and TRST# must be provided, one for each voltage level.

A Debug Port and connector may be placed at the start and end of the JTAG chain containing the processor, with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port. There are no requirements for placing the Intel® Celeron® Processor-ULP/LP and Intel® Pentium® III Processor-LP in the JTAG chain, except for those that are dictated by voltage requirements of the TAP signals.

The 1.5 V connector is a mirror image of the older 2.5 V connector. Either connector will fit into the same printed circuit board layout. Only the pin numbers change (Figure 5). Also required, along with the new connector, is an In-Target Probe* (ITP) that is capable of communicating with the TAP at the appropriate logic levels.

Figure 5. TAP Connector Comparison

2.5 V connector, AMP 104068-3 vertical plug, top view

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

RESET# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

1.5 V connector, AMP 104078-4 vertical receptacle, top view

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

RESET# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

sys_bus_TAP_conn

Caution: The Intel® Pentium® III processor (CPUID=068xh) and Intel® Celeron® processor (CPUID=068xh) require an in-target probe (ITP) compatible with 1.5 V signal levels on the TAP. Previous ITPs were designed to work with higher voltages and may damage the processor when connected to any of these specified processors.

See the processor datasheet for more information regarding the debug port.

18 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design

3.9 PLL Filter Recommendations

It is highly critical that phase lock loop power delivery to the processor meets Intel requirements. A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated, decoupled power source for the internal PLL.

3.9.1 Topology

The general desired topology for these PLLs is shown in Figure 6. Not shown are the parasitic routing and local decoupling capacitors. Excluded from the external circuitry are parasitic associated with each component.

The following tables contain examples of components that meet Intel recommendations when configured in the topology of Figure6.

Table 9. Component Recommendations – Inductor

Part Number Value Tolerance SRF Rated DCR (Typical) Current

TDK MLF2012A4R7KT 4.7 µH 10% 35 MHz 30 mA 0.56 Ω (1 Ω max.)

Murata LQG21N4R7K00T1 4.7 µH 10% 47 MHz 30 mA 0.7 Ω (±50%)

Murata LQG21C4R7N00 4.7 µH 30% 35 MHz 30 mA 0.3 Ω max.

Table 10. Component Recommendations – Capacitor

Part Number Value Tolerance ESL ESR

Kemet T495D336M016AS 33 µF 20% 2.5 nH 0.225 Ω

AVX TPSD336M020S0200 33 µF 20% 2.5 nH 0.2 Ω

Table 21. Component Recommendation – Resistor

Value Tolerance Power Note

1 Ω 10% 1/16 W Resistor may be implemented with trace resistance, in which case a discrete R is not needed. See Figure.

To satisfy damping requirements, total series resistance in the filter (from VTT to the top plate of the capacitor) must be at least 0.35 Ω. This resistor can be in the form of a discrete component or routing or both. For example, if the chosen inductor has minimum DCR of 0.25 Ω,thena routing resistance of at least 0.10 Ω is required. Be careful not to exceed the maximum resistance rule (2 Ω). For example, if using discrete R1 (1 Ω±1%), the maximum DCR of the L (trace plus inductor) is less than 2.0 – 1.1 = 0.9 Ω, which precludes the use of some inductors and sets a max. trace length.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 19 Processor Host Bus Design

Other routing requirements: • The capacitor (C) is close to the PLL1 and PLL2 pins, < 0.1 Ω per route. These routes do not count towards the minimum damping R requirement. • The PLL2 route is parallel and next to the PLL1 route (i.e., minimize loop area).

• The inductor (L) is close to C. Any routing resistance is inserted between VTT and L.

• Any discrete resistor (R) is inserted between VTT and L.

Figure 6. Example PLL Filter Using a Discrete Resistor

VTT

R L <0.1 Ω route PLL1 Discrete resistor C Processor

PLL2 <0.1 Ω route

PLL_filter_1

Figure 7. Example PLL Filter Using a Buried Resistor

VTT

R L <0.1 Ω route PLL1 Trace resistance C Processor

PLL2 <0.1 Ω route

PLL_filter_2

20 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design

3.9.2 Filter Specification

The function of the filter is to protect the PLL from external noise through low-pass attenuation. The low-pass specification, with input at VCCCORE and output measured across the capacitor, is as follows: • < 0.2 dB gain in pass band • < 0.5 dB attenuation in pass band (see DC drop in next set of requirements) • > 34 dB attenuation from 1 MHz to 66 MHz • > 28 dB attenuation from 66 MHz to core frequency

The filter specification is graphically shown in Figure 8.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 21 Processor Host Bus Design

Figure 8. Filter Specification

0.2dB 0dB -0.5 dB

Forbidden Zone

Forbidden Zone -28dB

-34dB

DC 1Hz fpeak 1MHz 66MHz fcore

passband high frequency band

filter_spec

NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore. 3. fpeak is less than 0.05 MHz.

Other requirements: • Use shielded-type inductor to minimize magnetic pickup. • Filter supports DC current > 30 mA. • DC voltage drop from VCC to PLL1 is < 60 mV, which in practice implies series

R<2Ω. This also means pass-band (from DC to 1 Hz) attenuation < 0.5 dB for VCC =1.1 V, and < 0.35 dB for VCC =1.5V.

22 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design

3.10 Decoupling Guidelines for BGA2-based Processors

The amount of bulk decoupling required on the VCC and VCCT planes to met the voltage tolerance requirements for the Intel® Celeron® Processor – Low Power or Ultra Low Power and Intel® Pentium® III Processor – Low Power are a strong function of the power supply design. Contact your Intel Field Sales Representative for tools to help determine how much bulk decoupling is required.

For 700 MHz processors, the following decoupling is recommended. The processor core power plane (VCC) has fifteen 0.68µF 0603 ceramic capacitors (using X7R dielectric for thermal reasons) placed directly under the package using two vias for power and two vias for ground to reduce the trace inductance. Also to minimize inductance, traces to those vias are 22 mils (in width) from the capacitor pads to match the via-pad size (assuming 22-mil pad size). Twenty- four 2.2µF 0805, X5R mid-frequency decoupling capacitors placed around the die as close to the die as flex solution allows. The system bus buffer power plane (VCCT) has twenty 0.1µFhigh- frequency decoupling capacitors around the die.

For 500 and 400 MHz processors, the processor core power plane (VCC)haseight0.1µFhigh- frequency decoupling capacitors placed underneath the die and twenty 0.1µF mid-frequency decoupling capacitors placed around the die as close to the die as flex solution allows. The system bus buffer power plane (VCCT) has twenty 0.1µF high-frequency decoupling capacitors around the die.

For 300 MHz processors, the processor core power plane (VCC)haseight0.1µF high-frequency decoupling capacitors placed underneath the die and twenty 0.1µF mid-frequency decoupling capacitors placed around the die as close to the die as flex solution allows. The system bus buffer power plane (VCCT) has twenty 0.1µF high-frequency decoupling capacitors around the die.

3.11 Catastrophic Thermal Protection

The Intel® Celeron® Processor – Low Power / Ultra Low Power and Intel® Pentium® III Processor – Low Power does not support catastrophic thermal protection or the THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the system against excessive temperatures.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 23 Clocking

4 Clocking

4.1 General Clocking Considerations

The host bus clock signals are critical signals for the BGA2-based processor and 815E platform. The signal integrity and timing of these signals needs to be carefully evaluated and simulated.

In general, the following layout recommendation needs to be followed for the host bus clocks:

• It is recommended that system bus clocks be routed on the signal layer next to the ground layer (referenced to ground)

• It is strongly recommended that system bus clocks do not traverse multiple signal layers.

• System clock routing over power plane splits need to be eliminated.

• When necessary, grounded guard band traces can be routed next to clock traces to reduce cross talk to other signals.

4.2 Single-Ended Host Bus Clocking Routing

The BGA2-based processor and 815E platforms have support for using single-ended host bus clock driver. When using this clocking method, the BCLK signal is used as the single-ended clock input to the BGA2-based processor. The CLKREF signal is used as a reference voltage and must be connected to the appropriate filter circuit described in section 4.2.1

Figure 9 shows the topology recommended for the BGA2-based processor and 815E clock traces. Please note that section 1, section 2 and section 3 refer to trace length between the illustrated components. Table 12 contains the recommended length and component values for this topology.

24 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Clocking

Figure 9 Single-Ended Clocking Topology

Table 12 Recommended Length for Single-Ended Clocking Topology

Destination Section 0 Length Section 1 Length Section 2 Length Section 3 Length

Processor BCLK <0.1” <0.5” A + 5.2” N.A.

GMCH HCLK N.A. <0.5” N.A. A + 8”

NOTES: 1. Length “A” has been simulated up to 6 inches. The length must be matched between SDRAM MCLK lines by ± 100 mils. 2. All length specific in inches

Clock Decoupling

Several general layout guidelines need to be followed when laying out the power planes for the CK815 clock generator, as follows: • Isolate power planes to each of the clock groups. • Place local decoupling as close as possible to power pins, and connect with short, wide traces and copper. • Connect pins to appropriate power plane with power vias (larger than signal vias). • Bulk decoupling needs to be connected to a plane with 2 or more power vias. • Minimize clock signal routing over plane splits. • Do not route any signals underneath the clock generator on the component side of the board. • An example signal via is a 14 mils finished hole with a 24 mils to 26 mils pad. An example power via is an 18 mils finished hole with a 33 mils to 38 mils pad. For large decoupling or power planes with large current transients, a larger power via is recommended

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 25 Clocking

4.2.1 CLKREF Filter Implementation

When using single-ended clocking mode, the CLKREF signal on the BGA2-based processor serves as a reference voltage to the clock input. To provide a steady reference voltage, a filter circuit must be implemented and attached to this pin. Figure 10 shows the recommended CLKREF filter implementation. The CLKREF filter need to be placed as close as possible (less than 1.0 inch) to the processor CLKREF pin.

Figure 10. Examples for CLKREF Divider Circuit

Table 13. CLKREF Component Values

R1 (Ω) ± 1% R2 (Ω) ± 1% CLKREF Voltage (V)

1k 1k 1.25

26 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Clocking

4.2.2 Single-Ended Clocking BSEL[1:0] Implementation

The BGA2-based processor and 815E platform is using single-ended clocking that only support 100 MHz system bus. In order to implement the 100 MHz system bus, BSEL0 needs to be pulled up to 1.5 V through a 1.5 KΩ 5% resistor and BSEL1 needs to be pulled down to GND. This strapping configures the clock generator to output 100 MHz clock to support a 100 MHz capable processor. Figure 11 shows a diagram of this implementation.

Figure 11. BSEL[1:0] Circuit Implementation for LP CopperMine processor Designs

8.2k

4.2.3 Clock Driver Decoupling and Power Delivery

The decoupling and power delivery requirements of the system clock driver are dependent on the clock driver and chipset used in the system implementation. Because of this, no specific information can be provided in this document. However, since proper decoupling and noise-free power delivery are critical to the clock driver operation, Intel encourages system implementers to carefully follow the chipset and clock driver vendor recommendations in these areas. An incorrect implementation of these circuits can easily cripple clock driver recommendations in these areas and its ability to produce reliable clock signals and lead to system instability. Please refer to the appropriate clock driver and chipset vendor information for more details.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 27 Processor Host Bus Design Checklist

5 Processor Host Bus Design Checklist

5.1 Introduction

This checklist highlights design considerations that need to be reviewed prior to manufacturing a motherboard. This design checklist only provides the processor host bus signals design recommendation. It is not a complete list and does not guarantee that a design functions properly. Besides the items in the following text, refer to most recent version of the Intel® 815E Chipset Platform For Use with Universal Socket 370 Design Guide for more detailed instruction. This checklist is to be revised, as new information is available.

5.2 GTL+ Checklist

Table 14. GTL+ signals checklist

Checklist items Recommendations

A[35:3]# Connect to A[31:3]# to 815 GMCH. Leave A[35:32]# as N/C.

BNR#, BPRI#, Connect to 815 GMCH. D[63:0]#, DBSY#, DEFER#, DRDY#, HIT#, HITM#, LOCK#, REQ#[4:0], RS[2:0], TRDY#

ADS# Connect to 815 GMCH. For debug purpose, pull-up to VCCT through 56 Ω resistor, and placed within 150 mils of 815 GMCH

AERR#, Leave as N/C. AP[1:0]#, BERR#, BINIT#, BP[3:2]#, BPM[1:0]#, DEP[7:0]#, RP#, RSP#

BREQ0# 10 Ω pull down to ground.

RESET# Connect to 815 GMCH. Pull up to VCCT with an 86 Ω 1% resistor. Connect to ITP with 240 Ω series resistor near to ITP if ITP is used.

28 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Processor Host Bus Design Checklist

5.2.1 CMOS (Non-GTL+) Checklist

Table 15. CMOS (Non-GTL+) signals checklist

Checklist items Recommendations

A20M#, IGNNE#, Connect to ICH2. INTR, INIT#, NMI, SMI#, STPCLK#

FERR#, SLP#, Connect to ICH2. Pull up to VCCT with a 1.5 KΩ resistor.

FLUSH#, IERR#, Pull up to VCCT with 1.5 K Ω resistor. PREQ#

PWRGOOD Pull up to 2.5V with 1.5 K Ω resistor.

PICD[1:0] Connect to ICH2. Pull up to VCCT with a 150 Ω resistor.

5.3 TAP Checklist

Table 16. TAP signals checklist

Checklist items Recommendations

TCK, TMS Connect to ITP with 47 Ω series resistor. Pull up to VCCT with 1 KΩ resistor

TDI, TDO Connect to ITP. Pull up to VCCT with a 150 Ω resistor.

TRST# Connect to ITP. Pull down with 1 KΩ resistor to ground.

PRDY# Connect to ITP with 240 Ω series resistor. Pull up to VCCT with 56.2 Ω resistor.

PRDY1#, PRDY2#, Pull up to 1.5 V VCCT through 1 KΩ resistor. PRDY3#

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 29 Processor Host Bus Design Checklist

5.3.1 Miscellaneous Checklist

Table 17. Miscellaneous signal checklist

BCLK Connect to CK815 clock generator with 33 Ω series resistor (may vary depends on simulation). Tie both host clock outputs (to the processor and to the chipset) at the clock generator before routing out to processor and GMCH.

BSEL0 Pull up to VCCT with 1.5 KΩ 5% resistor (100 MHz PSB only).

BSEL1 Tie to ground (100 MHz PSB only).

CLKREF Connect to voltage divider circuitry on 2.5 V to create 1.25 V reference. Decouple using 0.1 µF capacitor

EDGECTRLP Pull down with 110 Ω resistor 1% to ground.

PICCLK Connect to CK815E clock generator with 33 Ω series resistor (may vary depends on simulation).

PLL1, PLL2 Connect to PLL low pass filter circuit.

RTTIMPEDP Pull down with 56.2 Ω resistor 1% to ground.

THERMDA, If thermal sensor is used, connect to thermal sensor. Else, leave as NC. THERMDC

CMOSREF Connect to voltage divider circuitry on 2.5 V to create 1V reference. Decouple using two 0.1 µF capacitors.

VID[4:0] Connect 100 Ω resistor to GND.

VREF[7:0] Connect to voltage divider circuit to VCCT with 2/3 ratio (75 Ω and 150 Ω,1% resistors). Decouple with four 0.1 µF capacitors near processor. Also connect to 815 GMCH GTLREF[A,B] with two 0.1 µF decoupling capacitors at GMCH.

VCC_CORE Processor core supply. See notes 1 and 2

VCCT 1.5 V supply.

VSS Ground.

A15, A16, A17, C14, No connect. D8, D14, D16, E15, G2, G5, G18, H3, H5,J5,M4,M5,P3, P4, AA5, AA19, AC3, AC17, AC20, AD15, R2

NOTES: 1. Refer to Intel® Pentium® III Processor – Low Power 700Mhz, 500Mhz and 400Mhz Processors in BGA2 Package for power supply decoupling requirement. 2. Refer to Intel® Celeron® Processor – Low Power/Ultra Low Power 300MHz (ULP) and 400AMHz (LP) Processor in a BGA2 Package for power supply decoupling requirement.

30 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide Reference Schematic

6 Reference Schematic

This section provide the reference schematic for Intel ® Celeron® Processor – Low Power or Ultra Low Power or Intel ® Pentium® III - Low Power in a BGA2 package and the Intel ® 815E chipset platform.

Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide 31 A

INTEL® PENTIUM® III LOW POWER & INTEL® CELERON (TM) ULTRA-LOW POWER PROCESSOR (BGA2) / INTEL® 815E CHIPSET UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS

REVISION 0.5

Title Page Cover Sheet 1 ** Please note these schematics are subject to change. Block Diagram 2 Low Power Intel® Celeron®/Pemtium® III BGA2 3, 4 THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES CPU Decoupling 5 WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS Clock Synthesizer 6 FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING 82815E 7, 8, 9 OUT OF PROPOSAL, SPECIFICATION OR SAMPLES. Display Cache 10 System Memory 11, 12 Information in this document is provided in connection with Intel products. No license, ICH2 13, 14 express or implied, by estoppel or otherwise, to any intellectual property rights is A FWH & UDAM 100 IDE1-2 15 granted by this document. Except as provided in Intel's Terms and Conditions of Sale A for such products, Intel assumes no liability whatsoever, and Intel disclaims any Super I/O 16 express or implied warranty, relating to sale and/or use of Intel products including PCI Connectors 17, 18 liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products USB Connectors 19 are not intended for use in medical, life saving or life sustaining applications. AC97 CODEC 20 Audio I/O 21 Intel may make changes to specifications and product descriptions at any time, Serial and Parallel Ports 22 without notice. Kybrd / Mse / F. Disk / Gme Connectors 23 Digital Video Out 24 The Intel® Celeron(tm) processor and Intel® 815E chipset may contain design defects Video Connectors 25 or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. LAN on Motherboard 26 ATX Power & H/W Monitor 27, 28 Voltage Regulators 29, 30 Copyright (c) Intel Corporation 2001. System Configuration 31 Pullup Resistors and Unused Gates 32, 33 * Third-party brands and names are the property of their respective owners. Power Plane Decoupling Capacitors 34

COVER SHEET Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 1 of 34 A A

Block Diagram

VRM Low Power Intel® Celeron®/Pemtium® III BGA2 Processor Clock 8.5 AD CT DATA DR RL

GTL BUS AD CTR DATA DR L

Display Cache Memory 2 DIMM 815E Modules GMCH Digital Video Out Device

IDE Primary UltraDMA/100 PCI CONN PCI CONN PCI CONN 3 PCI CONN IDE Secondary ICH2 PCI BUS

A A 1 2 4 USB Port 1-2 USB LPC Bu 82562 Jordan PHY PHY s

SIO Audio Codec AC'97 Link FirmWare Hub

Game Port Keyboard Floppy Serial 1 Serial 2 Parallel Mouse

BLOCK DIAGRAM Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 2 of 34 A 5 4 3 2 1

VCC_CORE VCCT1_5

BGA2_1A BGA2_1B

A2 N2 H8 G6 A7 VSS VSS N3 H10 VCC VCCT G7 A8 VSS VSS N4 H12 VCC VCCT G8 A12 VSS VSS N8 H14 VCC VCCT G9 A VSS VSS VCC VCCT A A21 N10 H16 G10 B1 VSS VSS N12 J7 VCC VCCT G11 B5 VSS VSS N14 J9 VCC VCCT G12 B6 VSS VSS N16 J11 VCC VCCT G13 B7 VSS VSS N18 J13 VCC VCCT G14 VSS VSS VCC VCCT B8 N19 J15 G15 B10 VSS VSS N20 K8 VCC VCCT G16 B15 VSS VSS P5 K10 VCC VCCT G17 B18 VSS VSS P7 K12 VCC VCCT H6 C9 VSS VSS P9 K14 VCC VCCT H17 VSS VSS VCC VCCT C11 P11 K16 J6 C15 VSS VSS P13 L7 VCC VCCT J17 C16 VSS VSS P15 L9 VCC VCCT K6 C19 VSS VSS P19 L11 VCC VCCT K17 D2 VSS VSS R3 L13 VCC VCCT L6 VSS VSS VCC VCCT D6 R4 L15 L17 D7 VSS VSS R5 M8 VCC VCCT M6 D9 VSS Low PowerVSS R8 M10 VCC VCCT M17 E3 VSS BGA2-495 VSS R10 M12 VCC VCCT N6 E7 VSS VSS R12 M14 VCC VCCT N17 VSS VSS VCC VCCT E8 R14 M16 P6 E9 VSS VSS R16 N7 VCC VCCT P17 E10 VSS VSS R20 N9 VCC VCCT R6 VSS VSS VCC VCCT B E11 T3 N11 R17 B E13 VSS VSS T5 N13 VCC VCCT T6 VSS VSS VCC VCCT E19 T7 N15 T17 F3 VSS VSS T9 P1 VCC VCCT U6 F6 VSS VSS T11 P8 VCC VCCT U17 F7 VSS VSS T13 P10 VCC VCCT V6 F8 VSS VSS T15 P12 VCC VCCT V7 VSS VSS VCC VCCT F9 T18 P14 V8 F10 VSS VSS T19 P16 VCC VCCT V9 F11 VSS VSS U8 R7 VCC VCCT V10 F12 VSS VSS U10 R9 VCC VCCT V11 F13 VSS VSS U12 R11 VCC VCCT V12 VSS VSS VCC VCCT F14 U14 R13 V13 F15 VSS VSS U16 R15 VCC VCCT V14 F16 VSS VSS U20 T8 VCC VCCT V15 F20 VSS VSS V3 T10 VCC VCCT V16 G3 VSS VSS V19 T12 VCC VCCT V17 VSS VSS VCC VCCT G19 W4 T14 W6 H2 VSS VSS W18 T16 VCC VCCT W7 H7 VSS VSS Y3 U7 VCC VCCT W8 H9 VSS VSS Y9 U9 VCC VCCT W9 H11 VSS VSS Y10 U11 VCC VCCT W10 VSS VSS VCC VCCT H13 Y11 U13 W11 H15 VSS VSS Y12 U15 VCC VCCT W12 VSS VSS VCC VCCT C H20 Y13 A15 W13 C J4 VSS VSS Y14 A16 NC VCCT W14 J8 VSS VSS Y15 A17 NC VCCT W15 VSS VSS NC VCCT J10 Y16 C14 W16 J12 VSS VSS Y19 D8 NC VCCT W17 J14 VSS VSS AA4 D14 NC VCCT Y6 J16 VSS VSS AA13 D16 NC VCCT Y7 J19 VSS VSS AA20 E15 NC VCCT Y8 VSS VSS NC VCCT K2 AB3 G2 AA6 K7 VSS VSS AB5 G5 NC VCCT AA7 K9 VSS VSS AB9 G18 NC VCCT AA8 K11 VSS VSS AB11 H3 NC VCCT AB6 K13 VSS VSS AB13 H5 NC VCCT AB7 VSS VSS NC VCCT K15 AB14 J5 AB8 K20 VSS VSS AB17 M4 NC VCCT AC6 L5 VSS VSS AC1 M5 NC VCCT AC7 L8 VSS VSS AC2 P3 NC VCCT AC8 L10 VSS VSS AC5 P4 NC VCCT AD6 VSS VSS NC VCCT L12 AC10 AA5 AD7 L14 VSS VSS AC14 AA19 NC VCCT AD8 L16 VSS VSS AC16 AC3 NC VCCT L19 VSS VSS AC18 AC17 NC M7 VSS VSS AC21 AC20 NC VSS VSS NC M9 AD1 AD15 D M11 VSS VSS AD5 R2 NC D M13 VSS VSS AD16 NC M15 VSS VSS AD21 M20 VSS VSS Intel® Celeron®/Pemtium® III Low Power PBGA VSS PROCESSOR PART 1 Title Intel® Celeron®/Pemtium® III Low Power PBGA Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 3of 34 5 4 3 2 1 5 4 3 2 1

VCCT1_5 VCC2_5 VCC2_5 VCCT1_5

R1 R2 R3 R4 1K 1% 1K 1% 1.5K 1% L1 VREF_GTL VREF_CLK VREF_CMOS 1 PLL1 7 GTLREF BC1 BC2 BC3 BC4 4.7uH 2K 1% R6 C1 R7 C2 C3 E 0.1uF 0.1uF 0.1uF 0.1uF C4 E R5 1K 1% 0.1uF 1K 1% 0.1uF 0.1uF 33uF 16V PLL2

Place very close to Processor 7 HA#[31:3] HD#[63:0] 7 BGA2_1C BGA2_2D

HA#3 L3 D10 HD#0 VREF_GTL E5 T4 CPU_BNR# 7 HA#4 K3 A#3 D#0 D11 HD#1 E16 VREF BNR# U4 CPU_BPRI# 7 HA#5 J2 A#4 D#1 C7 HD#2 E17 VREF BPRI# U2 CPU_TRDY# 7 HA#6 L4 A#5 D#2 C8 HD#3 F5 VREF TRDY# U3 A#6 D#3 VREF DEFER# CPU_DEFER# 7 HA#7 L1 B9 HD#4 F17 R1 VCCT1_5 CPU_LOCK# 7 HA#8 K5 A#7 D#4 A9 HD#5 U5 VREF LOCK# T1 CPU_DRDY# 7 HA#9 K1 A#8 D#5 C10 HD#6 Y17 VREF DRDY# V1 CPU_HIT# 7 HA#10 J1 A#9 D#6 B11 HD#7 Y18 VREF HIT# Y4 R8 CPU_HITM# 7 HA#11 J3 A#10 D#7 C12 HD#8 VREF HITM# AA3 A#11 D#8 DBSY# CPU_DBSY# 7 HA#12 K4 B13 HD#9 VCCT1_5 VREF_CMOSAA9 AB2 1.5K A#12 D#9 CMOSREF ADS# CPU_ADS# 7 D HA#13 G1 A14 HD#10 AD18 AC9 D HA#14 H1 A#13 D#10 B12 HD#11 CMOSREF FLUSH# HA#15 E4 A#14 D#11 E12 HD#12 VCCT1_5 R9 VREF_CLK P2 AA21 CPU_HCLK 6 HA#16 F1 A#15 D#12 B16 HD#13 1.5K CLKREF BP#2 Y21 A#16 D#13 BP#3 HA#17 F4 A13 HD#14 AD17 W21 VCCT1_5 A#17 D#14 TESTHI BPM#0 HA#18 F2 D13 HD#15 Y5 W19 R10 C5 Do not stuff HA#19 E1 A#18 D#15 D15 HD#16 N5 TESTLO1 BPM#1 C6 R11 A#19 D#16 TESTLO2 BREQ#0 HA#20 C4 D12 HD#17 Only 100Mhz PSB AD20 10 18pF A#20 D#17 TESTP HA#21 D3 B14 HD#18 supported by BGA2 R14 R15 H4 M3 86 HA#22 A#21 D#18 HD#19 R12 R13 1K 1K TESTP BCLK D1 E14 processors. AA17 HA#23 E2 A#22 D#19 C13 HD#20 150 150 G4 TESTP A6 CPU_RST# 7 HA#24 D5 A#23 D#20 A19 HD#21 BSEL[1:0]='01' TESTP RESET# ITP_RESET# HA#25 D4 A#24 D#21 B17 HD#22 VCCT1_5 AA18 AA1 HA#26 C3 A#25 D#22 A18 HD#23 6 CPU_APICCLK AB21 PICCLK AERR# E6 VCC2_5 A#26 D#23 13 CPU_APIC0 PICD0 BERR# HA#27 C1 C17 HD#24 Y20 V21 HA#28 B3 A#27 D#24 D17 HD#25 13 CPU_APIC1 PLL1 L2 PICD1 BINIT# HA#29 A3 A#28 D#25 C18 HD#26 R16 PLL2 M2 PLL1 AA16 R17 CPU_EDGECTRL HA#30 B2 A#29 D#26 B19 HD#27 1.5K PLL2 EDGECTRLP AD19 R18 HA#31 C2 A#30 D#27 D18 HD#28 AA12 RTTIMPEDP AB19 1.5K, 1% 110 1% A#31 D#28 6,8 CPU_BSEL0 BSEL0 RSVD C A4 B20 HD#29 AB15 V5 R19 C CPU_PWGD 13 A5 A#32 D#29 A20 HD#30 6,8 CPU_BSEL1 BSEL1 PWRGOOD 56.2 1% B4 A#33 D#30 B21 HD#31 VCCT1_5 AD10 AA15 VTIN2 16,28 C5 A#34 D#31 D19 HD#32 13 CPU_A20M# AC13 A20M# THERMDA AB16 THRMDN 16,28 A#35 D#32 C21 HD#33 13 CPU_IGNNE# AA10 IGNNE# THERMDC 7 HREQ#[4:0] D#33 13,15 CPU_INIT# INIT# HREQ#0 T2 E18 HD#34 R20 AB18 W20 ITP_PRDY# HREQ#1 V4 REQ#0 D#34 C20 HD#35 13 CPU_INTR AC19 INTR/LINT0 PRDY# AB20ITP_PREQ# VCCT1_5 HREQ#2 V2 REQ#1 D#35 F19 HD#36 1.5K 13 CPU_NMI AC12 NMI/LINT1 PREQ# AA11ITP_TCK HREQ#3 W3 REQ#2 D#36 D20 HD#37 13 CPU_FERR# AD9 FERR# TCK AD13ITP_TDI HREQ#4 W5 REQ#3 D#37 D21 HD#38 AB12 IERR# TDI AC15ITP_TDO REQ#4 D#38 13 CPU_SLP# SLP# TDO H18 HD#39 AB10 AD14ITP_TMS 7 RS#[2:0] RS#0 U1 D#39 F18 HD#40 13 CPU_SMI# AC11 SMI# TMS AA14ITP_TRST# R21 R22 R23 R24 R25 R26 R27 R28 R29 RS#1 AA2 RS#0 D#40 J18 HD#41 13 CPU_STPCLK# STPCLK# TRST# RS#2 W1 RS#1 D#41 F21 HD#42 1K 1K 10K 1K 1K 150 150 1.5K 56.2 RS#2 D#42 E20 HD#43 Intel® Celeron®/Pemtium® III Low Power PBGA D#43 V20 H19 HD#44 T21 DEP#0 D#44 E21 HD#45 VCCT1_5 VCCT1_5 U21 DEP#1 D#45 J20 HD#46 R21 DEP#2 D#46 H21 HD#47 V18 DEP#3 D#47 L18 HD#48 R30 R31 J1 B DEP#4 D#48 B P21 G20 HD#49 ITP_RESET# R32 240 2 1 P20 DEP#5 D#49 P18 HD#50 1.5K 1% 1.5K 4 RESET# GND 3 U19 DEP#6 D#50 G21 HD#51 27 DBRESET# ITP_TCK R33 47 6 DBRESET# GND 5 DEP#7 D#51 K18 HD#52 ITP_TMS 8 TCK GND 7 ITP_TDI W2 D#52 K21 HD#53 R34 47 10 TMS TDI 9 ITP_TDO RP# D#53 POWERON TDO Y1 M18 HD#54 12 11 ITP_TRST# RSP# D#54 L21 HD#55 14 DBINST# TRST# 13 AB1 D#55 R19 HD#56 16 GND BSEN# 15 ITP_PREQ# Y2 AP#0 D#56 K19 HD#57 18 GND PREQ0# 17 ITP_PRDY# AP#1 D#57 T20 HD#58 20 GND PRDY0# 19 240 R35 D#58 GND PREQ1# AD2 J21 HD#59 22 21 AD3 VID0 D#59 L20 HD#60 24 GND PRDY1# 23 AD4 VID1 D#60 M19 HD#61 26 GND PREQ2# 25 R36 AC4 VID2 D#61 U18 HD#62 28 GND PRDY2# 27 AB4 VID3 D#62 R18 HD#63 30 GND PREQ3# 29 1K VID4 D#63 6 ITP_CLK ITP_CLK PRDY3#

Intel® Celeron®/Pemtium® III Low Power PBGA ITP_RECEPTACLE A R37 R38 R39 R40 R41 A 1K 1K 1K 1K 1K PROCESSOR PART 2 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 4of 34 5 4 3 2 1 5 4 3 2 1

VCC_CORE

D C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 VCC_CORE D

10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V

C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V

C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47

10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V

C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V

C C C64 C65 C66 C67 C68 C69 C70 C71 C72 C73

10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V C74 C75 C76 C77 C78 C79

2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V 2.2uF 6.3V

C80 C81 C82 C83 C84 C85 C86 C87 C88 C89

10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V 10uF 6.3V

C90 C91 C92 C93 C94

VCCT1_5 0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V

C95 C96 C97 C98 C99

0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 B B 150uF 150uF 150uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF C113 C114 C115 C116 C117

0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V 0.68uF 6.3V

C118 C119 C120 C121 C122 C123 C124 C125 C126 C127

1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF

C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 A A 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 5of 34 5 4 3 2 1 A

Clock Synthesizer VCC3_3

L2A USBV3 1 2 C150A C151A 1 +

VCC3_3 22uF 0.1uF 2 VCC3_3 L4A L3A Notes: 1 2 1 2 PCIV3 MEMV3 - Place all decoupling caps as close to VCC/GND pins as possible C157A C158A C159A C160A C161A C162A C152A C163A C164A C153A C154A C155A C156A C165A 1 1 - PCI_0/ICH pin has to go to the ICH. + + (This clock cannot be turned off through SMBus) 22UF 0.1uF .001uF 0.1uF .001uF 0.1uF 0.001uF 0.001uF 0.1uF 0.001uF 0.1uF 0.001uF 0.1uF 22uF 2 2 - CPU_ITP pin must go to the ITP. It is the only CPU CLK that can be shut off through the SMBUS interface.

R42A 8.2K U1 2 10 11 21 27 33 38 44 C166A

Y1A 12PF VDD3_3 VDD3_3 VDD3_3 VDD3_3 VDD3_3 VDD3_3 VDD3_3 VDD3_3 2 R43A XTAL_IN 3 55 APIC_0 AL XTAL_IN APIC_0 R44A CPU_APICCLK 4 XT APIC 54 APIC_1 33 APIC_1 ICH_APICCLK 13 33 4,8CPU_BSEL1 C167A 1 14.318MHZ REF R45A 4 52 XTAL_OUT XTAL_OUT CPU_0 R46A CPU_HCLK 4 50 33 R47A 12PF CPU CPU_1 R48A GMCH_HCLK 7 REFCLK 1 49 33 14 ICH_CLK14 REF0 CPU_2/ITP ITP_CLK 4 10 33 R49A R50A 3V66_0 7 46 DRAM_0 MEMCLK0 MEMCLK[7:0] 11,12 14 ICH_3V66 R51A 3V66_0 SDRAM_0 22 8 3V66 45 R52A 22 3V66_1 3V66_1 SDRAM_1 DRAM_1 MEMCLK1 9 GMCH_3V66 R53A 9 43 DRAM_2 22 MEMCLK2 22 3V66_2 SDRAM_2 A R54A A 42 DRAM_3 22 CK815 SDRAM_3 MEMCLK3 R55A R56A PCI_0 12 40 DRAM_4 22 MEMCLK4 13 PCLK_0/ICH R57A PCI_F SDRAM_4 R58A 33 13 Memory 39 22 PCI_1 PCI_0 SDRAM_5 DRAM_5 MEMCLK5 PCLK_117 R59A 22 R60A 33 PCI_2 15 37 DRAM_6 MEMCLK6 PCLK_217 PCI_1 SDRAM_6 R61A 33 R62A PCI_3 PCI_3 16 PCI 36 DRAM_7 22 MEMCLK7 PCLK_318 R63A PCI_2 SDRAM_7 33 PCI_4 18 22 PCLK_416 R64A PCI_3 R65A VCC3_3 33 PCI_5 19 34 DCLK 18 PCLK_5 R66A PCI_4 DCLK DCLK_WR 8 33 PCI_6 20 22 PCLK_615 PCI_5 R67A 33 32 VCC_CLK_2_5 29 14,16 SIO_CLK24 PWRDWN# 10 SLP_S3# 14,16,30

2 R68A USB_0 25 31 14,16 USBCLK USB_0 SCLK CK_SMBCLK 25 L5A R69A 33 26 USB 30 2 9 DOTCLK USB_1 USB_1 SDATA CK_SMBDATA 25 L6A 22 29 SEL1_PU SEL1 BC5 BC6 28 X10pF X10pF SEL0 CPU_BSEL0 4,8 1 1 L_CKVDDA 22 VDD_A 51 VDD2_5[0] C168A C169A 53 VDD2_5[1] L_VCC2_5 23 0.1UF .001UF VSS_A C170A C171A C172A 1

56 + VSS2_5[1] 48 VSS2_5[0] .001UF 0.1UF 4.7UF 2 VSS3_3[0] VSS3_3[1] VSS3_3[2] VSS3_3[3] VSS3_3[4] VSS3_3[5] VSS3_3[6] VSS3_3[7]

5 6 14 17 24 35 41 47 ICS9250-27

CLOCK SYNTHESIZER Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 6 of 34 A A VCC1_8 815E GMCH, PART 1: L7A 68NH-0.3A VCCT1_5 + Place as close as 1 possible to HOST INTERFACE C173A Use Surface Mount Caps C174A GMCH VCC1_8 C175A

V1P8 2 placed as close as possible to 33uF

0.1uF power pins with short, R70 0.01uF 1 2 GMCHGTLREF 4 GTLREF wide direct connections 0 C176A C177A U2A W6 Y9 Y18 AA6 AA8 AA11 AA13 AA15 AA17 AA19 AB16 AB20 AC22 AD19 C25 E24 F23 G22 J7 K6 M6 P6 T6 V7 G26 Y7 AA21 E23 AF26 AF25 AA1 HD#[63:0] 4 HD0# HD#0 0.1uF 2 AB2 HD#1 0.1uF R71 HD1# AF2 HD#2 56 HD2# VCC1_8[3] VCC1_8[4] VCC1_8[5] VCC1_8[6] VCC1_8[7] VCC1_8[8] VCC1_8[9] VCC1_8[0] VCC1_8[1] VCC1_8[2] VCC1_8[10] VCC1_8[11] VCC1_8[12] VCC1_8[13] VCC1_8[14] VCC1_8[15] VCC1_8[16] VCC1_8[17] VCC1_8[19] VCC1_8[20] VCC1_8[21] VCC1_8[22] VCC1_8[23] VCC1_8[24] VCC1_8[25] AD4 HD3# HD#3

1 U6 GTLREFA AB1 HD4# HD#4

AA10 Vccda_VCC1_8[26] Vccba_VCC1_8[27] GTLREFB Vccdpll_VCC1_8[18] AB3 HD#5

Vccdaca1_VCC1_8[28] Vccdaca2_VCC1_8[29] HD5# AA3 HD#6 AA7 HD6# 6 GMCH_HCLK HTCLK AC4 HD#7 H3 HD7# 15,16,24,32 PCIRST# RESET# AC1 HD#8 AA5 HD8# 4 CPU_RST# CPURST# AF3 HD#9 L4 HD9# 4 CPU_LOCK# HLOCK# AD1 HD#10 M3 HD10# 4 CPU_DEFER# DEFER# AE3 HD#11 Do not stuff G1 HD11# 1 C178 4 CPU_ADS# ADS# AD2 HD#12 N4 HD12# 18pF 4 CPU_BNR# BNR# AD3 Place cap within HD13# HD#13

2 M5 0.5" of clock ball 4 CPU_BPRI# BPRI# AF1 HD#14 J3 HD14# 4 CPU_DBSY# DBSY# AA4 HD#15 J1 HD15# 4 CPU_DRDY# DRDY# AD6 HD#16 K1 HD16# 4 CPU_HIT# HIT# AC3 HD#17 L3 HD17# 4 CPU_HITM# HITM# AE1 HD#18 K3 HD18# 4 CPU_TRDY# HTRDY# AB6 HD19# HD#19 AF4 HD#20 4 HA#[31:3] HA#3 R4 HD20# HA3# AE5 HD#21 HA#4 P1 HD21# HA4# 815E GMCH AC8 HD#22 HA#5 T2 HD22# HA5# AB5 HD#23 HA#6 R3 HD23# HA6# AF5 HD#24 HA#7 N5 544 mBGA HD24# HA7# AC6 HD#25 HA#8 P5 HD25# HA8# AF6 HD#26 HA#9 R1 PART1 HD26# HA9# AD11 HD#27 U1 HD27# HA#10 HA10# AF8 HD#28 P2 HD28# HA#11 HA11# HOST INTERFACE AD8 HD#29 HA#12 T1 HD29# HA12# AD5 HD30# HD#30 A HA#13 T3 A HA13# AB7 HD#31 HA#14 P3 HD31# HA14# AF7 HD#32 HA#15 T5 HD32# HA15# AD7 HD#33 HA#16 R5 HD33# HA16# AB8 HD#34 HA#17 V5 HD34# HA17# AE7 HD#35 HA#18 Y2 HD35# HA18# AE9 HD#36 HA#19 V3 HD36# HA19# AB9 HD#37 HA#20 W1 HD37# HA20# AF9 HD#38 HA#21 U4 HD38# HA21# AD10 HD#39 HA#22 V2 HD39# HA22# AF12 HD#40 HA#23 W3 HD40# HA23# AB11 HD#41 HA#24 W4 HD41# HA24# AB10 HD#42 HA#25 U5 HD42# HA25# AD9 HD#43 HA#26 Y5 HD43# HA26# AC10 HD#44 HA#27 Y3 HD44# HA27# AF10 HD#45 HA#28 U3 HD45# HA28# AD14 HD#46 HA#29 Y1 HD46# HA29# AD12 HD#47 HA#30 W5 HD47# HA30# AB12 HD#48 HA#31 V1 HD48# HA31# AE11 HD49# HD#49 AE15 HD#50 4 HREQ#[4:0] HREQ#0 M1 HD50# HREQ0# AF11 HD#51 HREQ#1 N1 HD51# HREQ1# AF13 HD#52 HREQ#2 M2 HD52# HREQ2# AB14 HD#53 HREQ#3 L5 HD53# HREQ3# AF14 HD#54 HREQ#4 N3 HD54# HREQ4# AB13 HD55# HD#55 AB15 HD#56 4 RS#[2:0] RS#0 K2 HD56# RS0# AE13 HD#57 RS#1 L1 HD57# RS1# AC14 HD#58 RS#2 H1 HD58# RS2# AD13 HD59# HD#59 AD15 HD60# HD#60 AF16 HD61# HD#61 AF15 HD#62 HD62# AC12 HD#63 VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35]_Vssdpll VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17]_Vssba VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] HD63# B26 C3 C6 C9 C12 C15 C18 C21 C24 D1 E5 E7 E10 E12 E15 E17 E20 E22 F1 F3 F11 F13 F16 F25 G9 G17 G21 G23 H6 H22 J2 J5 J23 J25 K4 K7

THIS DRAWING CONTAINS INFORMATION THAT HAS NOT BEEN VERIFIED FOR 815E GMCH PART 1 Title MANUFACTURING AS AN END USER Low Power Intel® Celeron®/Pemtium® III with 815E PRODUCT. INTEL IS NOT Size Document Number Rev RESPONSIBLE FOR THE MISUSE 0.5 OF THIS INFORMATION. Date: Wednesday, March 27, 2002 Sheet 7 of 34 A A

815E GMCH, PART 2:

VCC3_3 SYSTEM MEMORY VCC3_3SBY

U2B B2 B5 B8 B11 B14 B19 B22 B25 E2 F10 F14 F17 G6 G8 G19 H2 H5 H7 K20 Y24 L21 M23 U25 N25 R21 U20 U23 W20 SM_MD[63:0] D23 SM_MD[63:0] 11,12 SMD0 SM_MD0 C23 GMCH RESET STRAPS 11,12 SM_MAA[12:0] SMD1 SM_MD1 SM_MAA0 D13 SMAA0 VDDQ[0] VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] D22 SMD2 SM_MD2 Vsus3_3[1] Vsus3_3[2] Vsus3_3[3] Vsus3_3[4] Vsus3_3[5] Vsus3_3[6] Vsus3_3[7] Vsus3_3[8] Vsus3_3[9] SM_MAA1 B16 Vsus3_3[0] Vsus3_3[10] Vsus3_3[11] Vsus3_3[13] Vsus3_3[14] Vsus3_3[15] SMAA1 Vsus3_3[12] Vsus3_3[16] Vsus3_3[17] F21 SM_MD3 CPU_BSEL0 4,6 SM_MAA2 F12 SMD3 SMAA2 E21 SM_MD4 SM_MAA3 A16 SMD4 CPU_BSEL1 4,6 RN1 SMAA3 G20 SM_MD5 SM_MAA6 1 2 B12 SMD5 SMAA4 F20 SM_MD6 R72 R73 R74 SM_MAA7 3 4 A12 SMD6 1 1 1 SMAA5 D20 SM_MD7 10K 10K 10K SM_MAA4 5 6 C11 SMD7 SMAA6 F19 SM_MD8 7 8 A11 SMD8 SM_MAA5 SMAA7

E19 SM_MD9 2 2 2 SM_MAA8 10 D12 SMD9 SMAA8 D19 SM_MD10 SM_MAA9 C13 SMD10 SMAA9 E18 SM_MD11 SM_MAA10 E11 SMD11 SM_CAS# 11,12 SMAA10 B18 SM_MD12 SM_MAA11 A13 SMD12 SMAA11 F18 SM_MD13 SM_WE# 11,12 SM_MAA12 B7 SMD13 FSB PMOS kicker SMAA12 G18 SM_MD14 RN2 SMD14 SM_MAA9 11,12 SM_MAB#4 1 2 B15 D17 12 SM_MAB#[7:4] SMAB4# SMD15 SM_MD15 SM_MAB#5 3 4 A15 A3 SM_MD16 JP1 SMAB5# SMD16 1 2 SM_BS0 Reserved Strap SM_MAB#6 5 6 C14 A1 SM_MD17 SMAB6# SMD17 JP2 SM/LM muxing strap, SM_MAB#7 7 8 A14 C1 SM_MD18 1 2 SM_BS1 active low SMAB7# SMD18 10 F2 SM_MD19 JP3 IOQ depth: high = 4, B10 SMD19 1 2 low = 1 SMAC4# SM_MAA11 G3 SM_MD20 YAGEO A10 SMD20 JP4 SMAC5# D6 SM_MD21 1 2 SM_MAA12 Reserved Strap C10 SMD21 SMAC6# C5 SM_MD22 JP5 A9 SMD22 1 2 SM_MAA10 All - Z low SMAC7# B4 SM_MD23 SMD23 JP6 11,12 SM_BS[1:0] B13 D4 1 2 XOR low SM_BS0 SBS0 815E GMCH SMD24 SM_MD24 SM_RAS# D11 C2 SM_BS1 SBS1 SMD25 SM_MD25 544 mBGA D3 SM_MD26 11,12 SM_CSA#[3:0] SM_CSA#0 D15 SMD26 SCSA0# E4 SM_MD27 SM_CSA#1 A17 SMD27 SCSA1# PART 2 F5 SM_MD28 SM_CSA#2 D14 SMD28 SCSA2# G4 SM_MD29 SM_CSA#3 E14 SMD29 SCSA3# J6 SM_MD30 R75 R76 R77 R78 R79 R80 E13 SYSTEM MEMORY SMD30 1 1 1 1 1 1 SCSA4# K5 SMD31 SM_MD31 10K 10K 10K 10K 10K 10K A B17 A SCSA5# A26 SMD32 SM_MD32

11,12 SM_CSB#[3:0] SM_CSB#0 F9 A25 SM_MD33 2 2 2 2 2 2 SCSB0# SMD33 SM_CSB#1 F8 B24 SCSB1# SMD34 SM_MD34 SM_CSB#2 D10 A24 SCSB2# SMD35 SM_MD35 SM_CSB#3 D9 B23 SCSB3# SMD36 SM_MD36 B9 A23 SCSB4# SMD37 SM_MD37 A8 C22 SM_MD38 SCSB5# SMD38 A22 SM_MD39 C16 SMD39 11,12 SM_RAS# SRAS# D21 SM_MD40 D18 SMD40 11,12 SM_CAS# SCAS# B21 SM_MD41 E16 SMD41 11,12 SM_WE# SWE# A21 SM_MD42 11,12 SM_CKE[3:0] SMD42 SM_CKE0 D8 C20 SM_MD43 SCKE0 SMD43 FUNCTION SM_? DESCRIPTION SM_CKE1 E8 B20 SCKE1 SMD44 SM_MD44 SM_CKE2 E9 A20 LOW (P) : XOR TEST MODE SCKE2 SMD45 SM_MD45 XOR RAS# SM_CKE3 D7 C19 HIGH (NP) : NORMAL SCKE3 SMD46 SM_MD46 C8 A19 SCKE4 SMD47 SM_MD47 Tri-state MAA10 LOW(P) : Tri-state MODE C7 A4 SM_MD48 SCKE5 SMD48 HIGH (NP) : NORMAL A2 SM_MD49 F7 SMD49 6 DCLK_WR SCLK B1 SM_MD50 G10 SMD50 NC E1 SMD51 SM_MD51

1 System Bus C179 SM_DQM0 D16 G2 SM_MD52 SDQM0 SMD52 [WE#,CAS#] [1,0] : 100MHz FSB Frequency 22P/50V SM_DQM1 F15 E6 SM_MD53 SDQM1 SMD53

2 0603 5% SM_DQM2 A7 D5 SM_MD54 TDK/TAIYO SDQM2 SMD54 A6 C4 IOQ Depth MAA11 P : IOQ Depth of 1 SM_DQM3 SDQM3 SMD55 SM_MD55 A18 B3 NP : IOQ Depth of 4 SM_DQM4 SDQM4 SMD56 SM_MD56 SM_DQM5 C17 D2 SM_MD57 SDQM5 SMD57 MAA12 LO = FUTURE 0.13 u SOCKET 370 SM_DQM6 B6 E3 SM_MD58 PROCESSORS SDQM6 SMD58 A5 F4 HI = PENTIUM(R) II PROCESSOR OR SM_DQM7 SDQM7 SMD59 SM_MD59 R81 I NTEL CELERON(TM) PROCESSOR 11,12 SM_DQM[7:0] F6 SMD60 SM_MD60 W/CPU = 068XH VCC3_3SBY 1 2 G7 SRCOMP G5 SM_MD61 40.2 SMD61 1% H4 SM_MD62 0603 SMD62 YAGEO J4 SM_MD63 VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] SMD63 K21 K24 L2 L6 L11 L12 L13 L14 L15 L16 L22 L25 M4 M11 M12 M13 M14 M15 M16 N2 N6 N11 N12 N13 N14 N15 N16 N23 P4 P11 P12 P13 P14 P15 P16

THIS DRAWING CONTAINS INFORMATION THAT HAS NOT 815E GMCH PART 2 BEEN VERIFIED FOR Title MANUFACTURING AS AN END USER Low Power Intel® Celeron®/Pemtium® III with 815E PRODUCT. INTEL IS NOT Size Document Number Rev RESPONSIBLE FOR THE MISUSE 0.5 OF THIS INFORMATION. Date: Wednesday, March 27, 2002 Sheet 8 of 34 A A

815E , PART 3:

U3C P24 R2 R6 R11 R12 R13 R14 R15 R16 R23 R25 T4 T11 T12 T13 T14 T15 T16 T21 U2 U7 V4 V6 V20 V22 W2 W7 W23 W25 Y4 Y6 Y8 DISPLAY CACHE VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99]

AND VIDEO INTERFACE VSS[100] VSS[101] VSS[102] DC_CS# P25 AD16 FTD0 FTD[11:0] 24 10 DC_CS# LCS#/GSTOP# LTVDATA0 AF17 FTD1 10 DC_DQM[3:0] DC_DQM0 K26 LTVDATA1 LDQM0/GAD0 AE17 FTD2 DC_DQM1 M24 LTVDATA2 LDQM1/GAD10 AD17 FTD3 AB23 LTVDATA3 VCC3_3 DC_DQM2 LMQM2/SBA2 AF18 FTD4 DC_DQM3 AC24 LTVDATA4 LDQM3/ST1 AD18 LTVDATA5 FTD5 R82 V25 AF20 FTD6 1 LCKE/GAD24 VIDEO DIGITAL OUT LTVDATA6 10K V26 AD20 FTD7 5% 10 DC_CAS# LCAS#/GAD26 LTVDATA7 0603 Y26 AC20 FTD8 YAGEO 10 DC_RAS# LRAS#/GCBE3# INTERFACE LTVDATA8

2 AA26 AF21 FTD9 10 DC_WE# LWE#/SBA5 LTVDATA9 Y25 AE21 LGM_FREQ_SEL/SBA7 LTVDATA10 FTD10 AD21 FTD11 10 DC_MA[11:0] V24 LTVDATA11 DC_MA0 LMA0/GAD22 AB19 N26 LTVBLANK# FTBLNK# 24 DC_MA1 LMA1/GAD15 AC18 DC_MA2 M26 LTVCLKIN/SL_STALL SL_STALL 24 LMA2/GAD11 AE19 DOTCLK DC_MA3 H23 LTVCLKOUT0 FTCLK0 24 LMA3/GCBE0# 815E GMCH AF19 M25 LTVCLKOUT1 FTCLK1 24 DC_MA4 1 LMA4/GAD9 AC16 C180 DC_MA5 N24 LTVVSYNC FTVSYNC 24 LMA5/GAD13 AB17 DO NOT STUFF 18P/50V-NP LTVHSYNC

R24 FTHSYNC 24 2 0603 DC_MA6 LMA6/GPAR Place site w / in 0.5" 544 mBGA 5% DC_MA7 P21 of clock ball (AE24). TDK/TAIYO LMA7/GTRDY# AA20 DC_MA8 T26 LTVDA 3VFTSDA 24,25 LMA8/GAD16 PART3 AB21 U26 LTVCK 3VFTSCL 24,25 DC_MA9 LMA9/GAD20 R26 DC_MA10 LMA10/GFRAME# DISPLAY CACHE, DC_MA11 U24 LMA11/GAD18 AB18 VIDEO, DDCCK 3VDDCCL 25 10 DC_MD[31:0] DC_MD0 K22 AA18 LMD0/GAD8 AND DDCDA 3VDDCDA 25 DC_MD1 K23 AE24 LMD1/GAD7 DCLKREF DOTCLK 6 DC_MD2 J20 HUB INTERFACE Y20 VCC3_3 LMD2/GAD5 IWASTE R83 DC_MD3 J21 AD23 IREFPD 1 2 LMD3/GAD3 IREF DC_MD4 J22 GRAPHICS INTERFACE 174 LMD4/GAD1 AF22 DC_MD5 L26 VSYNC CRT_VSYNC 25 LMD5/GAD6 1 DISPLAY CACHE AF23 CX1 Do not stuff Cx RN3 L24 HSYNC CRT_HSYNC 25 DC_MD6 LMD6/GAD4 Place Site within 0.5" Place as close as AD22 18pF of clock ball (AA21) 2 1 K25 RED VID_RED 25 WBF# DC_MD7 2 Possible to GMCH LMD7/GAD2 AE22 4 3 ADSTB1 DC_MD8 M21 GREEN VID_GREEN 25 and via straight to LMD8/GAD12 AE23 6 5 N22 BLUE VID_BLUE 25 A ADSTB0 DC_MD9 LMD9/GAD14 VSS plane. A 8 7 N21 SBSTB DC_MD10 LMD10/GCBE1# 8P4R-8.2K P26 DC_MD11 LMD11/GDEVSEL# DC_MD12 P23 F22 LMD12/GIRDY# HLCLK GMCH_3V66 6 DC_MD13 T25 H24 HL0 LMD13/GCBE2# HL0 T22 H26 HL[10:0] 13 DC_MD14 LMD14/GAD17 HL1 HL1 DC_MD15 T23 H25 HL2 LMD15/GAD19 HL2 1 C181 D o not stuff DC_MD16 T24 G24 HL3 LMD16/GAD21 HL3 18pF

U21 F24 2 DC_MD17 LMD17/GAD23 HL4 HL4 DC_MD18 V21 E26 HL5 LMD18/GAD25 HL5 VCC1_8 DC_MD19 W21 E25 HL6 LMD19/GAD27 HUB I/F HL6 DC_MD20 W22 D26 HL7 LMD20/GAD29 HL7 1 Y21 D25 R84 DC_MD21 LMD21/GAD31 HL8 HL8 Y22 D24 300 1% DC_MD22 LMD22/SBA6 HL9 HL9

DC_MD23 AA22 C26 HL10 2 LMD23/SBA4 HL10 AC26 H21 HUBREF DC_MD24 LMD24/PIPE# HUBREF HUBREF 13 DC_MD25 AB25 G25 1 LMD25/SBA1 HLSTB HLSTB 13 R85 Place HUBREF Generation DC_MD26 AB26 F26 C182 C183 LMD26/SBA3 HLSTB# R86 HLSTB# 13 300 1% Circuit in the middle of DC_MD27 AE26 H20 HCOMP 1 2 0.01uF 0.1 uF LMD27/GREQ# HCOMP VCC1_8 GMCH and ICH. Must be 40.2 Place cap 2 DC_MD28 AD24 1% within 4" of GMCH and LMD28/ST0 as close ICH2. DC_MD29 AC23 R87 LMD29/ST2 AD25 1 2 as possible DC_MD30 AD26 GGNT# VCC3_3 to GMCH LMD30/RBF# 8.2K AB22 M22 DC_MD31 LMD31/SBA0 ADSTB0 ADSTB0 R89 R88 R90 22 L23 1 2 ADSTB0# 1 2 1 2 W26 VCC3_3 10 DC_CLK0 LTCLK0/GAD30 U22 ADSTB1 8.2K 15 1 2 W24 ADSTB1 R92 1% 10 DC_CLK1 LTCLK1/GAD28 V23 1 2 R91 22 AGP ADSTB1# R22 Y23 SBSTB 8.2K R94 OCLOCK SBSTB R93 1 P22 AA24 1 2 RCLK RCLOCK SBSTB# 301 1% 8.2K AB24 WBF# WBF# 2

J24 1 C184 AGPREF R95 15P/50V J26 1 2 R96 GRCOMP Place within 0.5" of 1

2 0603 5% 40.2 the GMCH Ball 200 TDK/TAIYO 1% 1% 2 VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136]_Vssdaca

Y10 Y17 Y19 AA2 AA9 AA12 AA14 AA16 AA23 AA25 AB4 AC2 AC5 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC25 AE2 AE4 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE25 AF24 THIS DRAWING CONTAINS INFORMATION THAT HAS NOT 815E GMCH PART 3 BEEN VERIFIED FOR Title MANUFACTURING AS AN END USER Low Power Intel® Celeron®/Pemtium® III with 815E PRODUCT. INTEL IS NOT Size Document Number Rev RESPONSIBLE FOR THE MISUSE 0.5 OF THIS INFORMATION. Date: Wednesday, March 27, 2002 Sheet 9 of 34 A A 4MB Display Cache

VCC3_3 VCC3_3

U4A

U5A 1 25 7 13 38 44 1 25 7 13 38 44

DC_MA[11:0] VDD_1 VDD_2

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 DC_MD[31:0] 9 VDD_1 VDD_2 DC_MA0 21 2 DC_MD16

9 DC_MA[11:0] DC_MA0 21 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 2 DC_MD0 A0 DQ0 A0 DQ0 DC_MA1 22 3 DC_MD17 DC_MA1 22 3 DC_MD1 A1 DQ1 A1 DQ1 DC_MA2 23 5 DC_MD18 DC_DQM[3:0] 9 DC_MA2 23 5 DC_MD2 A2 DQ2 VCC3_3 A2 DQ2 DC_MA3 24 6 DC_MD19 DC_MA3 24 6 DC_MD3 A3 DQ3 A3 DQ3 DC_MA4 27 8 DC_MD20 DC_MA4 27 8 DC_MD4 A4 DQ4 A4 DQ4 DC_MA5 28 9 DC_MD21 A5 DQ5

DC_MA5 28 9 DC_MD5 OP A5 DQ5 DC_MA6 29 11 DC_MD22 DC_MA6 29 11 DC_MD6 A6 DQ6 A6 DQ6 DC_MA7 30 12 DC_MD23 DC_MA7 30 12 DC_MD7 A7 DQ7 R97A A7 DQ7 DC_MA8 31 39 DC_MD24 DC_MA8 31 39 DC_MD8 A8 DQ8 4.7K A8 DQ8 DC_MA9 32 40 DC_MD25 DC_MA9 32 40 DC_MD9 A9 DQ9 A9 DQ9 DC_MA10 20 42 DC_MD26 A10 DQ10 DC_MA10 20 42 DC_MD10 50-PIN TS A10 DQ10 50-PIN TSOP DC_MA11 19 43 DC_MD27 A11 DQ11

DC_MA11 19 43 DC_MD11 SDRAM A11 DQ11 DC_MD28

SDRAM 45 45 DC_MD12 DQ12 DQ12 A 35 46 DC_MD29 A 35 46 DC_MD13 9 DC_CLK1 CLK DQ13 9 DC_CLK0 CLK DQ13 DC_CKE 34 48 DC_MD30 DC_CKE 34 48 DC_MD14 CKE DQ14 CKE DQ14 49 DC_MD31 49 DC_MD15 DQ15 DQ15 DC_CS# 18 18 CS# CS# 9 DC_CS# DC_RAS# 17 36 DC_DQM3 RAS# 17 36 DC_DQM1 UDQM 9 DC_RAS# RAS# UDQM DC_CAS# 16 14 DC_DQM2 CAS# 16 14 DC_DQM0 LDQM 9 DC_CAS# CAS# LDQM DC_WE# 15 WE# 15 9 DC_WE# WE#

33 33 NC_1 NC_1 37 37 NC_2 NC_2 VSSQ_4 VSSQ_3 VSSQ_2 VSSQ_1 VSS_2 VSS_1 VSSQ_4 VSSQ_3 VSSQ_2 VSSQ_1 VSS_2 VSS_1 4 10 41 47 26 50 4 10 41 47 26 50

DISPLAY CACHE Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 10of 34 A A

SYSTEM MEMORY

8,12 SM_MD[63:0] 22 57 17 62 52 47 37 27 12 32 42 D0 D7 D2 MD15 MD60 MD10 MD20 MD35 MD39 MD14 MD59 MD24 MD30 MD19 MD34 MD50 MD55 MD29 MD45 MD49 MD54 MD25 MD44 MD40 MD4 MD9 MD5 _MD21 _MD36 _MD56 _MD58 _MD63 _MD11 _MD48 _MD46 _MD38 _MD13 _MD16 _MD18 _MD23 _MD28 _MD31 _MD33 _MD41 _MD43 _MD51 _MD53 _MD61 _MD26 _MD3 _MD1 _MD8 _MD6 SM_ SM_ SM_MD SM_ SM_ SM SM_ SM SM_ SM SM_MD SM SM SM SM_ SM_MD SM SM_ SM_MD SM_M SM_ SM_ SM SM_ SM_ SM SM_ SM_MD SM_ SM_MD SM SM_ SM_ SM SM SM SM SM SM SM_MD SM SM_ SM_ SM_MD SM_MD SM_ SM SM_ SM SM SM SM_MD SM SM_MD SM_ SM_ SM_M SM SM SM_ SM SM_ SM_M SM 2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 21 22 52 53 105 106 136 137 DQ7 DQ8 DQ6 DQ5 DQ4 DQ3 DQ2 DQ9 VCC3_3SBY DQ0 DQ1 DQ60 DQ63 DQ50 DQ51 DQ53 DQ56 DQ57 DQ58 DQ59 DQ40 DQ41 DQ42 DQ43 DQ46 DQ47 DQ48 DQ49 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ52 DQ44 DQ45 DQ54 DQ55 DQ61 DQ62 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7

168 162 VCC17 VSS18 157 152 VCC16 VSS17 143 148 VCC15 VSS16 133 138 VCC14 VSS15 84 127 VCC13 VSS14 73 116 VCC12 VSS13 59 107 VCC11 VSS12 49 96 VCC10 VSS11 124 85 VCC9 VSS10 110 DIMM SOCKET 78 VCC8 VSS9 102 68 VCC7 VSS8 90 64 VCC6 168 PIN VSS7 41 54 VCC5 VSS6 40 43 A VCC4 VSS5 A 26 32 VCC3 VSS4 18 23 VCC2 VSS3 6 12 VCC1 VSS2 1 VSS1

J2A DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 S0# S1# S2# S3# WE# RAS# SMBDATA SMBCLK REGE SA0 SA1 SA2 CLK0 WP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 CLK1 CLK2 CLK3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 CAS# CKE0 CKE1

42 125 79 163 33 117 34 118 35 119 36 120 37 121 38 123 126 132 122 39 28 29 46 47 112 113 130 131 30 114 45 129 27 111 115 128 63 82 83 147 165 166 167 81 24 25 31 44 48 50 51 61 62 80 108 109 134 135 145 146 164 VCC3_3SBY

R98A

4.7K M2 M7 B#1 AA5 AA0 LK0 AA10 QM0 QM4 QM5 KE0 CLK2 CLK3 BS0 CSA#0 CSA#1 _MAA2 _MAA8 _MAA3 _MAA7 _DQM1 _DQM3 _DQM6 _CSB#0 MCLK1 SM SM_MAA4 SM SM_MAA9 SM_MAA1 SM SM_M SM SM_M SM_MAA6 SM_ SM_BS1 SM_D SM SM_DQ SM SM_D SM_D SM SM_DQ SM_ SM_ SM SM_CS SM_MAA11 SM_M SM_MAA12 SM_C SM_CKE1 MEMC ME MEM MEM

6,12 MEMCLK[7:0]

8,12 SM_MAA[12:0]

8,12 SM_BS[1:0]

8,12 SM_DQM[7:0] 8,12 SM_CSA#[3:0] 8,12 SM_CSB#[3:0] 8,12 SM_WE# 8,12 SM_CAS# 8,12 SM_RAS#

8,12 SM_CKE[3:0] 12,14,16,25,31,32 SMBDATA 12,14,16,25,31,32 SMBCLK

SYSTEM MEMORY PART 1 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 11of 34 A A SYSTEM MEMORY PART 2

SYSTEM MEMORY

8,11 SM_MD[63:0] 3 4 8 9 3 4 8 9 3 4 8 9 3 4 8 9 3 4 8 9 3 3 4 8 9 11 16 21 26 31 36 41 46 51 56 61 D1 D6 SM_MD0 SM_M SM_MD2 SM_MD SM_MD SM_MD5 SM_M SM_MD7 SM_MD SM_MD SM_MD10 SM_MD SM_MD12 SM_MD1 SM_MD1 SM_MD15 SM_MD SM_MD17 SM_MD1 SM_MD1 SM_MD20 SM_MD SM_MD22 SM_MD2 SM_MD2 SM_MD25 SM_MD SM_MD27 SM_MD2 SM_MD2 SM_MD30 SM_MD SM_MD32 SM_MD3 SM_MD3 SM_MD35 SM_MD SM_MD37 SM_MD3 SM_MD3 SM_MD40 SM_MD SM_MD42 SM_MD4 SM_MD4 SM_MD45 SM_MD SM_MD47 SM_MD4 SM_MD4 SM_MD50 SM_MD SM_MD52 SM_MD5 SM_MD5 SM_MD55 SM_MD SM_MD57 SM_MD5 SM_MD5 SM_MD60 SM_MD SM_MD62 SM_MD6 2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 21 22 52 53 105 106 136 137 VCC3_3SBY DQ7 DQ8 DQ6 DQ5 DQ4 DQ3 DQ2 DQ9 DQ0 DQ1 DQ60 DQ63 DQ50 DQ51 DQ53 DQ56 DQ57 DQ58 DQ59 DQ40 DQ41 DQ42 DQ43 DQ46 DQ47 DQ48 DQ49 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ52 DQ44 DQ45 DQ54 DQ55 DQ61 DQ62 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7

168 162 VCC17 VSS18 157 152 VCC16 VSS17 143 148 VCC15 VSS16 133 138 VCC14 VSS15 84 127 VCC13 VSS14 73 116 VCC12 VSS13 59 107 VCC11 VSS12 49 96 VCC10 VSS11 124 85 VCC9 VSS10 110 DIMM SOCKET 78 VCC8 VSS9 102 68 VCC7 VSS8 90 64 VCC6 168 PIN VSS7 41 54 VCC5 VSS6 40 43 VCC4 VSS5 26 32 VCC3 VSS4 18 23 VCC2 VSS3 6 12 A VCC1 VSS2 A 1 VSS1

J3A DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 S0# S1# S2# S3# WE# RAS# SMBDATA SMBCLK REGE SA0 SA1 SA2 CLK0 WP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 CLK1 CLK2 CLK3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 CAS# CKE0 CKE1 42 125 79 163 33 117 34 118 35 119 36 120 37 121 38 123 126 132 122 39 28 29 46 47 112 113 130 131 30 114 45 129 27 111 115 128 63 82 83 147 165 166 167 81 24 25 31 44 48 50 51 61 62 80 108 109 134 135 145 146 164

VCC3_3SBY A#3 M7 M2 LK4 AA10 AA0 QM4 QM5 QM0 KE2 CLK6 CLK7 BS0 CSB#3 _MAA2 _MAA8 _MAA3 MCLK5 _DQM6 _DQM3 _DQM1

_CSB#2 R99A _CSA#2 AB#5 SM SM SM_MAA11 SM SM_MAA1 SM_MAA9 SM_M SM_MAA12 SM_CS SM_M ME MEM MEMC MEM SM_BS1 SM SM_DQ SM_ SM_D SM SM_D SM_DQ SM SM_D SM_C SM_CKE3 SM SM_ SM MAB#7 4.7K SM_MAB#4 SM_M SM_MAB#6 SM_ 6,11 MEMCLK[7:0] VCC3_3SBY

R100A 8,11 SM_MAA[12:0]

4.7K 8 SM_MAB#[7:4]

8,11 SM_BS[1:0]

8,11 SM_DQM[7:0]

8,11 SM_CSA#[3:0] 8,11 SM_CSB#[3:0] 8,11 SM_WE# 8,11 SM_CAS# 8,11 SM_RAS#

8,11 SM_CKE[3:0] 11,14,16,25,31,32 SMBDATA 11,14,16,25,31,32 SMBCLK

SYSTEM MEMORY PART 2 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 12of 34 A A VCC3_3 VCC1_8 VCC1_8 V3SB V3SB V3SB V1_8SB V1_8SB

U6A ICH2_5 E14 E15 E16 E17 E18 F18 G18 H18 J18 P18 R18 R5 T5 U5 V5 V6 V7 V8 D10 E5 K19 L19 P5 V9 D2 U18 T18 F5 G5 V17 V18 V14 V15 V16 H5 J5 17,18 AD[0..31] AD[0..31] AD0 AA4 HL[10:0] HL[10:0] 9 AD1 AB4 AD0 AD1

AD2 Y4 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 D11 CPU_A20M# 4 AD3 W5 AD2 A20M# A12 AD3 CPUSLP# CPU_SLP# 4 AD4 W4 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 R22 CPU_FERR# 4 AD5 Y5 AD4 FERR# A11 CPU_IGNNE# 4 AD6 AB3 AD5 IGNNE# C12 CPU_INIT# 4,15 AD7 AA5 AD6 INIT# C11 CPU_INTR 4 AD8 AB5 AD7 INTR B11 AD8 NMI CPU_NMI 4 AD9 Y3 B12 CPU_SMI# 4 AD10 W6 AD9 SMI# C10 CPU_STPCLK# 4 AD11 W3 AD10 STPCLK# B13 KBRST# 16,32 AD12 Y6 AD11 RCIN# C13 A20GATE 16,32 AD13 Y2 AD12 A20GATE A13 AD13 CPUPWRGD CPU_PWGD 4 AD14 AA6 AD14 AD15 Y1 A4 HL0 TPHL1 AD16 V2 AD15 HL0 B5 HL1 AD17 AA8 AD16 HL1 A5 HL2 1 AD18 V1 AD17 HL2 B6 HL3 AD18 HL3 Test point AD19 AB8 B7 HL4 AD19 HL4 AD20 U4 A8 HL5 Place R VCC1_8 AD20 HL5 AD21 W9 B8 HL6 within 0.5" AD22 U3 AD21 HL6 A9 HL7 of HLCOMP AD23 Y9 AD22 HL7 C8 HL8 AD23 HL8 AD24 U2 C6 HL9 pin via a PR1 AD25 AB9 AD24 HL9 C7 HL10 10 mil wide AD26 U1 AD25 HL10 C5 trace 40,1% AD27 W10 AD26 HL11 A6 HLSTB 9 AD28 T4 AD27 HLSTB A7 AD28 HLSTB# HLSTB# 9 AD29 Y10 A3 AD30 T3 AD29 HLCOMP B4 HUBREF 9 AD31 AA10 AD30 ICH2 Part 1 HUBREF AD31 P1 BC7 PIRQ#A 17,18,32 AA3 PIRQ#A P2 17,18 C_BE#0 C_BE#0 PIRQ#B PIRQ#B 17,18,32 AB6 P3 0.01UF 17,18 C_BE#1 PIRQ#C 17,18,32 Y8 C_BE#1 PIRQ#C N4 17,18 C_BE#2 C_BE#2 PIRQ#D PIRQ#D 17,18,32 17,18 C_BE#3 AA9 C_BE#3 F21 IRQ14 15 W11 IRQ14 C16 6 PCLK_0/ICH PCICLK IRQ15 IRQ15 15 V3 N20 Place as close as A 17,18,32 FRAME# ICH_APICCLK 6 A C185 AB7 FRAME# APICCLK N19 17,18,32 DEVSEL# CPU_APIC0 4 Possible to ICH2 W8 DEVSEL# APICD1 P22 17,18,32 IRDY# CPU_APIC1 4 and via straight 10PF V4 IRDY# APICD0 N21 17,18,32 TRDY# TRDY# SERIRQ SERIRQ 16,32 to VSS plane NPOP W1 17,18,32 STOP# STOP# AA15 R2 32 ICHRST# PREQ#0 17,32 AA7 PCIRST# REQ#0 R3 17,18,32 PLOCK# PREQ#1 17,32 W2 PLOCK# REQ#1 T1 17,18 PAR PREQ#2 18,32 W7 PAR REQ#2 AB10 17,18,32 SERR# PREQ#3 18,32 Y7 SERR# REQ#3 P4 17,18,32 PERR# PERR# REQ#4 PREQ#4 32 Y15 L3 17,18 PCI_PME# PME# REQ#B/GPIO01/REQ#5 PREQ#5 32 M3 M2 32 PCI_REQ#A PGNT#0 17 L2 REQ#A/GPIO0 GNT#0 M1 PGNT#1 17 GNT#A/GPIO16 GNT#1 R4 GNT#2 PGNT#2 18 N3 T2 32 PIRQ#E N2 PIRQ#E/GPIO02 GNT#3 R1 PGNT#3 18 32 PIRQ#F N1 PIRQ#F/GPIO03 GNT#4 L4 32 PIRQ#G M4 PIRQ#G/GPIO04 GNT#B/GPO17/GNT#5 32 PIRQ#H Y11 PIRQ#H/GPIO05 G2 15 P66DET GPIO06 LAN_RXD0 LAN_RXD0 26 AA11 G1 15 S66DET LAN_RXD1 26 Y14 GPIO07 LAN_RXD1 H1 32 GPI8 LAN_RXD2 26 W14 GPIO08 LAN_RXD2 RN4 22/8P4R 31 EXTSMI# AB15 GPIO12 F3 1 2 16,32 LPC_PME# LAN_TXD0 26 A15 GPIO13 LAN_TXD0 F2 3 4 GPIO18 LAN_TXD1 LAN_TXD2 26 D14 F1 5 6 LAN_TXD1 26 C14 GPIO19 LAN_TXD2 7 8 L1 GPIO20 B14 GPIO21 H2 LAN_RSTSYNC 26 A14 GPIO22 LAN_RSTSYNC G3 15 GPIO23 GPIO23 LAN_CLK LAN_CLK 26 AB14 32 GPIO27 AA14 GPIO27 32 GPIO28 GPIO28 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 A1 A10 A2 A21 A22 AA1 AA2 AA21 AA22 AB1 AB2 AB21 AB22 B1 B10 B2 B21 B22 B3 B9 C2 C3 C4 C9 D3 D5 D6 D7 D8 D9 E6 E7 E8 E9 J10 J11 J12 J13 J14 J9 K1 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M9 M10 M11 M12 M13 M14 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 ICH2 PART 1 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 13of 34 A A B C D E V3SB 6 ICH_CLK14 ICH_CLK14 VCCRTC VCCT1_5 VCC5SBY

D1 C186 C187 SS12/SMD 2.2uF 0.1uF

R101 1K VCC5 R102 1K VCC3_3 C188 4 C189 BC8 BC9 D2 SS12/SMD 4 1.0uF U7B U21 D12 D13 V19 M20 K2 1.0UF 0.1UF 0.1UF W15 32 GPIO25 V21 GPIO25 GPIO24 AA13 16,32 OVT# THRM# JP6: W16 V5REF2 V5REF1 E21 6,16,30 SLP_S3# SLP_S3# VCCRTC PDCS#1 PDCS#1 15

AB18 V_CPU_IO V_CPU_IO C15 1-2 Normal (default) 30 SLP_S5# SLP_S5# SDCS#1 SDCS#1 15 R20 V5REF_SUS E19 2-3 Clear CMOS 16,27 PWROK PDCS#3 15 Y16 PWROK PDCS#3 D15 RSM_PWROK SDCS#3 SDCS#3 15 JP7 W21 PDA[0..2] 16 PWRBTN# PDA[0..2] 15 R103 15K 1 AA17 PWRBTN# F20 PDA0 32 ICH_RI# 2 R21 RI# PDA0 F19 PDA1 16,27 RSMRST# C190 3 Y17 RSMRST# PDA1 E22 PDA2 AA18 SUS_STAT# PDA2 A16 SDA0 16 SUSCLK SUSCLK SDA0 D3 1.0UF CLR_CM0S AA16 D16 SDA1 11,12,16,25,31,32 SMBDATA R104 AB16 SMBDATA SDA1 B16 SDA2 11,12,16,25,31,32 SMBCLK AB17 SMBCLK SDA2 SDA[0..2] 32 SMBALERT# SDA[0..2] 15 SS12/SMD 1K T19 SMBALTER#/GPI11 G22 16,28 CASEOPEN# PDREQ 15 INTRUDER# PDREQ B18 SDREQ SDREQ 15 R105 1K F22 PDDACK# 15 M19 PDDACK# B17 SDDACK# 15 C191 P20 CLK14 SDDACK# G19 6,16 USBCLK PDIOR# 15 D4 CLK48 PDIOR# D17 3 6 ICH_3V66 SDIOR# 15 3 O.O47uF CLK66 SDIOR# G21 PDIOW# PDIOW# 15 BAT1 VBIAS T21 C17 SDIOW# 15 RTCX1 U22 VBIAS ICH2 Part 2 SDIOW# G20 PIORDY 15 BATTERY RTCX2 T22 RTCX1 PIORDY A17 SIORDY 15 RTCRST# T20 RTCX2 SIORDY RTCRST# H19 PDD0 PDD0 R106 H22 PDD1 V22 PDD1 J19 PDD2 20,32 AC_RST# P19 AC_RST# PDD2 J22 PDD3 20 AC_SYNC 10M C192 R19 AC_SYNC PDD3 K21 PDD4 20 AC_BITCLK P21 AC_BITCLK PDD4 L20 PDD5 20,32 AC_SDOUT AC_SDOUT PDD5 X18PF Y22 M21 PDD6 20,32 AC_SDIN0 R107 10M W22 AC_SDIN0 PDD6 M22 PDD7 32 AC_SDIN1 N22 AC_SDIN1 PDD7 L22 PDD8 31,32 ICH_SPKR SPKR PDD8 Y2 L21 PDD9 15,16 LAD0 Y12 PDD9 K22 PDD10 LAD0/FWH0 PDD10 15,16 LAD1 W12 K20 PDD11 32.768KHZ 15,16 LAD2 AB13 LAD1/FWH1 PDD11 J21 PDD12 C193 C194 15,16 LAD3 AB12 LAD2/FWH2 PDD12 J20 PDD13 15,16 LFRAME# AB11 LAD3/FWH3 PDD13 H21 PDD14 18pF 18pF Y13 LFRAME#/FWH4 PDD14 H20 PDD15 16 LDRQ#0 LDRQ#0 PDD15 W13 PDD[0..15] PDD[0..15] 15 RN5 15/8P4R LDRQ#1 D18 SDD0 SDD0 2 1 2 W17 B19 SDD1 2 19 USBP0P 3 4 Y18 USBP0P SDD1 D19 SDD2 19 USBP0N 5 6 AB19 USBP0N SDD2 A20 SDD3 19 USBP1P USBP1P SDD3 7 8 AA19 C20 SDD4 19 USBP1N W18 USBP1N SDD4 C21 SDD5 Y19 USBP2P SDD5 D22 SDD6 AB20 USBP2N SDD6 E20 SDD7 VCC3_3 AA20 USBP3P SDD7 D21 SDD8 USBP3N SDD8 C22 SDD9 W19 SDD9 D20 SDD10 19 USBOC#0-1 Y20 OC#0 SDD10 B20 SDD11 Y21 OC#1 SDD11 C19 SDD12 R108 W20 OC#2 SDD12 A19 SDD13 OC#3 SDD13 1K C18 SDD14 K4 SDD14 A18 SDD15 V3SB 26 EE_CS K3 EE_CS SDD15 SDD[0..15] 26 EE_DIN SDD[0..15] 15 J4 EE_DIN U19 26 EE_DOUT SMLINK0 18,32 J3 EE_DOUT SMLINK0 V20 26 EE_SHCLK EE_SHCLK SMLINK1 SMLINK1 18,32 B15 VRM_PWRGD 29 VRMPWRGD U20 R109 1K TP0 AA12 R110 R111 R112 R113 R114 FS0 TPFS1 1 1 1 560K 15K 15K 15K 15K ICH2_5 Test point

ICH2 PART 2 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 14of 34 A B C D E 8 7 6 5 4 3 2 1 IDE

FWH PDD[0..15] 14 PDD[0..15] VCC3_3 VCC3_3 PDA[0..2] 14 PDA[0..2] IDE1 IDERST# R115 33 1 2 32 IDERST# PDD7 3 4 PDD8 D D BC10 BC11 BC12 BC13 VCC3_3 PDD65 6 PDD9 R116 PDD5 7 8 PDD10 0.1UF PDD4 9 10 PDD11 0 0.1UF 0.1UF 0.1UF PDD3 11 12 PDD12 R117 PDD2 13 14 PDD13 PDD1 15 16 PDD14 4.7K PDD0 17 18 PDD15 U8 19 20 1 32 21 22 2 VPP VCC 31 14 PDREQ 23 24 7,16,24,32 PCIRST# RST# CLK PCLK_6 6 14 PDIOW# R118 8.2K 3 30 R119 8.2K 25 26 4 FGPI3 FGPI4 29 14 PDIOR# 27 28 5 FGPI2 IC 28 14 PIORDY 29 30 6 FGPI1 GNDA 27 14 PDDACK# 31 32 7 FGPI0 VCCA 26 13 IRQ14 PDA1 33 34 WP# GND P66DET 13 13 GPIO23 8 25 VCC3_3 R120 8.2K PDA0 35 36 9 TBL# VCC 24 37 38 CPU_INIT# 4,13 PDCS#3 14 10 ID3 INIT# 23 14 PDCS#1 39 40 LFRAME# 14,16 11 ID2 FWH4 22 31 IDEACTP# 12 ID1 RFU 21 PIN_2X20 ID0 RFU 14,16 LAD0 13 20 PDA2 R121 14,16 LAD1 14 FWH0 RFU 19 C195 14,16 LAD2 15 FWH1 RFU 18 10K 16 FWH2 RFU 17 LAD3 14,16 47PF C GND FWH3 C FWH32

SDD[0..15] 14 SDD[0..15] SDA[0..2] 14 SDA[0..2] IDE2 IDERST# R122 33 1 2 SDD7 3 4 SDD8 VCC3_3 SDD6 5 6 SDD9 SDD5 7 8 SDD10 SDD4 9 10 SDD11 SDD3 11 12 SDD12 R123 SDD2 13 14 SDD13 SDD1 15 16 SDD14 4.7K SDD0 17 18 SDD15 19 20 21 22 14 SDREQ 23 24 14 SDIOW# 25 26 14 SDIOR# 27 28 14 SIORDY B 29 30 B 14 SDDACK# 31 32 13 IRQ15 SDA1 33 34 S66DET 13 VCC3_3 R124 8.2K SDA0 35 36 37 38 SDCS#3 14 14 SDCS#1 39 40 31 IDEACTS# PIN_2X20 R125 SDA2 C196 10K 47PF

A A

FWH AND IDE 1 & 2 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 15of 34 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

IRRX 23 IRTX 23 RI#1 22 DCD#1 22 11,12,14,25,31,32 SMBDATA R126 TXD1 22 300 RXD1 22 11,12,14,25,31,32 SMBCLK R127 DTR#1 22 300 RTS#1 22 28 -5VIN DSR#1 22 28 -12VIN CTS#1 22 28 +12VIN 28 +3.3VIN CASEOPEN# 14,28 D 28 VTT D 28 VCORE SUSCLK 14 28 HM_VREF 28 VTIN3 SLP_S3# 6,14,30 FB1 R128 VCC5SBY VCC5 1 2 IOAVCC 10K R129 PS_ON 27 FB2 0 1 2 BEAD PWROK 14,27 BC14 R130 V3SB 0.1UF 10K BEAD RSMRST# 14,27 4,28 THRMDN PANSWIN 31 VCCRTC PWRBTN# 14 VCC5 MDAT 23 BC15 BC16 MCLK 23 0.1UF 0.1UF U9 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS VCC RIB# SINB -5VIN VBAT VREF AVCC MCLK VTIN3 AGND PSIN# MDAT -12VIN RTSB# CTSB# +12VIN DTRB# DSRB# DCDB# SOUTB +3.3VIN PSOUT# VCOREA VCOREB SCL/GP21 SDA/GP22 SUSCLKIN IRTX/GP26 IRRX/GP25 PLED/GP23 WDTO/GP24 CASEOPEN# CIRRX/GP34 PWROK/GP32 4,28 VTIN2 103 SUSCIN/GP30 64

VTIN2 PWRCTL#/GP31 RSMRST#/GP33 SUSLED/GP35 SUSLED 31 C 28 VTIN1 104 63 C KDAT 23 14,32 OVT# 105 VTIN1 KDAT 62 OVT# KCLK KCLK 23 106 61 VCC5SBY 107 VID4 VSB 60 KBRST# 13,32 108 VID3 KBRST 59 VID2 GA20M A20GATE 13,32 109 58 KEYLOCK# 31 110 VID1 KBLOCK# 57 RI#0 22 28 FANIO3 111 VID0 RIA# 56 DCD#0 22 28 FANIO2 112 FANIO3 DCDA# 55 28 FANIO1 113 FANIO2 VSS 54 FANIO1 SOUTA TXD0 22 114 53 RXD0 22 115 VCC SINA 52 DTR#0 22 28 FANPWM2 116 FANPWM2 DTRA# 51 W83627HF RTS#0 22 28 FANPWM1 117 FANPWM1 RTSA# 50 DSR#0 22 31 BEEP 118 VSS DSRA# 49 BEEP CTSA# CTS#0 22 23 MIDI_IN 119 48 VCC5 23 MIDI_OUT 120 MSI/GP20 VCC 47 STB# 22 23 J1BUTTON2 121 MSO/IRQIN0 STB# 46 AFD# 22 23 J2BUTTON2 122 GPSA2/GP17 AFD# 45 ERR# 22 23 JOY1Y 123 GPSB2/GP16 ERR# 44 GPY1/GP15 INIT# PAR_INIT# 22 23 JOY2Y 124 43 SLIN# 22 23 JOY2X 125 GPY2/P16/GP14 SLIN# 42 23 JOY1X 126 GPX2/P15/GP13 PD0 41 23 J2BUTTON1 127 GPX1/P14/GP12 PD1 40 BC17 23 J1BUTTON1 128 GPSB1/P13/GP11 PD2 39 0.1UF GPSA1/P12/GP10 PD3

B B DRVDEN0 DRVDEN1 INDEX# MOA# DSB# DSA# MOB# STEP# WD# WE# VCC TRAK0# WP# HEAD# DSKCHG# CLKIN PME# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 VCC3V LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 DIR# RDATA# PDR0 22 W83627HF FDD Signals Trace 8 or 10 mil PDR1 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PDR2 22 FDC1 PDR3 22 1 2 RWC# PDR4 22 3 4 PDR5 22 5 6 DS1# PDR6 22 7 8 PDR7 22 9 10 MOA# ACK# 22 11 12 DSB# BUSY 22 13 14 DSA# PE 22 15 16 MOB# SLCT 22 17 18 DIR# 19 20 STEP# PCIRST# 7,15,24,32 21 22 WD# VCC5 23 24 WE# 25 26 VCC3_3 27 28 29 30 31 32 HEAD# BC18 BC19 33 34 .1U .1U

HEADER_17X2 6,14 SIO_CLK24 13,32 LPC_PME# A 6 PCLK_4 A 14 LDRQ#0 13,32 SERIRQ

14,15 LAD3 14,15 LAD2 SUPER I/O 14,15 LAD1 14,15 LAD0 Title 14,15 LFRAME# Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 16of 34 8 7 6 5 4 3 2 1 A B C D E

V3SB V3SB VCC5 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC5 VCC5 VCC5 VCC12 VCC12- VCC12 VCC12-

4 4 PCI1 PCI2 B1 A1 B1 A1 B2 -12V TRST# A2 B2 -12V TRST# A2 B3 TCK +12V A3 B3 TCK +12V A3 GND TMS GND TMS B4 A4 B4 A4 B5 TDO TDI A5 B5 TDO TDI A5 B6 +5V +5V A6 B6 +5V +5V A6 PIRQ#B PIRQ#A 13,18,32 B7 +5V INTA# A7 PIRQ#C B7 +5V INTA# A7 PIRQ#D 13,18,32 PIRQ#B PIRQ#C 13,18,32 B8 INTB# INTC# A8 PIRQ#A B8 INTB# INTC# A8 13,18,32 PIRQ#D INTD# +5V INTD# +5V B9 A9 B9 A9 B10 PRSNT#1 RESERVED A10 B10 PRSNT#1 RESERVED A10 B11 RESERVED +5V(I/O) A11 B11 RESERVED +5V(I/O) A11 B12 PRSNT#2 RESERVED A12 B12 PRSNT#2 RESERVED A12 B13 GND GND A13 B13 GND GND A13 GND GND GND GND B14 A14 B14 A14 B15 RESERVED RESERVED A15 B15 RESERVED RESERVED A15 PCI_RST# 6 PCLK_1 B16 GND RST# A16 PCI_RST# 18,32 6 PCLK_2 B16 GND RST# A16 B17 CLK +5V(I/O) A17 B17 CLK +5V(I/O) A17 PGNT#0 13 PGNT#1 13 B18 GND GNT A18 B18 GND GNT A18 13,32 PREQ#0 REQ# GND 13,32 PREQ#1 REQ# GND B19 A19 B19 A19 PCI_PME# PCI_PME# 13,18 AD31 B20 +5V(I/O) PME# A20 AD30 AD31 B20 +5V(I/O) PME# A20 AD30 AD29 B21 AD31 AD30 A21 AD29 B21 AD31 AD30 A21 AD29 +3.3V AD29 +3.3V 3 B22 A22 AD28 B22 A22 AD28 3 AD27 B23 GND AD28 A23 AD26 AD27 B23 GND AD28 A23 AD26 AD27 AD26 AD27 AD26 AD25 B24 A24 AD25 B24 A24 B25 AD25 GND A25 AD24 B25 AD25 GND A25 AD24 C_BE#3 B26 +3.3V AD24 A26 R_AD16 R131 AD16 C_BE#3 B26 +3.3V AD24 A26 R_AD17 R132 AD17 AD23 B27 C/BE#3 IDSEL A27 100 AD23 B27 C/BE#3 IDSEL A27 100 B28 AD23 +3.3 A28 AD22 B28 AD23 +3.3 A28 AD22 GND AD22 GND AD22 AD21 B29 A29 AD20 AD21 B29 A29 AD20 AD19 B30 AD21 AD20 A30 AD19 B30 AD21 AD20 A30 B31 AD19 GND A31 AD18 B31 AD19 GND A31 AD18 AD17 B32 +3.3V AD18 A32 AD16 AD17 B32 +3.3V AD18 A32 AD16 C_BE#2 B33 AD17 AD16 A33 C_BE#2 B33 AD17 AD16 A33 C/BE#2 +3.3V C/BE#2 +3.3V B34 A34 B34 A34 FRAME# FRAME# 13,18,32 B35 GND FRAME# A35 IRDY# B35 GND FRAME# A35 13,18,32 IRDY# B36 IRDY# GND A36 B36 IRDY# GND A36 TRDY# TRDY# 13,18,32 B37 +3.3V TRDY# A37 DEVSEL# B37 +3.3V TRDY# A37 13,18,32 DEVSEL# B38 DEVSEL# GND A38 B38 DEVSEL# GND A38 STOP# GND STOP# STOP# 13,18,32 GND STOP# 13,18,32 PLOCK# B39 A39 PLOCK# B39 A39 13,18,32 PERR# PERR# B40 LOCK# +3.3V A40 PERR# B40 LOCK# +3.3V A40 B41 PERR# SDONE A41 B41 PERR# SDONE A41 B42 +3.3V SBO# A42 SERR# B42 +3.3V SBO# A42 13,18,32 SERR# B43 SERR# GND A43 B43 SERR# GND A43 PAR +3.3V PAR PAR 13,18 +3.3V PAR C_BE#1 B44 A44 AD15 C_BE#1 B44 A44 AD15 AD14 B45 C/BE#1 AD15 A45 AD14 B45 C/BE#1 AD15 A45 AD14 +3.3V AD14 +3.3V 2 B46 A46 AD13 B46 A46 AD13 2 AD12 B47 GND AD13 A47 AD11 AD12 B47 GND AD13 A47 AD11 AD10 B48 AD12 AD11 A48 AD10 B48 AD12 AD11 A48 AD10 GND AD10 GND B49 A49 AD9 B49 A49 AD9 GND AD9 GND AD9

AD8 B52 A52 C_BE#0 AD8 B52 A52 C_BE#0 AD7 B53 AD8 C/BE#0 A53 AD7 B53 AD8 C/BE#0 A53 AD7 +3.3V AD7 +3.3V B54 A54 AD6 B54 A54 AD6 AD5 B55 +3.3V AD6 A55 AD4 AD5 B55 +3.3V AD6 A55 AD4 AD3 B56 AD5 AD4 A56 AD3 B56 AD5 AD4 A56 B57 AD3 GND A57 AD2 B57 AD3 GND A57 AD2 AD1 B58 GND AD2 A58 AD0 AD1 B58 GND AD2 A58 AD0 AD1 AD0 AD1 AD0 B59 A59 B59 A59 ACK64# B60 +5V(I/O) +5V(I/O) A60 ACK64# B60 +5V(I/O) +5V(I/O) A60 18,32 ACK64# REQ64#1 32 REQ64#2 32 B61 ACK64# REQ64# A61 B61 ACK64# REQ64# A61 B62 +5V +5V A62 B62 +5V +5V A62 +5V +5V +5V +5V

PCI_CON_32BIT PCI_CON_32BIT

AD[0..31] 13,18 AD[0..31] 1 1 C_BE#[0..3] 13,18 C_BE#[0..3] PCI 1 & 2 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 17of 34 A B C D E A B C D E

V3SB V3SB VCC3_3 VCC3_3 VCC3_3 VCC3_3

VCC5 VCC5 VCC5 VCC5

VCC12- VCC12 VCC12- VCC12

4 4 PCI3 PCI4 B1 A1 B1 A1 B2 -12V TRST# A2 B2 -12V TRST# A2 B3 TCK +12V A3 B3 TCK +12V A3 GND TMS GND TMS B4 A4 B4 A4 B5 TDO TDI A5 B5 TDO TDI A5 B6 +5V +5V A6 B6 +5V +5V A6 PIRQ#D PIRQ#C 13,17,32 B7 +5V INTA# A7 PIRQ#A B7 +5V INTA# A7 PIRQ#B 13,17,32 PIRQ#D PIRQ#A 13,17,32 B8 INTB# INTC# A8 PIRQ#C B8 INTB# INTC# A8 13,17,32 PIRQ#B INTD# +5V INTD# +5V B9 A9 B9 A9 B10 PRSNT#1 RESERVED A10 B10 PRSNT#1 RESERVED A10 B11 RESERVED +5V(I/O) A11 B11 RESERVED +5V(I/O) A11 B12 PRSNT#2 RESERVED A12 B12 PRSNT#2 RESERVED A12 B13 GND GND A13 B13 GND GND A13 GND GND GND GND B14 A14 B14 A14 B15 RESERVED RESERVED A15 B15 RESERVED RESERVED A15 PCI_RST#PCI_RST# 6 PCLK_3 B16 GND RST# A16 PCI_RST# 17,32 6 PCLK_5 B16 GND RST# A16 B17 CLK +5V(I/O) A17 B17 CLK +5V(I/O) A17 PGNT#3 PGNT#2 13 B18 GND GNT A18 B18 GND GNT A18 PGNT#3 13 13,32 PREQ#2 REQ# GND 13,32 PREQ#3 REQ# GND B19 A19 B19 A19 PCI_PME# PCI_PME# 13,17 AD31 B20 +5V(I/O) PME# A20 AD30 AD31 B20 +5V(I/O) PME# A20 AD30 AD29 B21 AD31 AD30 A21 AD29 B21 AD31 AD30 A21 AD29 +3.3V AD29 +3.3V 3 B22 A22 AD28 B22 A22 AD28 3 AD27 B23 GND AD28 A23 AD26 AD27 B23 GND AD28 A23 AD26 AD27 AD26 AD27 AD26 AD25 B24 A24 AD25 B24 A24 B25 AD25 GND A25 AD24 B25 AD25 GND A25 AD24 C_BE#3 B26 +3.3V AD24 A26 R_AD18 R133 AD18 C_BE#3 B26 +3.3V AD24 A26 R_AD18 R134 AD18 AD23 B27 C/BE#3 IDSEL A27 100 AD23 B27 C/BE#3 IDSEL A27 100 B28 AD23 +3.3 A28 AD22 B28 AD23 +3.3 A28 AD22 GND AD22 GND AD22 AD21 B29 A29 AD20 AD21 B29 A29 AD20 AD19 B30 AD21 AD20 A30 AD19 B30 AD21 AD20 A30 B31 AD19 GND A31 AD18 B31 AD19 GND A31 AD18 AD17 B32 +3.3V AD18 A32 AD16 AD17 B32 +3.3V AD18 A32 AD16 C_BE#2 B33 AD17 AD16 A33 C_BE#2 B33 AD17 AD16 A33 C/BE#2 +3.3V C/BE#2 +3.3V B34 A34 B34 A34 FRAME# FRAME# 13,17,32 B35 GND FRAME# A35 IRDY# B35 GND FRAME# A35 13,17,32 IRDY# B36 IRDY# GND A36 B36 IRDY# GND A36 TRDY# TRDY# 13,17,32 B37 +3.3V TRDY# A37 DEVSEL# B37 +3.3V TRDY# A37 13,17,32 DEVSEL# B38 DEVSEL# GND A38 B38 DEVSEL# GND A38 STOP# GND STOP# STOP# 13,17,32 GND STOP# 13,17,32 PLOCK# B39 A39 PLOCK# B39 A39 13,17,32 PERR# PERR# B40 LOCK# +3.3V A40 PERR# B40 LOCK# +3.3V A40 SMLINK0 14,32 B41 PERR# SDONE A41 B41 PERR# SDONE A41 SMLINK1 14,32 B42 +3.3V SBO# A42 SERR# B42 +3.3V SBO# A42 13,17,32 SERR# B43 SERR# GND A43 B43 SERR# GND A43 PAR +3.3V PAR PAR 13,17 +3.3V PAR C_BE#1 B44 A44 AD15 C_BE#1 B44 A44 AD15 AD14 B45 C/BE#1 AD15 A45 AD14 B45 C/BE#1 AD15 A45 AD14 +3.3V AD14 +3.3V 2 B46 A46 AD13 B46 A46 AD13 2 AD12 B47 GND AD13 A47 AD11 AD12 B47 GND AD13 A47 AD11 AD10 B48 AD12 AD11 A48 AD10 B48 AD12 AD11 A48 AD10 GND AD10 GND B49 A49 AD9 B49 A49 AD9 GND AD9 GND AD9

AD8 B52 A52 C_BE#0 AD8 B52 A52 C_BE#0 AD7 B53 AD8 C/BE#0 A53 AD7 B53 AD8 C/BE#0 A53 AD7 +3.3V AD7 +3.3V B54 A54 AD6 B54 A54 AD6 AD5 B55 +3.3V AD6 A55 AD4 AD5 B55 +3.3V AD6 A55 AD4 AD3 B56 AD5 AD4 A56 AD3 B56 AD5 AD4 A56 B57 AD3 GND A57 AD2 B57 AD3 GND A57 AD2 AD1 B58 GND AD2 A58 AD0 AD1 B58 GND AD2 A58 AD0 AD1 AD0 AD1 AD0 B59 A59 B59 A59 ACK64# B60 +5V(I/O) +5V(I/O) A60 ACK64# B60 +5V(I/O) +5V(I/O) A60 17,32 ACK64# REQ64#3 32 REQ64#4 32 B61 ACK64# REQ64# A61 B61 ACK64# REQ64# A61 B62 +5V +5V A62 B62 +5V +5V A62 +5V +5V +5V +5V

PCI_CON_32BIT PCI_CON_32BIT

1 AD[0..31] 1 13,17 AD[0..31]

C_BE#[0..3] 13,17 C_BE#[0..3] PCI 3 & 4 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 18of 34 A B C D E 8 7 6 5 4 3 2 1

D D

VCC5DUAL

F1 FUSE_1.0A

R135A 470k

C 14 USBOC#0-1 USB1 C 1 2 1 VCC0 2 FB3 BEAD 3 DATA0- DATA0+ + EC1 BC20 4 5 GND0 100UF 470PF 6 VCC1 DATA1- 1 2 7 8 DATA1+ 1 2 FB4 BEAD GND1 USB_CON2 14 USBP0N 1 2 FB5 BEAD 14 USBP0P 14 USBP1N 1 2 FB6 BEAD 14 USBP1P FB7 BEAD 2 4 6 8 1 3 5 7 2 4 6 RN6 CP1 15K/8P4R 47PF/8P4C 1 3 5 7 8 2 4 6 8

B 1 3 5 7 B

A A

USB PORT 1 & 2 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 19of 34 8 7 6 5 4 3 2 1 A

VCC3_3 VCC5 VCC5_AUDIO 1 VCC12 PFB1 U10 VCC5_AUDIO MC78M05CDT BEAD 2 1 3 VIN +5V

BC22 BC23 BC24

1 1 BC21 C198 GND C200 C197 C199 0.1UF 0.1UF 0.1UF 0.1UF

10uF 0.1uF 15V 2 10uF 0.1uF 6.3V 2 2 L8A 1 2

U11 4 1 7 9 38 42 25 26 40 44 43 NC40 NC44 NC43 AVSS2 AVSS1 DVSS1 DVSS2 AVDD2 AVDD1 DVDD1 DVDD2

MC1 1UF 12 PC_BEEP 21 LINE_IN_R 24 21 LINE_IN_L 23 LINE_IN_R 21 MIC_IN 21 LINE_IN_L 11 AC_RST# 14,32 22 MIC1 RESET# 5 AC_SDOUT 14,32 21 CD_R 20 MIC2 SDATA_OUT 8 CD_R SDATA_IN AC_SDIN0 14,32 21 CD_L 18 10 AC_SYNC 14 21 CD_REF 19 CD_L SYNC 6 AC'97 AC_BITCLK 14 17 CD_REF BIT_CLK 16 VIDEO_R CODEC 46 21 AUX_L 14 VIDEO_L CS1 45 AUX_L CS0 21 AUX_R 15 48 13 AUX_R CHAIN_CLK 47 EAPD 21 31 AC97SPKR R136 10K MC2 X1UF 37 PHONE EAPD 21 LNLVL_OUT_R 36 MONO_OUT C201 21 LNLVL_OUT_L 35 LINE_OUT_R LINE_OUT_L A 41 10PF A 39 LNLVL_OUT_R LNLVL_OUT_L

AFILT1 AFILT2 FILT_L FILT_R RX3D CX3D VREF VREFOUT XTL_OUT XTL_IN R137 CS4299

29 30 32 31 33 34 27 28 3 2 1K

R138 X0 AUD_VREFOUT 21

MC3 Y3 R139 0.1UF 1K 24.576MHZ

BC25 R140 C202 C203 MC4 MC5 MC6 MC7 MC8 MC9 C204 C205 1K 0.1UF 2700PF 2700PF 1UF 1UF 0.1UF 0.1UF 4.7UF 2.2UF 22PF 22PF

C206 0.1uF

AC'97 CODEC Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 20of 34 A 8 7 6 5 4 3 2 1

Stereo HP/Spkr out

C207 R141 FB8

+ 1 2 JK1 100UF 20 BEAD

C208 R142 FB9

+ 1 2 D D 100UF 20 BEAD MC10 R143 PHONEJACK C209 C210 20 LNLVL_OUT_L 1UF 20K 100uF 100uF C211 100PF

R144 20K

VCC5_AUDIO U12 MC11 R146 1 8 R145 OUTA VDD 2 7 20K C212 20 LNLVL_OUT_R 3 INA OUTB 6 100PF BYPASS INB 1UF 20K 4 5 GND SHUTDN LM4880

MC12 1UF BC26 C C 0.1UF 20 EAPD

Line_In Analog Input CD Analog Input MC13 FB10 CD1 R147 1 2 R148 MC14 20 LINE_IN_R 1K 1 CD_INR JK2 CD_R 20 1UF BEAD 2 3 CD_ING 1K 1UF MC15 FB11 4 CD_INL R150 MC16 R149 1 2 20 LINE_IN_L CD_L 20 1K 2.54_WAFER_4 1K 1UF BEAD 1UF C213 C214 PHONEJACK R151 MC17 CD_REF 20 100PF 100PF 1K 1UF B CD2 B 1 R152 C215 R153 C216 R154 C217 2 220K 220K 220K 3 100PF 100PF 100PF 4

2mm_WAFER_4

R155 Microphone Input JK3 AUX1 MC18 20 AUD_VREFOUT 1 AUX_INL 2.2K AUX_L 20 2 3 MC19 R156 FB12 1UF MC20 1 2 4 AUX_INR 20 MIC_IN AUX_R 20 1K 1UF BEAD 2.54_WAFER_4 1UF C219 PHONEJACK C220 C221 C218 0.01UF 100PF 100PF 100PF

A A "SINGLE POINT CONNECTION" AUDIO I/O Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 21of 34 8 7 6 5 4 3 2 1 A B C D E COM1 VCC12- VCC12 VCC5 COM1 DCD0 1 DSR0 6 RXDD0 2 D4 D5 RTS0 7 U13 TXDD0 3 SS12/SMD SS12/SMD CTS0 8 10 1 DTR0 4 4 -12V 12V 4 11 20 RI0 9 GND 5V 5 12 9 DCD0 BC27 16 DCD#0 13 RY5 RA5 8 DTR0 .1U 16 DTR#0 14 DA3 DY3 7 CTS0 2 4 6 8 2 4 6 8 CONNECTOR_DB9 16 CTS#0 RY4 RA4 15 6 TXDD0 CN1 2 4 6 2 4 6 CN2 16 TXD0 16 DA2 DY2 5 RTS0 16 RTS#0 17 DA1 DY1 4 RXDD0 16 RXD0 18 RY3 RA3 3 DSR0 100PF/8P4C 100PF/8P4C 16 DSR#0 19 RY2 RA2 2 RI0 1 3 5 71 8 3 5 7 8 16 RI#0 RY1 RA1

GD75232 1 3 5 7 1 3 5 7 COM2 CTS1 DSR1 U14 DTR1 RXDD1 10 1 COM2 11 -12V 12V 20 DCD1 GND 5V TXDD1 1 2 3 4 3 12 9 DCD1 BC28 3 16 DCD#1 13 RY5 RA5 8 DTR1 .1U RTS1 5 6 16 DTR#1 DA3 DY3 7 8 14 7 CTS1 RI1 16 CTS#1 15 RY4 RA4 6 TXDD1 9 10 16 TXD1 DA2 DY2 16 5 RTS1 HEADER_5X2 16 RTS#1 17 DA1 DY1 4 RXDD1 16 RXD1 18 RY3 RA3 3 DSR1 2 4 6 8 2 4 6 8 16 DSR#1 RY2 RA2

19 2 RI1 2 4 6 2 4 6 CN4 16 RI#1 RY1 RA1 CN3 GD75232 100PF/8P4C 100PF/8P4C 1 3 5 71 8 3 5 7 8 1 3 5 7 1 3 5 7 16 AFD# Parallel Port

16 ERR# VCC5 D6

U15 SS12/SMD 16 PAR_INIT# 1 28 P1 P8 BC29 2 16 SLIN# 2 27 .1U 2 P2 P7 LPT1 16 STB# 3 26 1 SI1 SO1 14 16 PDR0 4 25 2 SI2 SO2 15 16 PDR1 5 24 3 SI3 SO3 16 16 PDR2 6 23 4 SI4 SO4 17 16 PDR3 7 22 5 SI5 GND 18 16 SLCT 8 21 6 P3 SO5 19 16 PDR4 9 20 7 SI6 VCC 20 16 PE 10 19 8 P4 SO6 21 16 PDR5 11 18 9 SI7 SO7 22 16 BUSY 12 17 10 P5 SO8 23 16 PDR6 13 16 11 SI8 SO9 24 1 16 PDR7 14 15 12 1 SI9 P6 25 13 SERIAL AND PARALLEL PORT PAC-S1284 16 ACK# LPT Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 22of 34 A B C D E A B C D E

VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 R157 0

F2 XFUSE_1.0A 2 FB13 BEAD R158 R159 R160 R161 R162 R163 C222 4 4

4.7K 4.7K 4.7K 4.7K 1 4.7K 4.7K 470PF J4 1 RN7 1K/8P4R 9 8 7 J1BUT1 2 16 J1BUTTON1 6 5 J2BUT1 10 16 J2BUTTON1 4 3 JOY_1X 3 16 JOY1X 2 1 JOY_2X 11 16 JOY2X 4 R164 47 MIDI_OUTPUT 12 16 MIDI_OUT RN8 1K/8P4R 5 8 7 JOY_2Y 13 16 JOY2Y 6 5 JOY_1Y 6 16 JOY1Y 4 3 J2BUT2 14 16 J2BUTTON2 2 1 J1BUT2 7 16 J1BUTTON2 R165 47 MIDI_INPUT 15 16 MIDI_IN 8

C223 C224 GAME_PORT 8 6 4 2 8 6 4 2 1000PF 22PF C225 6 4 2 6 4 2 3 C226 C227 C228 C229 CN5 CN6 3 1000PF 22PF 470PF 470PF 470PF C230 C231 470PF/8P4C 75 3 1 8 75 3 1 8 470PF/8P4C 22PF 1000PF

7 5 3 1 7 5 3 1 Game Port C232 C233 22PF 1000PF

VCC5DUAL R166 0 FB14 F3 XFUSE_1.0A 1 2

BEAD R167 0

F4 XFUSE_1.0A FB15 U16 1 2 16 KDAT 1 2 BEAD 3 2 FB16 2 1 2 4 16 KCLK 5 6 BEAD RN9 4.7K/8P4R 8 7 13 14 6 5 FB17 4 3 1 2 15 2 1 16 BEAD 17 FB18 1 2 16 MDAT 7 8 BEAD 9 FB19 1 2 10 16 MCLK 11 12 BEAD KB/MOUSE IR1 CN7 VCC5 1 8 7 78 2 6 5 C234 C235 3 4 6 5 3 16 IRRX 4 3 4 2 1 2.2UF 2.2UF Keyboard 1 5 2 1 1 16 IRTX 470PF8P4C HEADER_1X5 Mouse KEYBOARD, MOUSE, GAME & IR Title IR Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 23of 34 A B C D E A

Digital Video Out

VCC3_3 VCC3_3

L9A L10A 2 1 FPP1V3 2 1 A A A A A 3 C236 + C237 C240A C241A C238 C242 C239 1 1 + FPDV F 2 VCC3_3 2 10UF 10UF 100PF 100PF 100PF 100PF 100P

L11A

2 1 FPAV3 VCC1_8 A C243 C245A 1 + C244A 2

R168A 100PF 100PF 10UF 1K R169A 400 1% FTVREF

Place C106A U17A 3 29 23 49 18 33 12 1 near U8A pin 3 C246A 1

R170A + TRS_PU C247A VREF VCC2 VCC1 VCC0 PVCC1 PVCC0 36 AVCC1 AVCC0

1K D23 EX 2 100pF 37 21

0.01UF D22 TXC- TXC- 25 38 22 D21 TXC+ TXC+ 25 39 D20 40 D19 41 24 D18 TX0- TX0- 25 42 25 D17 TX0+ TX0+ 25 43 A D16/PFEN DFP A 44 D15 45 27 D14 Flat Panel TX1- TX1- 25 46 28 D13 Transmitter TX1+ TX1+ 25 47 D12 9 FTD[11:0] 50 FTD11 D11 FTD10 51 30 D10 TX2- TX2- 25 FTD9 52 31 D9 TX2+ TX2+ 25 53 FTD8 D8 54 19 FTD7 D7 EXT_RS 55 FTD6 D6 FTD5 58 35 D5 DKEN PCIRST# 7,15,16,32 59 34 FTD4 D4 TEST TEST_PD FTD3 60 15 D3 BSEL/SCL 3VFTSCL 9,25 61 14

FTD2 3 D2 DSEL/SDA 3VFTSDA 9,25 62 13 FTD1 D1 ISEL/RST

FTD0 63 11 FPDV D0 MSEN SL_STALL9 10 PD 56 9 IDCLK- EDGE/CHG 9 FTCLK0 3VHTPLG 25 R171A 57 9 FTCLK1 IDCLK+ 8 CTL1/A1/DK1 A1_PD 2 DE FTBLNK#9 7 A2_PD 1K 4 CTL2/A2/DK2 HS R172A 9 FTHSYNC 6 A3_PD 5 CTL3/A3/DK3 9 FTVSYNC VS 1K R174A R173A

AGND2 AGND1 AGND0 PGND GND2 GND1 GND0 4.7K 1K 32 26 20 17 64 48 16

Do Not Stuff

DIGITAL VIDEO OUT Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 24of 34 A A

Video Connectors

20 Pin Flat Panel Connector VGA Connector VCC5 VCC1_8

CR1A 2

2 F5A

BLM11B750S is rated at 2.5A VCC5 1 3 70Ohms at 100MHz

VCC5 1 BAT54S L12A R176A R175A CR 1 2 1K 1K 9 VID_RED T5V_F J5A C BLM11B750S

CR2A 8A 9A - Place R66A,R67A,&

1 11 C24 C24 TX2+ 24 1N5821 R69A Close to VGA 24 TX1+ + Protection Circuit R177A

2 12 Connector F A 75 2 24 TX1- TX2- 24 for 20V Tolerance PF 3 13 1% 3.3P 3.3 L13A 4 14 VCC1_8 J6A

5 15 CR3A 24 TXC + TX0+ 24 6 16 6 24 TXC - TX0- 24 2 1 6 7 17 R178A L_RED 1 1 11 1 3 8 18 CON_HTPLG 5VHTPLG MONOPU 11 1 1A 9 19 R179 2.2K BAT54S 7 L14A C25 + C250A 10 20 1 1 2 L_GREEN 2 30k D e-Bounce 9 VID_GREEN

Circuit F

2 12

BLM11B750S 3A 2A 2 10UF 8 0.01U C25 C25 R180A L_BLUE 3 A F PF SCL 75 L_HSYNC 13 1% 3.3P 3.3 FUSE_5 9 CON_FT CON_FTSD R181A MON2PU 4 5VFTSDA 0K L_VSYNC 14 R182A 10 5VFTSCL 5VDDCDA 10 0K 5 15 R183A 5 Populate if DFP Devi ce 5VHSYNC 15

A is also populated. A A

VCC5 0K 55A C254 C2 CR4A F PF 2

5V to 3.3V Translation / Isolation 3.3 VCC5 3.3P CR5A 1 3 Do Not Stuff C114A and C115A QS4_3V C A BAT54S A 5VDDCCL 8 7 6 5 C256 RP1A R184A R185A 4.7K 5VVSYNC UF

VCC5 7A 0K 0.1 58A

2.2K C25 C2

U18A 1 2 3 4 CR6A A A F F 62A QST3384 2 61A 3.3P C2 3.3P C260 C2 24 C259 VCC 3 2 5VDDCDA 1 3 9 3VDDCDA 1A1 1B1 F PF 4 5 5VDDCCL PF PF 10P 10 9 3VDDCCL 1A2 1B2 BAT54S Do Not Stuff C117A and C118A 10 10 7 6 5VHSYNC 9 CRT_HSYNC 1A3 1B3 8 9 5VVSYNC L15A 9 CRT_VSYNC 1B41A4 1 2 11 10 5VHTPLG 9 VID_BLUE 24 3VHTPLG 1B51A5

A BLM11B750S 14 15 5VFTSDA 9,24 3VFTSDA 2A1 2B1 64A VCC1_8 C2 17 16 C263 2A2 5VFTSCL R186A 9,24 3VFTSCL 2B2 R187A CR7A F 18 19 QSSDA 75 F 6 CK_SMBDATA 2A3 2B3 SMBDATA 11,12,14,16,31,32 R188A 0K 1% 2

21 20 QSSCL 3.3P 2A4 2B4 SMBCLK 11,12,14,16,31,32 3.3P 6 CK_SMBCLK 0K 22 23 2A5 2B5 1 3 1 12 BEA# GND BAT54S 13 BEB#

R189A

2.2K R190A

2.2K Do Not Populate VIDEO CONNECTORS Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 25of 34 A 8 7 6 5 4 3 2 1

V3SB

V3SB U19 8 BLM11B750S1A 1

14 EE_CS VCC 1 2 2 EECS 6 D 14 EE_SHCLK EESK NC D 3 7 14 EE_DIN 4 EEDI NC 14 EE_DOUT C265 C266 EEDO GND 4.7uF 4.7uF 93C46

5 V3SB RP2 U20 1 25 40 36 2 7 9 12 14 17 19 23 1 2 13 LAN_CLK 3 4 VCC 13 LAN_RSTSYNC VCC Place decoupling capacitors near 5 6 39 10 TDP C267 C268 C269 VCCP VCCT VCCP VCCA VCCT VCCT VCCT VCCR 13 LAN_TXD2 VCCR JCLK VCCA2 TDP 7 8 11 TDN 0.1uF 0.1uF 0.1uF 82562ET 13 LAN_TXD1 45 JRSTSYNC TDN RP3 0 44 JTXD2 15 RDP 1 2 43 JTXD1 RDP 16 RDN 13 LAN_TXD0 3 4 37 JTXD0 RDN V3SB 13 LAN_RXD2 JRXD2 5 6 35 5 13 LAN_RXD1 7 8 34 JRXD1 RBIAS100 4 13 LAN_RXD0 JRXD0 RBIAS10 0 41 32 ACTLED C270 C271 C272 C273 C274 C275 30 ADV10 ACTLED 31 SPEEDLED R191 R192 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF ISOL_TCK SPDLED 28 27 LILED 619, 1% 549, 1% 29 ISOL_TI LILED 26 ISOL_EX 47 TOUT X2 C 21 46 C TESTEN X1 V3SB R193 R194 VSSP VSS VSS VSS VSS VSSP VSSA VSSR 10K 0 VSS VSSA2 VSSR 82562ET

8 13 18 24 48 33 38 3 6 22 20 Y4 + C276 + C277 + C278 4.7uF 4.7uF 4.7uF 25MHz

C279 C280

22pF 22pF

V3SB

R195 B R196 330 B ACTLED TDP Place close to 82562ET 330 R197 U21 J7 RJ45 100, 1% 1 FRE D7 D8 TD+ TX+ 2 C1 E5608-0E0045 TDN TDC CMT 3 C2 GREEN AMBER TD- TX- C3 RDP 4 NC NC 5 C4 LILED R198 NC NC 6 C5 100, 1% RD+ RX+ 7 C6 RDC RXC 8 C7

RDN RD- RX- C8 SH_0 SH_1 H1102 11 12 SPEEDLED

C281 0.1uF R199 R200 R201 R202 75, 1% 75, 1% 75, 1% 75, 1%

C282 A A

1000pF, 2KV LAN ON MOTHERBOARD Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 26of 34 8 7 6 5 4 3 2 1 A B C D E

VCC3_3 VCC5SBY VCC5 V3SB ATXPR1 11 1 VCC12- 12 3.3V 3.3V 2 BC30 D9 13 -12V 3.3V 3 .1U 1N4148 R203 GND GND 14 4 VCC5SBY 15K R204 16 PS_ON 15 PS_ON +5V 5 V3SB 16 GND GND 6 U23A 14 U22A 4.7K 17 GND +5V 7 14 VCC_5- 18 GND GND 8 ATXPWROK 1 2 1 2 4 -5V PWROK 4 19 9 VCC5 20 +5V AUX5V 10 VCC5SBY 74LVC14A C283 R205 +5V +12V VCC12

7 74LVC06A 33K

ATX_PWCON 7 2UF VCC5SBY

VCC5SBY

U23B U22B

R206 100 3 4 3 4 14 31 HWRST# U24A VCC5SBY 74LVC14A 74LS132

V3SB V3SB 74LVC06A VCC U22C 1 A 3 5 6 PWROK 14,16 2 Y R207 BC31 VCC5SBY C284 B 1K .1U 74LVC06A U23C U22D 1.0uF

5 6 9 8 4 DBRESET#

3 74LVC14A 3 74LVC06A VCC5

R208A

22 C285 1 C286 0.01uF 10uF SW1

2 1 2

Reset button

JP8 Resume Reset Circuitry. Place JP near front panel hdr 22msec delay

V3SB V3SB V3SB 2 2

U25A 14 U26A R209A 1 2 1 2 RSMRST# 14,16

74LVC14A 74LVC14A 22k 7

BC32

1.0uF R210ADo not stuff. For debug only 1M

1 1

ATX POWER Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 27of 34 A B C D E A B C D E

4 4

VCC12 VCC5 JP9 R211

4.7K TEMPERATURE SENSING 1 2 HEADER_2 Q1 CHASSIS FAN R212 1K 2N2907 D10 R213 +12CHFAN 1K 1N4148 16 VTIN3 FAN1 Q2 EC2 + 3 FANIO1 16 PR2 RT1 t 2N7002 2 16 FANPWM1 22UF 1 16 HM_VREF 3 R214 510 10K,1% X10K_1%-THRM/0603 3 HEADER_3 16 VTIN1 "system use" R215 PR3 RT2 t VCC12 VCC5 4,16 VTIN2 30K 10K,1% R216 C287 10K_1%-THRM/0603 4.7K "power use" Q3 CPU FAN 3300PF R217 1K 2N2907 D11 R218 +12CPUFAN 4,16 THRMDN 1N4148 1K PR4 PR5 Q4 FAN2 VCC12 EC3 3 VOLTAGE SENSING + FANIO2 16 28K,1% 10K,1% 2N7002 2 16 FANPWM2 22UF 1 R219 510 +12VIN 16 HEADER_3 VCC_CORE R220 VCORE 16 10K VCC12 VCC5 VCCT1_5 R221 VTT 16 VCCRTC R222 10M 10K R223 2 14,16 CASEOPEN# PWR FAN VCC3_3 2 EC4 +3.3VIN 16 + D12 R224 10K If case is opened, 22UF PR6 PR7 this switch should be closed. 1N4148 1K VCC12- S1 FAN3 56K,1% 232K,1% 3 FANIO3 16 -12VIN 16 HEADER_2PIN 2 1 -5VIN 16 PR8 PR9 HEADER_3 VCC_5- 56K,1% 120K,1%

1 1

HARDWARE MONITOR Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 28of 34 A B C D E A B C D E

VCC12 VCC5 Dip Switch L16 1.7uH 1.35V 1.25V 1.10V Pin # (Default) 1 : open

1-12 1 0 1 1 0 0 : close (GND) C288 C290 C291 C292 C293 C295 C296 4 0.1uF C289 4.7uF 4.7uF 4.7uF 3300uF C294 0.1uF 10uF 4 0 2-11 1 0 0.1uF 3300uF 3-10 1 0 1 2 2

4-9 0 0 1 R225 2 1 5-8 0 0 0

4m U27

1 20 VID3 GND 2 19 Stuff only one VID2 PGND R226 2.2 Q5 R227 3 18 2 1 MOSFET N VID1 DRVH 1 2 4 17 2 1 VID0 DRVL 3m 5 16 R228 2.2 VCC_CORE VID25 VCC L17 1uH R229 6 15 1 2 PWRGD LRFB 7 14 3m 3 REF LRDRV 3 12 11 10 9 8 7 8 13 MOSFET N EC5 + EC6 + EC7 + EC8 + EC9 + EC10+ EC11 + SW2 SD COMP Q6 2 2 9 12 R230 R232 2 820uF 820uF 820uF 820uF 1000uF 1000uF 1000uF DIP switch 6 position FB CT C297 10V 10V 10V 10V 10V 10V 10V R231 10 11 220 220 CS- CS+ 1 2 3 4 5 6 11.2k C298 180nF

6.3V 1

1 0.1uF C299 1 6.3V ADP3170 0.001uF 6.3V

EC12 + EC13 + EC14 + EC15 +

2 1000uF 1000uF 1000uF 1000uF 2 2 2 2 2 R233 10V 10V 10V 10V R234 R235 R236 R237 R238 C300 C301 C302 100 100 100 100 100. 56k 2.2nF 0.1uF 10uF 1

1 1 1 1 1 Not Pop

2 2 VCC5 14 VRM_PWRGD

Q7 VCCT1_5 3 2

VIN ADJ VOUT VCC_CLK_2_5 6 Q8 LM1117ADJ

VCC3_3 + C303 1 + C304 3 2 PR10

VIN ADJ VOUT 10uF 10uF LT1587-ADJ 100,1% 1

+ C305 R239 + C306

10uF 49.9 1% 10uF PR11

100,1%

1 1 R240 10 1% VOLTAGE REGULATOR PART 1 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 29of 34 A B C D E A B C D E

VCC5SBY VCC12 VCC3_3 VCC5 VCC2_5 Q9

3 2

EC16 EC17 EC18 VIN ADJ VOUT C307 + + + LM1117ADJ 4 100uF 10uF 100uF 4 0.1uF 1 + EC19 PR12 + EC20

1 14 U28 10uF 100,1% 100uF

Q10 12V

Q11 5VSB 15 3 DRV2 HUF76121D3S/TO252 NZT651/SOT223 3V3DLSB PR13 16 VSEN2 VCC3_3SBY 4 100,1% V3SB 9 3V3DL VCC5SBY EC21 FAULT/MSET C308 EC22 + + C309 R241 1uF 1500uF 10uF 1uF 10K EC23 + 11 5VDLSB Q12 100uF 6 NDS356AP/SOT23 6,14,16 SLP_S3# S3 7 V3SB V1_8SB 14 SLP_S5# 5 S5 12 Q13 VCC5SBY 2 EN5VDL 5VDL VCC5DUAL EN3VDL 3 13 10 3 2 3 SS GND DLA C310 VIN ADJ VOUT C311 HIP6501 LM1117ADJ

8 1uF + EC24 1 + EC25 0.1uF PR14 10uF 10uF 120,1%

Q14 PR15

4 5 60,1% G2 D2 VCC3_3 3 6 S2 D2

2 7 G1 D1 VCC5 1 8 S1 D1

VCC3_3 VCC1_8 Q15 2 FDS8936 / SI9936 2 EC26 EC27 + + 3 2

100uF 100uF VIN ADJ VOUT LM1117ADJ

+ EC28 1 + EC29 PR16 10uF 10uF 120,1%

PR17

60,1%

1 1

VOLTAGE REGULATOR PART 2 Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 30of 34 A B C D E A B C D E

V3SB VCC5SBY VCC5

4 4

VCC5 VCC5SBY VCC5 R242 R243 R244 R245 R246 10K 220 10K 150 220

R247 10K R248 R249 PN1 10K 150 1 PN2 2 1 3 27 HWRST# RESET KEYLOCK 2 16 KEYLOCK# 4 3 13 EXTSMI# 5 4 6 5 7 SPEAKER HDD LED 6 8 7 9 8 10 PWR_SW 9 16 PANSWIN 11 GREEN LED 10 R250 BC33 12 11 13 10K R251 SMI_SW 12 14 16 SUSLED Q16 R252 RESERVE 0.1uF 0 3 13 3 2N3904 C312 HEADER_14 0 14 HEADER_14 0.1uF VCC5 VCC5 SP1 D13 1N4148 R253 15 IDEACTP# R254 33 10K R255 68 BUZZER D14 1N4148 15 IDEACTS# 16 BEEP Q17 R256 68 2N3904

JP10 14,32 ICH_SPKR R257 2.2K Q18 1 2 2N3904 BC34 3 4 0.1uF XHEADER 2X2 VCC5 VCC5 R258 0 20 AC97SPKR JP8 TRADITIONAL PC SOUND 11,12,14,16,25,32 SMBCLK 2 1-2 ON ON BOARD BUZZ OR DIRECT TO SPKR 2 3-4 ON MIXED IN ON_BOARD AC97 CODEC 11,12,14,16,25,32 SMBDATA

SMB1 SMB2 1 1 2 2 3 3 4 4 5 5

SMBCON SMBCON

D15 VCC5SBY R259 330

LED

1 1

FRONT PANEL AND SMBUS Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 31of 34 A B C D E A B C D E

PCI VCC5 ICH V3SB VCC3_3 VCC3_3 VCC5 RP4 RN10 13,17,18 PERR# 1 5 14 SMBALERT# 1 2 13,17,18 SERR# 2 R1 C 3 4 13,17,18 PLOCK# 3 R2 11,12,14,16,25,31 SMBCLK 5 6 BC35 R260 13,17,18 STOP# 4 R3 10 11,12,14,16,25,31 SMBDATA 7 8 .1U 1K

R4 C 14 13,17,18 DEVSEL# 6 R5 13,17,18 TRDY# 7 4.7K/8P4R V3SB U29A 13,17,18 IRDY# 8 R6 1 2 RN11 IDERST# 15 13,17,18 FRAME# 9 R7 13,16 LPC_PME# 1 2 R8 3 4 74LVC07A 4 2.7K/10P8R 14,18 SMLINK0 5 6 4

RN12 14,18 SMLINK1 7 8 7 1 2 13,18 PREQ#2 3 4 4.7K/8P4R V3SB VCC3_3 13,17 PREQ#1 5 6 RN13 VCC3_3 13,17 PREQ#0 7 8 1 2 13 GPI8 3 4 14 GPIO25 5 6 R261 2.7K/8P4R 13 GPIO27 RN14 7 8 1K 13 GPIO28 14 1 2 13,18 PREQ#3 3 4 8.2K/8P4R VCC3_3 U29B 13 PREQ#5 5 6 3 4 RN15 PCI_RST# 17,18 13 PREQ#4 7 8 13 PCI_REQ#A 1 2 17,18 ACK64# 14,16 OVT# 3 4 74LVC07A 2.7K/8P4R 13,16 KBRST# 5 6

RN16 13,16 A20GATE 7 8 7 1 2 17 REQ64#1 3 4 8.2K/8P4R VCC3_3 VCC3_3 VCC3_3 17 REQ64#2 5 6 VCC3_3 VCC3_3 18 REQ64#3 7 8 13,16 SERIRQ R262 8.2K 18 REQ64#4 2.7K/8P4R Do not populate R263 R264 14,20 AC_SDIN0 R265 10K 1K 1K 14 14 3 3 14 AC_SDIN1 R266 10K U29C U29D VCC3_3 13 ICHRST# 5 6 9 8 PCIRST# 7,15,16,24 14,20 AC_RST# R267 1.8K 74LVC07A 74LVC07A

JP11 V3SB 7 7 14,20 AC_SDOUT R268 8.2K

JP12 14 ICH_RI# R269 8.2K 14,31 ICH_SPKR R270 2.7K

VCC3_3 RN17 13,17,18 PIRQ#A 1 2 U23D 13,17,18 PIRQ#B 3 4 VCC5SBY VCC3_3 13,17,18 PIRQ#C 5 6 9 8 13,17,18 PIRQ#D 7 8 74LVC14A 8.2k RN18 U22E 14 13 PIRQ#E 1 2 U29E U23E 13 PIRQ#F 3 4 11 10 11 10 11 10 2 13 PIRQ#G 5 6 2 13 PIRQ#H 7 8 74LVC07A 74LVC14A 74LVC06A

8.2k 7

VCC5SBY VCC3_3

U22F 14

13 12 U29F 13 12

74LVC06A 74LVC07A

JP1 7 OFF : Normal CPU freq strap (default) ON : Force CPU freq strap safe mode

JP5 1 OFF : Reboot on TCO timer timeout (default) 1 ON: No reboot on TCO timer timeout

PULL-UP RESISTORS Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 32of 34 A B C D E A UNUSED GATES

V3SB V3SB VCC3_3 V3SB

U31A 14 14 1 U30A U26B 3 14 VCC 14 2 3 4 SN74LVC08A

1 2 7 U32A A O VCC 74LVC14A 7 1 2 SN74LVC06A U31B

A O 14 U26C GND 14 4 6 5 6 5 7 GND SN74LVC07A SN74LVC08A 7 7 74LVC14A 14 7

U30B VCC5SBY VCC 14 V3SB 3 4

U32B A O 14 VCC U34A 14 U33A 3 4 SN74LVC06A A O VCC 1 GND 1 2 A 3 A Y A 2

SN74LVC07A 7 B GND 74LS132 7 GND 7 SN74LVC07A 7 14 U34B 14 14

VCC U30C U32C 3 4 VCC 14 5 6 A O U33B 5 6 A O SN74LVC07A 7 VCC SN74LVC06A 4 A 6 SN74LVC07A U34C Y

GND 14 5 GND B 74LS132 7 7 5 6 GND

SN74LVC07A 7 7

UNUSED GATES Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 33of 34 A A B C D E

VCC12 " ATX POWER " VCC12- " ATX POWER " VCC3_3 " ATX POWER "VCC5 " ATX POWER "VCC_5- " ATX POWER "

EC30 BC36 BC37 BC38 BC39 EC31 BC40 BC41 BC42 BC43 EC32 BC44 BC45 EC33 BC46 BC47 EC34 BC48 BC49 22UF 0.1UF 0.1UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF

4 4

VCCVID VCC3_3 " Display Cache : Near the Power Pins "

MC21 MC22 MC23 MC24 MC25 MC26 MC27 MC28 MC29 MC30 MC31 MC32 MC33 MC34 MC35 MC36 BC50 BC51 BC52 BC53 BC54 BC55 BC56 BC57

4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

VCC3_3SBY " DIMM0 : Near Power Pins " VCC3_3SBY " DIMM1 : Near Power Pins "

MC37 MC38 MC39 MC40 BC58 BC59 BC60 BC61 BC62 BC63 MC41 MC42 MC43 MC44 BC64 BC65 BC66 BC67 BC68 BC69

4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

3 3 VCC1_8 " GMCH : 0.1U//0.01U at each conner and each side-center "

MC45 MC46 BC70 BC71 BC72 BC73 BC74 BC75 BC76 BC77 BC78 BC79 BC80 BC81 BC82 BC83 BC84 BC85

4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

VCC3_3SBY " GMCH : Near System Mem Quadrant " VCC3_3 " GMCH : Near Display Cache Quadrant " " Within 70 mils of GMCH "

BC86 BC87 BC88 BC89 BC90 BC91 BC92 BC93 BC94 BC95 BC96 BC97 BC98 BC99 BC100

0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

VCC3_3 " ICH2 : 0.1U//0.01U at each conner V3SB " ICH2 : Near Power Pins VCC1_8 " ICH2 : Near Power Pins V1_8SB " ICH2 : Near Power Pins 2 " " " " 2

MC47 MC48 BC101 BC102 BC103 BC104 BC105 BC106 BC107 BC108 MC49 MC50 BC109 BC110 BC111 BC112 BC113 BC114 BC115 BC116 BC117 BC118 BC119 BC120

2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

VCC3_3 " misc. "

BC121 BC122 BC123 BC124 BC125 BC126 BC127 BC128 BC129 BC130 BC131 BC132 BC133 BC134 BC135 BC136 BC137 BC138 BC139 BC140

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

H1 HOLE A H2 HOLE A H3 HOLE A H4 HOLE A H5 HOLE A H6 HOLE A 1 8 1 8 1 8 1 8 1 8 1 8 1 2 7 2 7 2 7 2 7 2 7 2 7 1 3 6 3 6 3 6 3 6 3 6 3 6 4 5 4 5 4 5 4 5 4 5 4 5 DECOUPLING CAPACITORS Title Low Power Intel® Celeron®/Pemtium® III with 815E

Size Document Number Rev 0.5

Date: Wednesday, March 27, 2002 Sheet 34of 34 A B C D E Reference Schematic

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66 Intel® Pentium® III and Intel Celeron® – Low Power/Ultra Low Power / 815E Design Guide