June 18, 2001 An Advertising Supplement to EE Times EDAC Message Ray Bingham, May 2001
From cell phones to pacemakers to MP3 players, we make them possible. We’re the people who develop the design technologies and tools essential to design nearly every electronic device, instrument, or system. This thought, from EDAC’s new ad campaign, depicts the one constant in our industry that has proven to be absolutely steadfast: companies that fail to continually innovate ulti- mately fail themselves.
Over the last few months, it has become clearer that companies need to spend more money and energy on research and develop- ment than at any other time. Many customers, while announcing layoffs and spending cuts, are increasing R&D spending. Whether they design chips or pharmaceuticals or consumer products, smart companies know that R&D is the only way they can ever create a breakthrough technology, help anticipate an unmet market need well ahead of the curve, and accelerate ahead of competitors.
Despite the overall slowdown in the economy and weaker growth in the semiconductor market, the business of the companies who populate the electronic design industry remains stronger in the face of downturns. With electronic design solutions driven by the need to design innovative, next-generation products rather than by current manufacturing volumes, spending for electronic design tracks against R&D spending.
In electronic design, our mission is to design new solutions that will enable our customers to create and commercialize next-gen- eration products quickly and reliably. This mission is important! Look around the healthcare industry and see all the devices that rely on new electronics designed using solutions from our member companies. Now think about all the lives that are saved. This is why we innovate.
Technology changes perpetually …that is the exciting/rewarding part of our business. So, our biggest challenge is staying ahead of the design and technology needs of our customers, ensuring that our products exceed customer expectations, and accelerate the empowerment of the electronics supply chain.
Ten years ago, the most complex ICs went into expensive products like mainframe computers and workstations and for devices used by the military and aerospace industry. Today, complex chips also go into millions of units of consumer products from cell phones to video games that touch our daily lives.
Demand for electronic design solutions is driven by the market demand for next-generation products, not by the manufacturing vol- ume of cell phones, for example. Thus, we must focus on innovation that helps customers get their ideas to market more quickly, efficiently and at lower costs. While competition ensures we will develop the best solutions and deliver them at a competitive price, we need to partner across the supply chain to help get products to market.
Our industry remains hard-pressed to solve all the technical challenges brought on by the deep submicron, system-on-chip era, but the pace of electronic design innovation is accelerating all the time. One only needs to look at some of the leading-edge design methodologies that are in place at the world’s top electronics companies. Approaches such as true system-level design, placement- knowledgeable synthesis, and real concurrent design (that combines hardware and software, digital and analog, chip and board) were just thoughts on a white board five years ago. Today, these methodologies are being delivered by the electronic design indus- try and are a major factor in the impressive expansion of the electronics industry. We’re seeing the convergence of computing, com- munications, and multi-media in a single product.
With product cycles as short as six months, innovation is the only way to create new value for customers and success for ourselves. I am very optimistic about the future of our industry. We participate in one of the most exciting and dynamic industrial sectors the world has ever known, and as electronics continue to proliferate into almost every aspect of our lives, there will be great opportu- nities for the people who understand how to design them. We must be very clear about what our role is: to help companies devel- op innovative products and get them to market quickly and reliably.
2 Strong Language Shapes EDA Debate On System Description and Synthesis
debate is raging within design circles, and the outcome may For example, Celoxica offers various kinds of C-language design and syn- determine the future direction of the EDA industry. In seeking thesis tools. Frontier Design markets A/RT Designer, a C-language synthe- sis tool. Co-Design Automation is leveraging Superlog, a Verilog superset, Aa solution for exploding complexity, one side has dug in behind for higher level design work. And Innoveda is taking the “scenic” road to the need for a high-level language; the other argues for keeping the famil- the world of higher abstraction, via a mixed graphical/text-based system called Visual Elite. iar VHDL or Verilog. But where the rubber meets the road, workers say, “Where is the As usual, the line separating the viewpoints is blurry: Many high-level assemblage of tools and methodologies that can replace the way I model, languages are vying for attention, with C as the leading contender, and simulate, verify, synthesize? Give me not just a new language, but a top-to- many hardware designers are not adverse to mixing VHDL or Verilog with bottom flow, an efficient method that leads to implementation. Then, per- some form of a high-level language, or perhaps updating those tried and haps I’ll listen.” true argots to include C constructs. Flows are being stretched. Notably, both Altera and Xilinx are working Why are feathers flying? Because semiconductor manufacturing tech- with Synopsys to flesh out details of a new design flow that would start nology continues to outpace design and verification technology. Not long with a C/C++ system-level description and eventually end with an FPGA ago, designers churned out an average of 500 gates each day; soon, that daily place and route tool. number will rocket to four million gates, according to conventional wisdom. Proceler, a start-up in the embedded-systems arena, is working on a As a result, designers are caught in a vise, with the jaws of productivity and compiler that will take C code and split it into reconfigurable logic and complexity inexorably closing in on each other. code for a standard processor, depending on whether a particular code Whatever the number, the pressure keeps mounting because design segment is computationally-intensive or not—no synthesis, no placement decisions are becoming even riskier and warnings of changes ahead are and routing. Want to change functionality? Just recompile. getting louder—such as Dataquest’s estimate that by 2004, the majority of Still, a vacuum exists. new electronic designs will be started using a high-level language other To get around the void, some true believers write some of their own tools than VHDL or Verilog. or models. But continue watching the shipping docks at the established EDA The only way to relax the grip, say many experienced industry hands, is vendors—Cadence, Innoveda, Mentor and Synopsys, among others—while to design and verify systems at the architectural or conceptual level and, keeping a close eye on a bunch of relative newcomers: C-Level Design, somehow, go directly to implementation. That means abandoning the com- Celoxica, CoDesign Automation, CoWare, Forte, Frontier, and others. fortable RTL design methodology—certainly, not even thinking of design- In the meantime, who holds the “right” answers? Someone once pro- ing individual gates or transistors. But most admit that some combination posed raw truth as the cure for conflict; another, Thomas Paine, in fact, said, of top-down and bottom-up design always will be necessary. “The harder the conflict, the more glorious the triumph.” Designing at a higher level of abstraction probably means relying on When it comes to system design, what is the raw truth? That is mainly time savers, such as design reuse and IP interchange, or using a proven for designers to decide, even as the language wars take on the mien of hardware platform and placing much of an application into software or religiosity and become almost as hermeneutic as the Bible. But based on firmware. To some, it could also mean going to so-called SoCs (system on the fierceness of the battle, the reward will be nothing less than survival chips) or reconfigurable processors, or combining ASICs and FPGAs, or in an increasingly brutal world market. Remember, such wars have been processors and FPGAs, or some combination of each of those. It also fought before, over models and simulators and HDLs, ad infinitum—or means simulating and verifying hardware together with software. nauseam; such is the stuff of progress. Whatever the solutions to complexity, assuredly they are not pat. Remember, when it comes to system design, even the definition of “system” A system parsed by any other method… is in dispute. Then, again, what is an SoC? It depends on who’s talking. There is agreement on one thing: System-level (SLD) and platform-based To some, a system is anything (functionality) that can be described at a design are two answers to complexity. “Certainly,” accorded Mentor’s level of abstraction above implementation. To others, it mainly means hard- Serge Leef, General Manager of the SoC Verification Div., “but SLD is a ware and software or perhaps whatever can fit on one or two chips. To still monstrously complex problem in itself.” Leef outlines two fundamental others, a system is composed of some kind of standardized hardware plat- challenges: a language suitable for describing systems at that level of form (processor, bus, operating system and compatible peripherals), with abstraction, “the lesser challenge,” and synthesis of system-level descrip- algorithmic-C functionality dropped into an embedded memory. tions, “the more profound challenge.” A few hardy individuals insist on including other critical portions in the Political and technical issues prevent the appearance of such a lan- system definition, such as analog functions, interconnections, packaging, guage, Leef believes, but he sees temporary strategies emerging, such as C power and signal integrity concerns, manufacturing and even testing. But and C++. “These are grossly inadequate,” he warns, “but if the industry high-level constructs that can describe, simulate, verify or synthesize most agrees on them and there’s enough momentum, their suitability is not rele- of these elements, or link them to high-level design, probably are years away. vant and the technical issues will be overcome.” On some level, any of these definitions can work. The real problem is, As Rami Rachamin, Director of Product Marketing, SLD Group, at whatever the definition, the system-level tools that many regard as essen- Innoveda, sees it, a C/C++ language standard will appear in the next few tial to success are not plentiful, although more are appearing almost daily. years, “because the C language has the 20-year legacy, the popularity, the
3 familiarity. But in the end, the market will drive the most powerful and rea- implementation or modeling or whatever, with no magic bullet doing sonable approach.” everything in system design. Since DAC in Los Angeles last year, many EDA, systems and semicon- Standard Verilog probably will survive, too, but “it will become the ductor companies have come out for a high-level language based on ‘assembly language’ of hardware design, used by just a few holdouts,” C/C++. Why? One argument goes like this: according to John Sanguinetti, Chief Technical Officer and Chairman of Forte The emergence of SoCs (whatever they are) has created challenges at Design Automation (recently formed from the merger of CynApps and all levels of the design process. At the systems level, engineers are recon- Chronology). Forte is the provider of the Cynlib C++ class library. “When sidering how designs are specified, partitioned and verified. Today, with Fortran first appeared,” Sanguinetti reminds, “assembly language was the systems and software engineers programming in C/C++, and their hard- standard, but it was eventually replaced by higher-level languages.” ware counterparts working in hardware description languages, such as Gary Smith, Chief EDA analyst at Dataquest, has thought about languages VHDL and Verilog, a communications gap exists among different members and offers his analysis: “It appears we will need a different language for ES of the same team. (electronic system) Level Design. One of the promises of VHDL was that it Therefore, momentum is building behind C/C++ class libraries as a solu- could do both ESL and RTL design, but as it ended up, it was just too painful.” tion for representing functionality—software and hardware—at the systems “That doesn’t mean VHDL or Verilog will be replaced at the RT level,” level. Design complexity demands very fast executable specifications to vali- Smith cautioned. “Now that VHDL has dropped out of ESL contention, date the system concept, the argument goes, and only C/C++ delivers ade- there seems to be a shift to Verilog because of its speed and ease of quate performance. use. That will make Verilog the RTL and gate-level language of tomorrow. But without a common modeling platform, the market for system-level “We have two contenders for the ESL language, possibly three. First, design tools will fragment. Various proprietary languages and translators look at the C++ situation—one of the most talked about choices. Thanks will compete for attention, dramatically slowing technological innovation to heavy marketing by its proponents, most engineers today say SystemC and economic progress. is the emerging standard Systems houses and for ESL design. But most semiconductor manufac- state {S0, S1, S2} cstate; // state variable with enumeration also say it will take two turers have a substantial to six years to develop a interest in seeing that always @(posedge reset) fully working ESL lan- transition (cstate) default: ->> S0; endtransition market evolve. They want guage. to create and support a always @(posedge clk iff !reset) “Keep in mind that single system-level model transition (cstate) the C++ Class Libraries of intellectual property S0:if (inp == 0) ->>S2; // change state define the language S2:if (inp == 1) ->> S1; else ->> S0; cores and exchange those S1: ->> S0 n = treeFind(“shergar”, root); semantics. The first models with customers. endtransition SystemC Class Library They also want to be able turned out to be an RTL to buy the commercial typedef struct {string s; ref node left, right;} node; Class Library, so until the tools they need instead of ref node n, root; // global data - pointers to nodes SystemC 2.0 spec was continuing to divert int visited = 0; // global data - number of nodes visited released, there was no resources to create and ESL version; however, support their own internal function ref node treeFind(string str, ref node parent); the release specifies a if (parent == null) return null; tools. But when they look visited++; modeling/simulation into the market, all they if (str == parent->s) return parent; // string compare class library. The growing see is chaos, as various if (str < parent->s) return treeFind(str, parent->left); demand is for a test- would-be solutions pro- else return treeFind(str, parent->right); // recursion bench class library, and, endfunction viders look for ways to of course, the holy grail is lure customers into their Figure 1: Superlog Meets C: The Superlog language is based on Verilog but adds additional a synthesis class library. proprietary formats. systems and C-like constructs, sort of a Verilog++. The fragment demonstrates some of the “These three class For the systems hous- important constructs (courtesy of Co-Design Automation). libraries easily can be es and semiconductor completely semantically manufacturers, the stakes are far too high to get locked into a dead-end different from one other, which has started a call for an API Class path—no matter how promising the solution may seem today. So they wait. Library. You can see where this is going, and why no one expects to be So long as there’s chaos and uncertainty, companies cannot afford the risks doing a complete design using SystemC in the near future.” of making the wrong move. Consequently, a healthy market cannot begin to Smith sees a number of problems that need to be sorted out. “One develop—unless… C++ language that can help a lot,” he suggests, “is SpecC, from C Level Design. They’ve been at it the longest and have a synthesis class library, so Enter C/C++—and others there’s a lot of pressure on the folks there to join the SystemC effort and …unless a “unified” approach appears. The main contenders for unifica- help sort out the class library mess.” tion appear to be SystemC, Cynlib and SuperLog, although there is an (Just after the Smith interview last March, C Level announced it was almost maddening array of others. One count finds at least seven differ- joining both the Open SystemC Initiative (OSCI) and the SpecC ent versions of C/C++-based HDLs—and bear in mind the Rosetta mod- Technology Open Consortium (STOC). C Level also said it would place its eling language, Java (which the university community insists is the right CycleC Modeling and Methodology into the public domain by donating its solution), SpecC, Specman, Rave, Ptolemy II, MoML, UML, SDL, SLDL, technology to OCSI and Accellera.) Esterel, Vera, E, Behavioral VHDL and still others. The maneuvering, according to Smith, leaves the door open for Some languages compete, others are intended for different jobs. Superlog, a superset of Verilog. The question Smith poses is whether Chances are, each survivor will find its niche—for conceptualization or Superlog can provide enough performance for it to jump into the ESL lan-
4 guage vacuum. “We’ll have to wait and see,” he Open SystemC Initiative, which now envelopes once, and library development work is finished. reflected. “It certainly is a possibility, especial- about 25 companies offering as many products. For EDA vendors, proponents say, SystemC ly if the SystemC efforts start stretching out.” The OSCI is based on an open community will create a large and stable market and elimi- (At the Design Automation and Test in licensing model, that is, the underlying source nate proprietary design languages which limit Europe conference last March, Co-Design code that forms the platform of SystemC is innovation, foster small and fragmented niche Automation said it would allow the synthesis available free to the community at large, similar markets, lengthen time to market, and impose subset of its Superlog design language to be to what was done with Linux, Gnu, Apache, inefficient learning curves and risks. standardized ahead of the complete language. Netscape’s Mozilla and Sun Microsystems’ Jini. The company also said it was committed to stan- (Recently, Synopsys released OpenVera as Justifying C dardizing Superlog through Accellera.) an open language for functional verification. As CoWare Inc., for one, gives four rationales Smith’s third language is Rosetta. “Rosetta is an open, high-level, object-oriented language, for a system-level design language: First, unlike being developed as a true system-level lan- OpenVera addresses the complexity/productivity ASIC designs, SoCs are a combination of hard- guage,” he noted. “Think of it this way: RTL is a issue, as well as the mounting cry for non- ware and software—not just hardware—and, hardware language; ESL is a hardware/software proprietary solutions.) as a matter of fact, most designs contain more language; SL is the whole system: hardware, soft- What is all this fuss about? Basically, the software than hardware. Therefore, there is a ware, and mechanical—someday, including even SystemC modeling platform incorporates a set need for a language that describes the function- bioinformatics and who knows what else. People of C++ class libraries and a simulation kernel ality of both software and hardware; RTL lan- have been working on Rosetta for over five years that supports hardware modeling concepts at guages describe only the hardware. and it should finally be in use next year.” the system, behavioral and register-transfer Second, SoC designs increasingly incorpo- The idea behind Rosetta is that once the levels. Although systems architects and soft- rate hardware and software IP from various system design is completed, Rosetta will hand ware engineers widely deploy C/C++, it has no sources. All of these sources need to use a down the system description, with constraints semantics to adequately describe hardware common system-level design language so the (in a fully formally-provable format), to the ESL modeling concepts. SystemC’s C++ extensions entire system can be modeled. language. “If the other language efforts fail,” add the necessary constructs. Third, even hardware-only designs are Smith concludes, “it is conceivable that Rosetta Today, once a system has been partitioned becoming too complex to simulate in RTL. could hand off to Verilog and UML, on the soft- and handed off to the hardware and software Simulating the entire complex design at a high- ware side. It certainly could handle the ESL teams, software engineers re-describe the er level provides much faster simulation times behavioral portion of the design and let system-level architecture before proceeding and lets the designer test the behavior of the SystemC concentrate on the ESL architectural with their work. Moreover, the hardware engi- entire chip before it is produced. portion of the problem. We’ll have to see.” neers re-write the high-level C/C++ description Fourth, system-level design is no longer a into an entirely different language like VHDL or luxury—it’s a necessity. There’s no way a multi- Double speak Verilog. This creates a chasm between systems million-gate design can be successfully imple- Certainly, as designers move to higher level and software engineers and hardware engineers. mented the first time without careful system- languages, there will be an increasing need to It also creates the possibility of introducing level planning. System-level design also is perform some kind of mixed-language simula- errors and inconsistencies into the design as required to develop a virtual prototype of the tion or verification. Masami Yamazaki, a design people manually rewrite the C/C++ code. hardware that the software designers can use to manager at Fujitsu Transport, outlines the prob- SystemC fills this chasm and provides a begin software development. The old model of lem: “The biggest issue we faced with using refinement methodology from the original waiting until the hardware is finished to begin C++ in our hardware design flow was how to C/C++ functional and architectural descriptions, software development is totally out of date. Time simulate our C++ designs with our existing HDL thereby enabling hardware/software codesign to market is too important designs. It would be impractical to have to man- through a C-based modeling platform. Others agree. As part of the first phase of ually interface every new C++ design with our SystemC offers the ability to describe both its open-system design methodology initiative HDL simulator to do system-level verification hardware and software in the same high-level (ACE-1), NEC Electronics got around the slow with our existing HDL designs.” language, providing well-defined C-based con- speed of RTL simulators by going to C++ What Yamazaki was looking for was the abil- structs in a familiar and consistent program- abstracted models for early software/firmware ity to automatically generate FLI (Foreign ming environment. Because SystemC is open, verification. The result: a 100 times speedup in Language Interface) integration code for users can take advantage of a wide range of verification. mixed-language simulations. “That will make it EDA tools under development around it. Similarly, Innoveda’s Visual Elite has a easy for us to transition our design flow to Proponents of SystemC say that system hous- virtual prototype feature that lets hardware include C++,” Yamazaki said. es and semiconductor companies will benefit in development teams supply software developers Notably, C Level Design recently enhanced three ways: It will bring order to the chaos that with hardware design prototypes for early co- its System Compiler to provide Verilog exists today in the evolving system-level design verification against software blocks. The hard- Programming Language Interface (PLI) and software arena; it offers an alternative to creating ware models are described at various levels of VHDL FLI code generators to support mixed- and supporting proprietary libraries and tools; abstraction using C/C++, resulting in a high- language C++ and VHDL/Verilog simulations. and it allows companies to share models inside performance simulation environment. For its part, SystemC—which was devel- and outside their organizations. Visual Elite is Innoveda’s next-generation oped by CoWare, Frontier and Synopsys—lets IP providers will benefit because they can Visual HDL, expanded to support system-level designers model hardware concepts, such as provide a single set of models for each of their design methodologies, techniques and lan- concurrency, ports, and signals. An imminent cores to any systems house or semiconductor guages, including HW/SW codesign. With it, users version, 2.0, will add high-level modeling con- company—no more customized versions to can textually or graphically create design units in structs, such as channels and events. meet the different C-based modeling environ- C/C++ or SystemC and link the units to others Last fall, Synopsys and CoWare founded the ments; just create and validate a SystemC model created in HDL, dataflow macros or gates.
6 Other tools for building C++ or SC_MODULE(top) { with the goal of creating an exe- SystemC simulation models for sc_in
7 of ASIC engineering there. “It needs a Cynlib-to-Verilog equivalence The benefits STMicro derived from using SystemC: Seamless trans- checker, graphical entry system/viewer, testbench generation and IP formation from high-level, object-oriented program to high-level architec- model support.” ture and hardware implementation (following a top-down methodology); Mathstar, a year-old company specializing in digital signal processing, high-speed simulation of hardware models; and a mixed abstraction-level is in the process of developing an environment based around SystemC. modeling and simulation environment (C++ testbench and cycle-accurate Donna Salmi, an ASIC designer there who is highly experienced in the use hardware subsystems coexist in the same environment). of both Verilog and VHDL, said that, “We wanted to develop the hardware As those examples show, momentum for a new HDL is building; nev- and software together so we could have a hardware prototype that the ertheless, the “backforce” is considerable. SystemC has both rivals and software developers could use long before we have actual hardware. From detractors. Its main competitor is the Cynlib class library from Forte, the hardware perspective, SystemC has helped us get there a lot quicker.” which offers similar capabilities, such as constructs that let users model The part Salmi is working on executes extensive mathematical func- hardware concepts—concurrency, ports, signals, and the like; however, tions. “I used a combination of Module Compiler and SystemC,” she relat- CynApps president, Jacob Jacobsson, has been reported as seeking a ed, “the first to develop the lower level mathematical functions and the “convergence” between Cynlib and SystemC. second to do the scheduling for them. It’s worked pretty well, and I like As with any new design methodology, there’s a note of caution playing the ability to write C testbenches and a C hardware prototype without PLI through the engineering community—and a bit of skepticism resonating routines, and quickly get a functional simulation running.” within a cadre of designers who seem not to understand what problem is At Cadence Design Systems, a new release of its Signal Processing being solved. These technical iconoclasts see no need to raise the hard- Worksystem adds a feature that lets designers cosimulate with RTL mod- ware abstraction level. They say Verilog or VHDL is good enough for them els written in SystemC 1.0. and that architectures written in C can be easily translated to Verilog— Recently, the Fraunhofer Institute for Integrated Circuits and Siemens and then on to synthesis and gates. AG Austria individually reported successful deployments of SystemC, with Still, there is a need to get hardware and software to work together, both going to silicon. The former modeled a GPS receiver and the latter and some programmers would like to test their work on virtual proto- took an interrupt controller—already modeled in VHDL, verified by simu- types—which can be written in C. And as complexity continues to esca- lation and synthesized—replaced it by a SystemC model and then inte- late, will RTL continue rising to the occasion? grated it into a million-gate VHDL design. One who believes it is not necessary to leave RTL behind when work- And STMicroelectronics is modeling a 3D graphics pipeline with ing with multimillion gate chips is Cliff Cummings, a designer at Sunburst SystemC. Among other things, the company’s methodology consists of Design. He says that RTL with a few instantiated cores works great for object-oriented modeling in C++, and functional decomposition, in which multimillion-gate chips. His analysis: C++ objects are translated in SystemC blocks and C function calls are Many of those gates are instantiated cores and memories. Other gates translated in SystemC. take the form of 64-bit registers, instead of 16-bit registers, in which the only difference in the RTL code is the declaration size of the variables; the rest of the code remains unchanged. Cummings’ conclusion: Early abstrac- tion will not speed up the gate-level simulations at all. There’s been a misunderstanding, according to Kevin Kranen director of strategic programs for SystemC at Synopsys and an OSCI cochair. “RTL always will be needed,” he said, “but there’s a need for new approaches to architectural modeling and verification. For modeling, Synopsys believes SystemC is the solution; for verification, Synopsys advocates Vera.” In a heated panel discussion on design languages conducted last March at the International HDL Conference, the various advocates vehe- mently defended their respective approaches: “Verilog is not out of steam. If it ain’t broke, why fix it?,” said James Lee, a technical manager at Intrinsix Corp., who has designed several SoCs recently. Ahmad Ammar, an ASIC designer for Nortel Networks, doubted that any of the languages currently under development will become the be-all, end-all enabler of system-level design. “”There will be languages for the short, medium and long term,” he said. Ammar saw a short-term solution coming from languages that “push up” from or extend current HDL-based methodologies, with Superlog holding great promise for the next three to four years because Superlog does not require a radical shift in methodologies and allows groups to retain legacy code. “Superlog is Verilog done right,” agreed Gary Spivey, a senior member of the technical staff at Rincon Research Corp. Others said medium-range solutions likely will be C++-based lan- guages that have hardware design capabilities, such as SystemC and Cynlib. Long-term solutions for true system design likely will come from Rosetta, Ptolemy II, or the GSRC’s MoML. “Existing languages can be extended upward or downward, but to address real system design, not just system-chip design, new languages need to be created,”said Vassilios Gerousis, Design System Architect for Infineon Technologies. Gerousis also noted ality possible today, Forte’s John Sanguinetti few as possible; however, our customers are that many languages, rather than one, will sup- insists RTL won’t work. “Look out ten years, voting quite vociferously for SystemC.” port true system-level design. and clearly we need a higher level of abstrac- C Level Design’s David Park, Vice President According to Steve Schulz, Vice Chairman of tion,” he argues. “The question is, how and of Marketing, says “system” is in the mind of standards organization, Accellera and the when?” the beholder. “It can be an ASIC, a cell phone, a founder of the SLDL Initiative, the idea of a The cut-off point already has been network switch, but we think of it as an elec- grand unified language is fundamentally flawed. reached—around 20,000 gates—Sanguinetti tronic composition of hardware and software “We will have multiple languages targeting spe- contended. His response to those who believe components; software for flexibility, hardware cific areas,” he offered. “These languages will otherwise: “It’s safe to say that nobody’s going for performance.” be easier to learn than a grand language and to do a 100-million-gate design with RTL; 5-mil- “Based on that definition, system-level they also will be easier for tools to parse.” lion gates? Perhaps that’s debatable—but RTL modeling and codesign are of the essence, and At the end of the session, a vote on which definitely breaks somewhere between those that’s why we have focused on C and C++,” approach audience members would use if they two numbers.” Park related. “It boils down to this reality: The were starting a new chip design project within The way Sanguinetti sees it, “those RTL software can only run on the intended hard- six months showed only two or three hands for guys have got their heads in the sand.” ware. Prior to the existence of the hardware, SystemC, Cynlib and C Level Design; Superlog If an abstract language is needed, why C? the verification options include a coverification and Verilog each received around 20 votes; how- Because a system can be defined as an tool, such as Mentor’s Seamless or Synopsys’ ever, no vote was taken for projects further out. executable specification, and executables are Eagle-I, or an emulation environment, or an None of that debate has detoured Co- almost always programmed in C, Sanguinetti existing hardware description.” Design Automation from continuing with the answered. “It makes sense because the design “The problem is,” Park continued, “if you development of its Superlog design language, language contenders are close to C++, which is want to run in a software-based environment, which weaves C and other constructs into extendible and layerable. Different levels of the HDL is just too slow.” His conclusion: “You Verilog in support of concurrency, messaging abstraction can be derived with layers of need to have a common language among the and timing. Nor has it stopped Get2Chip, which classes—that’s the key to hierarchical design.” software and hardware designers—but it’s a recently rolled out Volare, the first Superlog religious issue. To sort out all of the language synthesis tool. The nitty gritty contenders, ask this: Will the language run on a “There are lots of proposals floating around, Stanley Krolikoski, Vice President of the processor? HDL won’t; C code will.” but they fall into two categories,” said David Kelf, System Level Design Group at Cadence Design Although Park acknowledges that issues for Vice President of Marketing at Co-Design systems, defines system design as work taking partitioning and co-design and other system Automation, “those trying to leverage C and C++ place above the RT level, particularly untimed areas still remain on the table, he believes the class libraries into a new language format, that is, levels where designers work algorithms down to benefits of a single C-based language tilt the driving C++ into the hardware space, and those blocks of IP or perform trade-off analyses of balance. For software engineers, C is fast trying to create a new language or extend an high-level architectural descriptions represent- enough for hardware simulations; for hardware existing HDL to leverage greater abstraction and ing underlying hardware. engineers, its coded hardware functionality is more powerful verification.” “People have been doing that kind of design fairly understandable. In any case, automated To that end, Co-Design provides a cosimula- for years,” Krolikoski emphasized, “for exam- partitioning and co-design tools need to start tion environment between C++ and Verilog so ple, the digital portion of most cell phones. from a common language. SystemC and Superlog components can be They could have been using such EDA tools as “We’re trying to work out the methodology mixed. Superlog also “entertains” the notion of SPW or COSSAP or MatLab or even a white for a common language,” Park said, referring to classes and object-oriented styles. board.” work at Accellera and the SRM (Semantics Kelf reminds that a Verilog design flow usu- Krolikoski acknowledges that timing, signal Reference Manual), “which doesn’t rule out ally runs into trouble on the verification side, integrity effects and other details still must be the use of other languages when needed.” “leading people to code up complex testbenches resolved at the lower levels, but recommends Dan Skilken, President of C Level, added this: and look for ways to effectively analyze simula- executing as much of the design as possible at “It’s significant how quickly momentum built for tion results and drive new tests into simulation. the highest level possible. “Then, you can con- SystemC. But it’s evolving quickly, too—it’s on its Neither Verilog nor VHDL contains those pieces. centrate on timing and other details, starting at fourth generation already—so the standard is Z and Vera provide the extra verification func- the RT level.” more one of language than of methodology. That tionality but users must jump into an entirely dif- But when designers ascend the abstraction and the slowness of simulation make it less com- ferently language, a painful situation.” ladder, do they really need to bring along a sys- pelling for hardware designers to adopt it in its The unwieldy code yielded by Verilog with tem design language? It depends on the com- current form. People are using it for system large designs drives designers to seek the more plexity of the system, according to Krolikoski, modeling and high-level simulations, but little concise coding styles and faster simulations who defines a likely candidate: a system, or implementation is coming out of it.” associated with higher levels of abstraction. integration platform, model that contains sev- “We’re hoping that specC and SystemC will While they are at it, they probably seek better eral control processors, at least one or perhaps converge someday,” Skilken revealed, “which ways to reuse IP, another Verilog shortcoming. a bank of DSPs, some complex buses, and a could happen with the 3.0 version of SystemC.” “Those drivers alone spell the need for new bunch of memory caches. Meanwhile, VHDL received a booster shot language capabilities,” Kelf concluded. “The “Having a language that allows for the inter- in the form of VITAL-2000, just approved by the best way to improve productivity is to encom- change of IP is reason enough,” he advises, IEEE and Accellera as an ASIC modeling stan- pass all of the needs in one language, one which “but a language with an agreed upon set of sim- dard. In addition, support is growing for those allows a single simulation tool to drive verifica- ulation semantics is also useful.” mixing VHDL- and Verilog-based IP on the same tion and greater abstraction.” “The problem is, there are way too many chip. Some recent mixed-language additions: Given the physical, or executable, function- languages,” Krolikoski concedes. “We’d like as simulation and verification from Synopsys; ASIC
12 prototyping software from Synplicity; and, for C-Level Design’s System Nodding to the Accellera work on universal semantics and syntaxes, Compiler, a new PLI/FLI generation capability which automates mixed-lan- Brophy said, “whether that ends up as C++ or Java or whatever, the lan- guage simulation with C++ and VHDL/Verilog for system-level verification. guage is not the important thing, and in any case, translators are always Synthesis is a key to acceptance of any HDL (as is simulation and verifi- available. Remember, too, system design encompasses more than digital, cation). For instance, as it turned out, Netrake ended up working with RTL especially if you’re talking about a single chip. There can be mathematical anyway. Their approach was to write the RTL model in Cynlib and use algorithms, such as those from Matlab or MathWorks, and analog and RF CynApps tools to translate to Verilog, which it then uses for synthesis. functions. Those are not covered by any current work on languages or According to Lie, Netrake stayed with RTL because no high-level syn- semantics.” thesis tool was available for writing at a more abstract level—the only way Thus, the Accellera system-level design standards group is collaborat- to produce synthesizable code was by writing at the RT level. ing with almost everybody on the C front—SystemC, SpecC, Cynlib, and Because of user pull like that of Netrake, at this year’s Design others. But there is a bigger picture: The group also is working with uni- Automation and Test in Europe conference, Co-Design Automation said it versity researchers. Brophy explains: “Perhaps you’ll have VHDL, would allow the synthesis subset of Superlog to be standardized ahead of SystemC, MatLab, UML, SDL, and so on, each for a different part of a sys- the complete language. Dave Kelf said the company was committed to stan- tem. The Rosetta language may help in getting all those languages to work dardization through Accellera. together, or translate from one facet or domain to another. It also can help Certainly, standardization will be essential before any language is uni- set overall system constraints for such parameters as cost, power dissi- versally accepted. To that end, Accellera (a fusion of the former Open pation and consumption, and so on.” Verilog International and VHDL International organizations) is evaluating a When will it all sort out? On the C front, Brophy says Accellera already bunch of submitted languages and verification technologies. has articulated a “semantic notion” for RTL and initiated work on archi- The question still remains: Are hardware languages alone enough for tectural semantics. By now, some of that work should have been solidified. “true” system design? What about software, a growing portion of many sys- For Rosetta, workshops and tutorials are under way, and tools are tems? Can both the hardware and software elements of a contemporary sys- imminent. tem be fused into a single standardized design methodology? Is that even For one, Kansas University has a Rosetta parser that EDA companies worth considering? can use for “quick-start” explorations in applications. U.C. Berkeley’s “We are exploring whether there’s a false wall between hardware and Ptolemy II semantic environment should soon “see the light of day” in software design,” declared Dennis Brophy, Chairman of Accellera, “But for Accellera’s semantic reference manual, Brophy delineated. systems design, we still need to bring hardware and software teams “It’s all going to be evolutionary,” Brophy emphasized, “despite the together so we can begin to invent tools that allow written specifications push to close the design gap by going to C.” to lead to either software or hardware.” But is there time? Recently, Daniel Gajski, a professor at UC Irvine (who is working on the SpecC class library) was quoted as saying, “In five years chips are going to be mostly software. The language is not the issue; it’s methodology—how can we handle these complex problems? I don’t think the EDA industry is aware that they are in front of a firing squad.” Given its latest growth rates, the demise of the EDA industry is great- ly exaggerated. More plausibly, the industry will change to keep up with technology, as it always has. Flows and methodologies and tools will change commensurately. One of the new methodologies receiving atten- tion is platform-based design.
Jumping on the platform “The single most important thing we have done to improve design pro- ductivity, and to help deliver new products to market quickly, is to develop SoC design platforms,” declared Jean-Marc Chateau, Director of Design in the Consumer and Microcontroller Groups at STMicroelectronics. “We develop the base architecture and then our customers, either internal prod- uct groups or external design teams at systems houses, build on the platforms and customize for a particular application.” What is platform-based design? STMicro defines it as the creation of a stable microprocessor-based architecture that can be rapidly extended, customized for a range of applications and delivered to customers for quick deployment. The processor core can be a DSP, a microcontroller or several of each. For example, STMicro used platform-based design techniques for a wide range of wireless and wireline devices and consumer products, including digital television, DVD players, and set-top boxes. The company has developed many platforms using a variety of processors, for example, the ARM7, ST20, ST40, DSP950, and MMDSP. One recent set-top box design employed five CPUs. The productivity improvements gained from platform-based design have had a major impact on STMicro. The company can start software designs much earlier in the design process and quickly verify that silicon will be functionally and architecturally correct. Also, the STMicro designers can
13 reuse components throughout the organization. Electric Industrial Co. Ltd., Sony and others. could include analog, RF, software and electro- But what about the end designers, the platform N2C helps engineering teams explore different optical and mechanical components.” users? How do they benefit? architectures, analyze the best way to partition The first release (last January), the Visual “It remains for customers to differentiate a a design into hardware and software, perform Elite family, includes mixed, abstract communi- platform for a particular application,” Chateau hardware/software co-simulation, and refine cations protocols, interconnected functional said. “They do that by building on the platform the design to RTL and object code for blocks whose behavior can be defined in C, and synthesizing the interfaces between the implementation. Verilog, VHDL, state flow diagrams, tables, and base platform hardware and other hardware Matsushita is deploying N2C for SoC devices so on—in any combination at any level of and software elements that need to be added. A and software for consumer electronics applica- design. large part of that involves generating a detailed tions, such as mobile phones. “We’ve already “With one environment, you can analyze dif- application-programming interface (API) so used it to design a block in an SoC,” revealed ferent architectural concepts—at the system- that embedded software can be mapped to the Yoshifumi Okamoto, General Manager of the within-a-system or system-within-a-module or processors.” EDA Technology Development Group at system-within-a-chip level—and take a direct “Platform-based design is a way of doing Matsushita’s Corporate Semiconductor path to translate from the abstract to structur- system-level design in a constrained fashion,” Development Div. “At present, N2C is the only al interfaces that include wires, bits, signals, said Serge Leef. “There’s no way to synthesize practical co-design tool available.” and so on,” Hayden related. a system-level description, even if there were a Okamoto noted that about 80 percent of the Work is proceeding on other system fronts. mutually-agreed on language. It’s a much hard- performance and cost of a final system is For example, with emulation becoming so er problem than behavioral synthesis which, in decided in the process of defining system important for system designs, there has been a turn, is harder than RTL synthesis. A break- specifications and architecture design. “A call for some kind of API standard. To that end, through or invention is required to solve the design’s iteration loop will be small with N2C the SCE-API consortium, formed at DAC last general problem, and there’s nothing in sight, and we expect to increase efficiency in design,” year, announced the completion of phase one so we’re six to ten years away from a commer- he concluded. of the specification for a common emulation cial solution,” Leef analyzed. application interface. In actuality, the system-level design prob- Tools wanted The result is a standard transaction-oriented lem has been constrained dramatically, in that Other tools are available but are confined modeling interface for emulators which provides many designs are redesigns or contain signifi- to designing hardware only, with verification in multiple message-passing channels between cant legacy components. Take the embedded C or hardware/software co-verification at the software models running on a host workstation arena. Perhaps two-thirds of the design starts in RTL abstraction level, which, as Okamato notes, and RTL models running in an emulator. The con- the wireless subscriber and infrastructure mar- may be too late in the design cycle. Slow verifi- sortium is collaborating with OSCI and Accellera, kets are based on ARM processors. ARM brings cation run time is another issue. And, of course, to make the technology (donated by IKOS with it a standardized bus, Amba, and a standard co-design attacks the primary cause of silicon Systems) widely available. operating system, such as Epoch or OSE Enea, spins—logical and functional errors that pri- The interface allows third parties and com- and a bunch of Amba-compatible peripherals marily stem from incomplete or changing peting emulation vendors to use a common (MPEG cores, for example, or USB or encryp- specifications. interface for connecting third-party software tion, or even DSP chips). There is no need to Note that tools that offer hardware design tools and user software models to all emulators start a system design with a blank sheet. in C are plentiful but can fall short on the soft- and simulators that support the solution. Constraining a system through such a ware side. Or those that are oriented toward According to Gerard Mas, a manager at the block-based approach makes the system syn- algorithm design may not attack the whole chip CMG division of STMicroelectronics, the API thesis plausible, Leef notes. “Your can write problem. will allow users to more easily interface soft- some functionality in algorithmic C, place it into Other things to watch for: Statistical model- ware models and tools from organizations that memory and see how well the function works. If ing tools that perform some high-level per- supply intelligent test benches and C and C-like it doesn’t meet the objective, you then can use formance modeling, but do not provide a path modeling environments. algorithmic synthesis to render the function in to implementation; co-verification tools that One area of design, analog and mixed signal, RTL hardware and see how that works. verify RTL hardware against software running has been mostly neglected at the system level— Subsequently, you can use an algorithmic syn- on instruction set simulators, which may come perhaps because its dependence on physical thesis tool to optimize hardware parameters, in too late in the design cycle or take too long layout makes it one of the toughest areas to such as performance vs. size and power con- for whole-chip simulation, or can verify only raise to higher levels of abstraction. sumption or weight.” one block at a time. Nevertheless, to some, systems design cannot There are plenty of choices available to What about the “rest” of the system? Work is be called complete unless the analog or mixed- designers who opt for platform-based design under way at some quarters and some exciting signal elements are included in the process. and the aggregation of related IP. For instance, breakthroughs appear imminent. Innoveda, for So far, the C and other language efforts Texas Instruments offers OMAP, a platform for one, is extending its visual HDL design-flow have concentrated on the digital aspects of a 2.5G and 3G subscriber devices; for networking capabilities to stretch from system to compo- system, except for a version of VHDL that applications, Xilinx places PowerPCs on its nent, including the electromechanical end: includes analog constructs; however, AVHDL Vertex FPGA line: platforms are available from boards, cabling, and the like. has a long way to go. Altera, Actel, LSI Logic, Motorola, Philips, “We’re using the IEEE definition of a sys- If there are any breakthroughs, they may STMicroelectronics, and plenty of others. tem, the broadest one possible,” said Warren come from the likes of a Mentor Graphics or However, tools are not that plentiful. Hayden, Marketing Director of the U.S. SLD Tanner EDA, two companies which have fielded Worthy of attention is CoWare’s N2C C- Group at Innoveda, “attacking even the top- strong efforts in software for analog and language-based hardware/software co-design level system-within-a-system—a multiple-unit, mixed-signal design. system, used by Alcatel, STMicro, Matsushita multiple-card, multiple-domain product, which
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