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Article Fabrication of Through via Holes in Ultra-Thin Fused Silica Wafers for Microwave and Millimeter-Wave Applications

Xiao Li *, King Yuk Chan and Rodica Ramer

School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, NSW 2052, Australia; [email protected] (K.Y.C.); [email protected] (R.R.) * Correspondence: [email protected]; Tel.: +61-2-9385-0914

Received: 14 February 2018; Accepted: 16 March 2018; Published: 20 March 2018

Abstract: Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave circuits and 3D integration. In this work, etching through via holes in ultra-thin fused silica wafers using deep reactive-ion etching (DRIE) and laser ablation was developed and analyzed. The experimental setup and process parameters for both methods are presented and compared. For DRIE, three types of mask materials including KMPR 1035 (Nippon Kayaku, Tokyo, Japan) photoresist, amorphous silicon and chromium—with their corresponding optimized processing recipes—were tested, aiming at etching through a 100 µm fused silica . From the experiments, we concluded that using chromium as the masking material is the best choice when using DRIE. However, we found that the laser ablation method with a laser pulse fluence of 2.89 J/cm2 and a pulse overlap of 91% has advantages over DRIE. The laser ablation method has a simpler process complexity, while offering a fair etching result. In particular, the sidewall profile angle is measured to be 75◦ to the bottom surface of the wafer, which is ideal for the subsequent metallization process. As a demonstration, a two-inch wafer with 624 via holes was processed using both technologies, and the laser ablation method showed better efficiency compared to DRIE.

Keywords: microwave and millimeter-wave; through via hole; fused silica; DRIE; laser ablation; etch rate

1. Introduction

Fused silica (SiOx) and quartz wafers are widely used in planar microwave and millimeter-wave circuits, due to their low loss properties and good thermal shock resistance. Microstrip technology has become the best known planar transmission line medium for radio frequency (RF) and microwave circuits. The popularity and widespread applications are due to microstrip line circuit’s planar nature, ease of fabrication using the various processes available, easy integration with solid-state devices, and good mechanical support. The ground plane connection plays a critical role in microstrip line circuits, as when a high frequency signal is conveyed in microstrip transmission mode, the energy is concentrated between the signal line and the ground plane. At the same time, it can affect the transition from coplanar waveguide (CPW) mode to microstrip mode. Transitions between microstrip and CPW were proposed and measured in [1–3], and the results showed that the ground plane implementation has a large impact on the bandwidth, insertion loss, as well as the chip size. With the increase in frequency, a thinner substrate is preferable [4] in order to reduce the dispersion and radiation loss. The microstrip line dispersion is proportionate to the ratio of substrate thickness to effective wavelength, so the substrate thickness should be decreased to maintain the required dispersion level at higher frequency [5]. Thin substrates also need a narrower microstrip line width to keep certain characteristic impedances, which allow the miniaturization of the structure and reduce radiation.

Micromachines 2018, 9, 138; doi:10.3390/mi9030138 www.mdpi.com/journal/micromachines Micromachines 2018, 9, 138 2 of 9

The traditional methods to make ground connection are radial stub virtual ground bonding and wire bonding. Radial stubs can reduce the costs of fabrication [6]; however, they will lead to unpredictable resonance which can be eliminated by silver paint ground connection [7]. Wire bonding is another option to make ground connections, and ribbon bonding could highly reduce the parasitic inductance compared to normal wire bonding. Despite the improvement in bonding techniques, proper capacitive compensation circuits need to be applied [8]. Besides this, dicing and bonding are deemed not suitable with pre-packaged RF micro-electromechanical system (MEMS) structures. As a result, a better ground connection method is required, which leads to the suggestion of through via holes in glass wafers. Moreover, 3D RF integration has become popular in recent years due to the continuously increasing demand for product miniaturization, high package density and better performance. Compared to other substrates used for passive microwave components, such as polytetrafluoroethylene (PTFE) and alumina, fused silica is viewed as a prospective material and has attracted a great deal of interest in RF integrated packaging applications. This is because fused silica wafers are homogeneous materials which offer compatibility with commercial wafer processes, dimensional stability against heat and humidity, and scalability when production shifts to the panel process from the wafer process [9]. Microwave components, such as spiral inductors, filters and interconnections using fused silica wafers were simulated and analyzed in [10,11]. The return loss, the insertion loss and the isolation show that using fused silica as the interposer material provides obviously improved RF performance compared to silicon material. Also, using through via holes for antennas could enable new integration and packaging opportunities in the millimetre-wave range. In [12], a directional through via holes antenna was designed and fabricated for point-to-point wireless communications, at a centre frequency of 78 GHz. Researchers in process engineering conducted different micromachining technologies in order to fabricate through via holes in quartz and fused silica wafers. These technologies were sorted and summarized in [13]. Chemical machining using DRIE and thermal machining using laser ablation are the two solutions which can accommodate ultra-thin wafers and offer a good profile for the subsequent metallization. In [14], using a single-layer KMPR photoresist mask, up to 30 µm deep via holes were successfully etched with an etch rate about 0.5 µm/min and a mask selectivity over 1. Tang et al. used 5.5 h to etch through the 150 µm thick fused silica wafers with the optimized process parameters obtained from experiments [15]. It also suggested that, compared to a Ni-Co metal mask, a KMPR photoresist mask is more suitable for fused silica through via hole etching. Using a nanosecond and femtosecond laser to etch high quality, high aspect ratio and crack-free microfeatures in glass substrates were reported in [16,17], and through glass via interposers used in 3D integration were fabricated in [18]. However, etching through via holes in ultra-thin fused silica wafers using laser ablation has been less explored. Considering the wide range of applications, fabrication processes using DRIE and laser for etching through via holes in ultra-thin fused silica wafers were studied and optimized, and are reported in this paper. The pros and cons of both methods were analyzed based on experimental results. To our knowledge, although both technologies have been explored in the literature separately, there is no literature research comparing the two technologies and analyzing their feasibility for through via holes etching in ultra-thin fused silica wafers.

2. Experiment

2.1. Inductively Coupled -Reactive Ion Etching (ICP-RIE) of Fused Silica A typical through via holes fabrication process using the inductively coupled plasma-reactive ion etching (ICP-RIE) dry etching method is shown in Figure1. The etched double-sided polished fused silica sample had a diameter of two inches and a thickness of 100 µm. Micromachines 2018, 9, 138 3 of 9 Micromachines 2018, 9, x 3 of 9

Figure 1.1. ThroughThrough via via hole fabrication process by deep reactive-ionreactive-ion etching (DRIE):(DRIE): (a) SampleSample cleaning; (b(b)) Deposition Deposition of of mask mask material; material; (c) Transfer(c) Transfer of desired of desired pattern; pattern; (d) Desired (d) patternDesired achieved; pattern (achieved;e) Inductively (e) Inductively coupled plasma-reactive coupled plasma ion- etchingreactive (ICP-RIE) ion etching dry (ICP etching;-RIE) ( fdry) Removal etching; of ( maskf) Removal residual. of mask residual.

First of all, thethe samplesample hadhad toto bebe properlyproperly cleanedcleaned inin piranhapiranha solution,solution, acetoneacetone andand isopropylisopropyl alcohol. Secondly, aa layerlayer ofof mask material waswas deposited onon the wafer and this layer will protect the waferwafer from plasmaplasma attack in the non-vianon-via area. Thirdly, thethe transfertransfer of desireddesired patternspatterns to the etching mask waswas carriedcarried out. out. Then, Then, the the two-inch two-inch sample sample was wa attacheds attached to ato four-inch a four-inch silicon silicon carrier carrier wafer wafer with aluminiumwith alumin coolingium cooling grease grease (from Amerasia(from Amerasia International International Technology, Technology, Inc., West Inc. Windsor,, West NJ,Windsor, USA) andNJ, etchedUSA) and in an etched ICP-RIE in an system. ICP-RIE Finally, system. the Finally, mask material the mask was material removed. was removed. Three differentdifferent types types of maskof mask material material were were tested tested and compared and compared in the etching in the process,etching including process, KMPRincluding 1035 KMPR (from 1035 Nippon (from Kayaku, Nippon Tokyo, Kayaku Japan), Tokyo photoresist,, Japan) photoresist, amorphous amorphous silicon (a-Si) silicon and chromium. (a-Si) and Thechromiu KMPRm. The 1035 KMPR was spin 1035 coated was spin at acoated speed at of a 2000speed rpm of 2000 to get rpm 70 toµ mget film 70 μ thickness.m film thickness. Then it Then was ◦ ◦ ◦ softit wa bakeds soft atbaked 30 C at for 30 10°C min, for 10 followed min, followed by 50 C by for 50 10 °C min for and 10 100min andC for 100 30 °C min. for After 30 min. exposing After 2 ◦ itexposing to 2200 it mJ/cm to 2200UV mJ/cm light,2 UV the light, sample the wassample post-baked was post at-baked 100 C at for 100 4 °C min for and 4 min developed and develop in SU-8ed developerin SU-8 developer for 6 min. for 6 min. Unlike using photoresist alone,alone, which can be directly patterned by , an extraextra photoresist maskmask layer is needed when transferring the desired pattern to the a a-Si-Si or or chromium chromium mas mask.k. The a-Sia-Si mask waswas deposited using the Oxford PECVD (Oxford(Oxford Instruments, Oxfordshire,Oxfordshire, UK)UK) with ◦ a deposition chamber pressure of 1500 mTorr, temperaturetemperature of 300 °C,C, heliumhelium gas flow flow of 475 sccm sccm,, SiH4 gasgas flow flow of of 25 25 sccm sccm,, and and an an RF RF power power of of20 20W. W.The The desired desired pattern pattern was was then then transferred transferred to a- toSi a-Simask mask using using RIE dry RIE etching dry etching with withnegative negative photoresist photoresist nLOF nLOF20202020 (from (from Microchemicals Microchemicals GmbH GmbH,, Ulm, Ulm,Germany Germany)) applied applied as an asetching an etching mask. mask.The chromium The chromium mask layer mask wa layers deposited was deposited with a withHHV a ( HHVHind (HindHigh High Vacuum Company Company Private Private Limited, Limited, Crawley, Crawley, UK) magnetron UK) magnetron sputtering sputtering system systemwith 600 with W 600direct W directcurrent current (DC) power, (DC) power, an an argon gas flow gas flow of 15 of sccm 15 sccm and and a deposition a deposition pressure pressure of of 15 15 mTorr. mTorr. Similarly, nLOF2020nLOF2020 photoresist photoresist was was used used as an as etching an etching mask andmask chromium and chromium was etched was in chromiumetched in etchantchromium (from etchant Sigma (from Aldrich, Sigma St. Aldrich Louis, MO,, St. Louis, USA). MO, USA). After the deposition and patterning of the mask materials, the fused silica samples werewere etched in the STS ICP RIE system ( (SurfaceSurface Technology Systems Plc. Plc.,, Newport, UK UK).). According According to to [1 [144,,15,19,19],], + = fluorocarbonfluorocarbon plasmaplasma CFx ((x =1,1, 2 2,, 3 3)) with high energy can slowly react with SiOxx. At At the the same same time, time, the combinationcombination with inert+ gases will boost the etch rate of fused silica by physical b bombardment.ombardment. 𝐶𝐶𝐶𝐶𝑥𝑥 𝑥𝑥 Since the etch etch rate rate is is very very slow, slow, this this becomes becomes the the key key criteria criteria when when exploring exploring the theetching etching recipe. recipe. By Byvarying varying the the process process parameters parameters and and considering considering the the available available conditions conditions in in the the lab, lab, the the best best process characterization was found to be:be: 300 scc sccmm heliumhelium flow,flow, 3030 sccmsccm CC44F8 flow,flow, 1400 W inductivelyinductively coupled plasmaplasma (ICP) (ICP power,) power, 400 400 W biasW bias power, power, 10 mTorr 10 mTorr chamber chamber pressure, pressure, and the and backside the backside cooling ◦ temperaturecooling temperature was set towa 20s setC. to 20 °C.

2.2. Laser Ablation of Fused Silica 2.2. Laser Ablation of Fused Silica Compared to the dry etching method, using laser ablation turns out to be a simpler process for etching through via holes in fusedfused silicasilica wafer.wafer. It does not include mask layer depositiondeposition and the conventional photolithography required for the desired patterning. Here, 2D high precision machining is applied to draw the desired pattern. In our experiments, the machining station

Micromachines 2018, 9, 138 4 of 9 conventionalMicromachines 2018 photolithography, 9, x required for the desired patterning. Here, 2D high precision machining4 of 9 is applied to draw the desired pattern. In our experiments, the machining station (Microstruct-C), with(Microstruct Scanlab’s-C), galvo with scanners Scanlab’s for galvo marking scanners and an for XY marking table for and sample an XY positioning, table for sample offered positioning, a positional erroroffered of lessa positional than 1.5 µerrorm. Since of less the throughthan 1.5 via μm. holes Sinc usede the in microwavethrough via applications holes usedwere in microwave fabricated asapplications described inwe there fabricated first step, alignmentas described marks in the form first at thestep, same alignment time, which marks are form fully at compatible the same time with, thewhich following are fully compatible with fabrication the following processes. semiconductor fabrication processes. Our laser system system (Coherent (Coherent Supe Superr Rapid Rapid-HE,-HE, Coherent, Coherent, Inc., Inc., Santa Santa Clara, Clara, CA, CA, USA USA),), used used for the for theablation ablation process process,, can canproduce produce 10 ps 10 pulsed ps pulsed laser laser with with a repetition a repetition rate rate of of20 20kHz kHz,, and and the the beam beam is isdelivered delivered through through a F a = F 100 = 100 mm, mm, f-theta f-theta lens, lens, producing producing a 15 a μ 15m µspotm spot at focus. at focus. To etch To etchthe ve thery verythin thinfused fused silica silica wafer, wafer, the thesecond second harmonic harmonic output output,, which which gives gives a awavelength wavelength of of 532 532 nm nm,, was was chosen chosen,, because this leads to moremore efficientefficient non-linearnon-linear absorptionabsorption andand smallersmaller laserlaser spotspot size.size. The laser ablation of fused silica will leave debris around the etched patterns, and the debris is difficultdifficult to removeremove withoutwithout mechanical wiping or polishing. Consequently, photoresist is coated on both sidessides of the wafer as protection. Then, the fused silica wafer is suspended above a large silicon plate with glass glass s slideslides supporting supporting its its edges. edges. When When processing processing the the 100 100 μmµ thickm thick fused fused silica silica wafer wafer,, we wefound found that that it wa it wass very very fragile fragile and and prone prone to to becom becominging chipped chipped and and even even cracked cracked when when processed processed at high powerspowers andand speeds. speeds. Cracks Cracks on on and and in in the the wafers wafers are are problematic problematic in microwavein microwave circuits circuits as they as they will formwill short-circuitsform short-circuits or introduce or introduce additional equivalentadditional radialequivalent stubs in radial the subsequent stubs in metallization the subsequent steps. Inmetallization consequence, steps. the etchingIn consequence, strategy adoptedthe etching was strategy to use low adopted power, was within to use an orderlow power, of magnitude within an of theorder glass of magnitude damage threshold, of the glass and damage with many threshold, repetitions and with of the many pattern repetitions in order of to the gently pattern cut throughin order theto gently fused cut silica through wafer. Athe set fused of five silica concentric wafer. A squares set of withfive concentric 10 µm offset squares was used with as 10 the μm etch offset pattern was toused create as the a 50etchµm pattern kerf for to create the centre a 50 μ tom fall kerf away for the in cent a ‘non-contact’re to fall away fashion, in a ‘non as- showncontact’ in fashion, Figure 2as. Theshown scanning in Fig speedure 2. ofThe laser scanning beam wasspeed set of to 25laser mm/s beam in wa equivalents set to 25 to amm/s pulse in overlap equivalent of 91% to to a createpulse aoverlap smooth of etching 91% to result.create a smooth etching result.

Figure 2. Methodology of laser ablating fused silica.

3. Results and Analysis

3.1. ICP-RIEICP-RIE of FusedFused SilicaSilica The experimentalexperimental resultsresults indicate indicate that that the the etch etch rate rate is mainlyis mainly proportional proportional to both to both ICP ICP power power and biasand power,bias power, because because the ICP the power ICP powe determinesr determines the plasma the plasma density density in the chamberin the chamber and the and bias the power bias givespower the gives etching the momentumetching momentum of the high of energythe high ions. energy We also ions. found We thatalso thefound selectivity that the between selectivity the fusedbetween silica theand fused the silica mask and material the mask decreases material when decreases the bias when power the bias is higher, power sois higher, there is so a trade-offthere is a trade-off when determining the bias power. The etching results obtained by the optimized process conditions are shown in Table 1.

Micromachines 2018, 9, 138 5 of 9 when determining the bias power. The etching results obtained by the optimized process conditions Micromachines 2018, 9, x 5 of 9 are shown in Table1.

Table 1. Fused silica etch rate and selectivity.

Mask Etch time Etched SiOx Depth Etched Mask Etch Rate Etch time Etched SiO Depth Etched Mask Depth Etch Rate Selectivity MaterialMask Material (min) (μm) x Depth (μm) (μm/min) Selectivity (min) (µm) (µm) (µm/min) KMPR 1035 110 57 43 0.52 1.33 KMPR 1035 110 57 43 0.52 1.33 a-Silicon 2.5 1 0.27 0.4 3.7 a-Silicon 2.5 1 0.27 0.4 3.7 ChromiumChromium 45 4522 221 1 0.490.49 22 22

The highest achieved etch rate was 0.52 μm/min, so it needs at least 3.5 h to fully etch through The highest achieved etch rate was 0.52 µm/min, so it needs at least 3.5 h to fully etch through the 100 μm fused silica wafer. During the long period of continuous etching, a lot of heat is generated the 100 µm fused silica wafer. During the long period of continuous etching, a lot of heat is generated by ion bombardment and then accumulated, which can seriously burn the photoresist mask and by ion bombardment and then accumulated, which can seriously burn the photoresist mask and lower lower the etching selectivity between fused silica and mask material. It should be noted that the the etching selectivity between fused silica and mask material. It should be noted that the burned burned photoresist is very difficult to remove. This burning cannot be avoided even though different photoresist is very difficult to remove. This burning cannot be avoided even though different measures measures have been taken. The sample was attached to a four-inch silicon wafer with a backside kept have been taken. The sample was attached to a four-inch silicon wafer with a backside kept at 20 ◦C and at 20°C and with aluminium paste to lower the heat. However, fused silica does not have good with aluminium paste to lower the heat. However, fused silica does not have good thermal conductivity thermal conductivity to convey the generated heat from the mask surface to the carrier wafer. to convey the generated heat from the mask surface to the carrier wafer. Meanwhile, the etching Meanwhile, the etching process was separated into small intervals to reduce the temperature process was separated into small intervals to reduce the temperature accumulation. The sample was accumulation. The sample was taken out from the process chamber every 30 min, and was cooled taken out from the process chamber every 30 min, and was cooled down to room temperature. down to room temperature. Figure3 illustrates the scanning electron microscopy (SEM) micrograph of the etched results. Figure 3 illustrates the scanning electron microscopy (SEM) micrograph of the etched results. The etched via holes had dimensions of 100 µm × 50 µm. Dry etching of the fused silica wafer with The etched via holes had dimensions of 100 μm × 50 μm. Dry etching of the fused silica wafer with ICP RIE gave a smooth sidewall finish and the sidewall angle was above 85◦, as shown in Figure3a. ICP RIE gave a smooth sidewall finish and the sidewall angle was above 85°, as shown in Figure 3a. One of the shortcomings of using thick photoresist as the etching mask is illustrated in Figure3b. One of the shortcomings of using thick photoresist as the etching mask is illustrated in Figure 3b. The The etched sample was cleaned by piranha solution for half an hour, but the burnt residual on top of etched sample was cleaned by piranha solution for half an hour, but the burnt residual on top of the the fused silica sample cannot be removed. fused silica sample cannot be removed.

Figure 3. Scanning electron microscopy ( (SEM)SEM) micrographs:micrographs: ( (aa)) T Thehe etched fused silica using the optimal recipe;recipe; (b)) OverOver burnt KMPR 10351035 residual.residual.

Another disadvantage of the KMPR 1035 mask is the high stress. Typically, wafers with a thicknessAnother over disadvantage 200 μm do not of theshow KMPR any 1035shape mask change is the after high applying stress. Typically, the thick wafersphotoresist. with a However, thickness µ overfor an 200 ultram-thin do wafer not show with any a thickness shape change of 100 afterμm, whe applyingn the thephotoresist thick photoresist. has an average However, thickness for anof µ µ ultra-thin70 μm and wafer when withit is cooled a thickness down of to 100 roomm, temperature when the photoresist post-baking has, the an compressive average thickness stress will of 70 bendm andthe two when-inch it is fused cooled silica down wafer. to room The temperature etching selectivity post-baking, using theamorphous compressive silicon stress mask will is bend tripled the two-inchcompared fused to a silicasingle wafer. photoresist The etching mask selectivity. However using, a lot amorphous of bubbles silicon appear mask when is tripled the deposition compared tothickness a single exceeds photoresist 6 μm mask. with However,plasma-enhanced a lot of bubbles chemical appear vapor when deposition the deposition (PECVD) thickness. In consequence, exceeds 6a-µSim mask with is plasma-enhanced only suitable for chemical via hole vaporetching deposition with a depth (PECVD). less than In consequence, 25 μm. The a-Sichromium mask is mask only suitableshowed the for viabest hole selectivity etching result, with and a depth it is lesspossible than to 25 etchµm. through The chromium 100 μm thick mask fused showed silica the, if best a 5 selectivityμm thick chromium result, and mask it is possible can be deposited. to etch through However, 100 µm due thick to the fused equipment silica, if a limitation 5 µm thicks in chromium our lab, the chromium mask was only sputtered for two hours in our experiment, achieving a thickness of 1.4 μm, which is not sufficient to etch through the fused silica. Furthermore, wet etching was used when transferring the desired pattern to the chromium mask, so the isotropic properties will lead to a slightly larger via hole size, which could be a potential drawback.

Micromachines 2018, 9, 138 6 of 9 mask can be deposited. However, due to the equipment limitations in our lab, the chromium mask was only sputtered for two hours in our experiment, achieving a thickness of 1.4 µm, which is not sufficient to etch through the fused silica. Furthermore, wet etching was used when transferring the desired pattern to the chromium mask, so the isotropic properties will lead to a slightly larger via hole size, which could be a potential drawback. Micromachines 2018, 9, x 6 of 9 3.2. Laser Ablation of Fused Silica 3.2. Laser Ablation of Fused Silica It was found empirically that the laser average power and the repetition used for each pattern It was found empirically that the laser average power and the repetition used for each pattern play key roles in the process. Based on the appearance of the etched sample, the key parameters of the play key roles in the process. Based on the appearance of the etched sample, the key parameters of laser ablation recipe were tested and optimized. Figure4 shows the inspection results under optical the laser ablation recipe were tested and optimized. Figure 4 shows the inspection results under microscope, without cleaning the debris. optical microscope, without cleaning the debris.

FigureFigure 4.4. AppearancesAppearances ofof etchedetched samplessamples underunder microscope:microscope: (a) 115115 mWmW andand 5050 passes;passes; ((b)) 115115 mWmW andand 5050 passespasses withwith roundround corners;corners; ((cc)) 102102 mWmW andand 6060 passes;passes; ((dd)) AccuracyAccuracy ofoflaser laser etching. etching.

In the initial experiment, the laser power was set to 70 mW and the repetition was 50 passes. In the initial experiment, the laser power was set to 70 mW and the repetition was 50 passes. However, it only left faint marks on the wafer without any hole or trench, which means the power However, it only left faint marks on the wafer without any hole or trench, which means the power was was below the ablation threshold. Figure 4a shows the etched result when the power is increased to below the ablation threshold. Figure4a shows the etched result when the power is increased to 115 mW 115 mW with a repetition of 50 passes. The corner chipped obviously although the central rectangular with a repetition of 50 passes. The corner chipped obviously although the central rectangular window window fell away from the wafer. Since the chipping positions happened at the four corners, one fell away from the wafer. Since the chipping positions happened at the four corners, one possible possible reason could be the sharp angle of the laser scanning route. In order to avoid the abrupt reason could be the sharp angle of the laser scanning route. In order to avoid the abrupt direction direction change, patterns with round corners were etched with the same processing parameters and change, patterns with round corners were etched with the same processing parameters and the results the results in Figure 4b show that the cracks still exist at random locations. The other explanation for in Figure4b show that the cracks still exist at random locations. The other explanation for the cracks the cracks is that the laser power was too high for the ultra-thin wafer. The repetition of the etching is that the laser power was too high for the ultra-thin wafer. The repetition of the etching pattern pattern should be increased, with a weaker average power selected. When processing with 102 mW should be increased, with a weaker average power selected. When processing with 102 mW of power of power at 60 repetition passes, the fused silica wafer was able to be cleanly etched through without at 60 repetition passes, the fused silica wafer was able to be cleanly etched through without cracks, cracks, as demonstrated in Figure 4c. This corresponds to a processing fluence of 2.89 J/cm2, while the as demonstrated in Figure4c. This corresponds to a processing fluence of 2.89 J/cm 2, while the pulse overlap was 91%. Furthermore, based on these optimized parameters, the power of the initial pulse overlap was 91%. Furthermore, based on these optimized parameters, the power of the initial 10 passes was adjusted to a more gentle 80 mW, but the etched results showed no obvious 10 passes was adjusted to a more gentle 80 mW, but the etched results showed no obvious improvement. improvement. This confirms that the roughness of the etched edges and sidewalls is independent of This confirms that the roughness of the etched edges and sidewalls is independent of the average the average output power when it is within a reasonable range. In order to study the etching accuracy output power when it is within a reasonable range. In order to study the etching accuracy and and resolution of the laser ablation process, a pattern with tooth structures and open windows was resolution of the laser ablation process, a pattern with tooth structures and open windows was etched etched and is illustrated in Figure 4d. The width of the tooth part was set to 50 μm, decreasing to 37 and is illustrated in Figure4d. The width of the tooth part was set to 50 µm, decreasing to 37 µm and μm and the 300 μm wide open windows became 306 μm. the 300 µm wide open windows became 306 µm. Subsequently to the laser ablation process, an ultrasonic acetone bath was adopted in order to lift the debris from the surface. Figure 5a shows the SEM micrograph of the through via holes etched by laser. The via holes had dimensions of 200 μm × 300 μm and the distance between the adjacent rectangular windows was 250 μm. The processed surface was free of debris after cleaning and the sidewall has a reasonable roughness to support metal connections. A cross-section of the sidewall profile is illustrated in Figure 5b and the tapered angle was measured to be 75°, which is more suitable for the subsequent metallization process compared to a vertical sidewall. In order to compare the etch rates between ICP-RIE and laser ablation, a two-inch wafer with 624 via holes was processed by laser machining and the time consumed was 2.3 h, corresponding to

Micromachines 2018, 9, 138 7 of 9

Subsequently to the laser ablation process, an ultrasonic acetone bath was adopted in order to lift the debris from the surface. Figure5a shows the SEM micrograph of the through via holes etched by laser. The via holes had dimensions of 200 µm × 300 µm and the distance between the adjacent rectangular windows was 250 µm. The processed surface was free of debris after cleaning and the sidewall has a reasonable roughness to support metal connections. A cross-section of the sidewall profile is illustrated in Figure5b and the tapered angle was measured to be 75 ◦, which is more suitable for the subsequent metallization process compared to a vertical sidewall. In order to compare the etch rates between ICP-RIE and laser ablation, a two-inch wafer with 624Micromachines via holes 2018 was, 9, processedx by laser machining and the time consumed was 2.3 h, corresponding7 of to 9 Micromachines 2018, 9, x 7 of 9 13 s for a single hole etching. The etch rates of both methods are plotted versus via hole numbers in 13 s for a single hole etching. The etch rates of both methods are plotted versus via hole numbers in Figure6. In contrast to laser ablation, which etches the via holes one by one, the etch rate of ICP-RIE Fig13 sure for 6. a Insingle contrast hole to etching. laser ablation The etch, which rates etchesof both the methods via holes are one plotted by one, versus the etchvia hole rate numbersof ICP-RIE in will not change with via hole number since they are processed at the same time. The laser ablation willFigure not 6. change In contrast with to via laser hole ablation number, which since theyetches are the processed via holes atone the by same one, time.the etch The rate laser of ablationICP-RIE method is less time consuming with a via number below 950 per wafer. The comparison results are methodwill not ischange less time with consuming via hole number with a viasince number they are below processed 950 per at wafer. the same The time. comparison The laser results ablation are based on 200 µm × 300 µm via hole dimensions in 100 µm thick, two-inch fused silica wafers. The cross basedmethod on is 200 less μ timem × 300consuming μm via holewith dimensionsa via number in below100 μ m950 thick per, wafer.two-inch The fused comparison silica wafers. results The are point of the two curves will shift to the right with decreased via hole dimensions, and vice versa. crossbased point on 200 of theμm two × 300 curves μm viawill hole shift dimensions to the right within 100 decreased μm thick via, two hole-inch dimensions, fused silica and wafers. vice versa. The cross point of the two curves will shift to the right with decreased via hole dimensions, and vice versa.

FigureFigure 5. ((a)) SEM SEM micrograph micrograph of of laser laser etched etched via via holes; holes; ( (bb)) Cross Cross-section-section image, etching direction from rightFigure to 5. left. (a) SEM micrograph of laser etched via holes; (b) Cross-section image, etching direction from right to left.

Figure 6. Etch rate comparison. FigureFigure 6.6. EtchEtch raterate comparison.comparison. 4. Conclusions 4.4. Conclusions In this paper, two technologies—ICP-RIE and laser ablation—which can create through via holes on fusedInIn thisthis silica paper,paper, wafers twotwo technologies—ICP-RIEtechnologieswere studied— andICP -compared.RIE andand laserlaser In ablation—whichablationterms of— thewhich dry cancanetching createcreate method, throughthrough we viavia tested holesholes onthreeon fusedfused types silicasilica of wafersmask wafers material were were studied studiedand investigated and and compared. compared. the Inetch termsIn rateterms of and the of selectivity drythe etchingdry etching of method, each method, material we tested we with tested three the typesoptimalthree oftypes maskprocess of materialmask recipes. material and Then, investigated and we investigatedanalyzed the etchthe theadvantages rate etch and rate selectivity and and disadvantages selectivity of each materialof each of different material with the materials, with optimal the processasoptimal well as recipes. process their ability Then, recipes. we to Then, analyzedetch through we analyzed the advantages100 μ them thick advantages and wafers. disadvantages and Experiments disadvantages of different show of that materials, different on the materials, as practical well as semiconductoras well as their manufacturingability to etch throughlevel, chromium 100 μm thickmetal wafers. mask is Experiments the best choice show for thatthe etchingon the practicalof ultra- thinsemiconductor fused silica manufacturing wafers. The sidewalls level, chromium are almost metal perpendicular mask is the to best the waferchoice surface for the andetching have of a ultra very- smooththin fused finish. silica wafers. The sidewalls are almost perpendicular to the wafer surface and have a very smoothWe finish.also described the processing strategy and experimental setup when applying a picosecond laser Weto etch also the described through the via processing holes. The strategylaser power, and experimentalkerf size and repetitionsetup when of applyingthe etched a picosecondpattern are thelaser three to etch main the parameters through via that holes. determine The laser the power, etched kerf results. size and Laser repetition ablation of theis considered etched pattern a more are convenientthe three main method parameters to obtain that through determine via hole thes etchedin thin results.fused silica Laser wafer ablations, since is considered it can avoid a thmoreese complexconvenient micro method-fabrication to obtain process through steps. via Thehole etcheds in thin via fused holes silica show wafer a goods, since quality it can and avoid sidewall these profilecomplex for micro the following-fabrication metallization process steps. process, The althoughetched via the holes accuracy show and a good surface quality roughness and sidewall cannot matchprofile the for results the following obtained metallization from dry etching. process, Considering although the fastaccuracy etch rate and when surface the roughness quantity of cannot holes permatch wafer the isresults less than obtained 500, this from method dry etching. has extensive Considering potential the fast application etch rates when and value. the quantity of holes per wafer is less than 500, this method has extensive potential applications and value.

Micromachines 2018, 9, 138 8 of 9 their ability to etch through 100 µm thick wafers. Experiments show that on the practical semiconductor manufacturing level, chromium metal mask is the best choice for the etching of ultra-thin fused silica wafers. The sidewalls are almost perpendicular to the wafer surface and have a very smooth finish. We also described the processing strategy and experimental setup when applying a picosecond laser to etch the through via holes. The laser power, kerf size and repetition of the etched pattern are the three main parameters that determine the etched results. Laser ablation is considered a more convenient method to obtain through via holes in thin fused silica wafers, since it can avoid these complex micro-fabrication process steps. The etched via holes show a good quality and sidewall profile for the following metallization process, although the accuracy and surface roughness cannot match the results obtained from dry etching. Considering the fast etch rate when the quantity of holes per wafer is less than 500, this method has extensive potential applications and value.

Acknowledgments: This work was performed in part at the New South Wales (NSW) node and OptoFab node of the Australian National Fabrication Facility, a company established under the National Collaborative Research Infrastructure Strategy to provide nano- and micro-fabrication facilities for Australia’s researchers. Micrographs are taken with the facilities at the Electron Microscope Unit at University of New South Wales (UNSW). Author Contributions: X.L. conceived, designed and conducted the experimental work under the supervision of K.Y.C. and R.R.; X.L. wrote the paper under the supervision and revision of K.Y.C. and R.R. Conflicts of Interest: The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the decision to publish the results.

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