XE166 Derivatives 16-Bit Single-Chip Real Time Signal Controller Volume 1 (Of 2): System Units

User’s Manual, V2.1, Aug. 2008 XE166 Derivatives 16-Bit Single-Chip Real Time Signal Controller Volume 1 (of 2): System Units Microcontrollers Edition 2008-08 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). 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User’s Manual, V2.1, Aug. 2008 XE166 Derivatives 16-Bit Single-Chip Real Time Signal Controller Volume 1 (of 2): System Units Microcontrollers XE166 Derivatives System Units (Vol. 1 of 2) XE16x Revision History: V2.1, 2008-08 Previous Version(s): V2.0, 2007-12 V1.0, 2007-10 Page Subjects (major changes since last revision) 1-5 Derivative synopsis table replaced by reference to Data Sheets 3-49ff Recommendations for Flash usage added 6-1ff Various descriptions refined and corrected (throughout the chapter) 6-77ff Description of EVR registers corrected 6-112ff Software Boot Support added 6-155ff Description of register ISSR corrected 6-161ff Description of Double Watchdog Timer Error corrected 6-182 Memory Content Protection added (was in memory chapter before) 8-2 Description of pin TRef updated 9-1ff Minor updates in description of EBC 10-2ff Status information added 10-29 Bootstrap loader information improved 11-1ff Minor updates in debug chapter We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] User’s Manual V2.1, 2008-08 XE166 Derivatives System Units (Vol. 1 of 2) Summary Of Chapters Summary Of Chapters This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For a quick overview this table of chapters summarizes both volumes, so you immediately can find the reference to the desired section in the corresponding document ([1] or [2]). Summary Of Chapters . 0-1 [1] Table Of Contents . 0-2 [1] 1 Introduction . 1-1 [1] 2 Architectural Overview . 2-1 [1] 3 Memory Organization . 3-1 [1] 4 Central Processing Unit (CPU) . 4-1 [1] 5 Interrupt and Trap Functions . 5-1 [1] 6 System Control Unit (SCU) . 6-1 [1] 7 Parallel Ports . 7-1 [1] 8 Dedicated Pins . 8-1 [1] 9 The External Bus Controller EBC . 9-1 [1] 10 Startup Configuration and Bootstrap Loading . 10-1 [1] 11 Debug System . 11-1 [1] 12 Instruction Set Summary . 12-1 [1] 13 Device Specification . 13-1 [1] 14 The General Purpose Timer Units . 14-1 [2] 15 Real Time Clock . 15-1 [2] 16 Analog to Digital Converter . 16-1 [2] 17 Capture/Compare Unit 2 . 17-1 [2] 18 Capture/Compare Unit 6 (CCU6) . 18-1 [2] 19 Universal Serial Interface Channel . 19-1 [2] 20 Controller Area Network (MultiCAN) Controller . 20-1 [2] Keyword Index . 21-1 [2] Register Index . 22-7 [2] User’s Manual L-1 V2.1, 2008-08 XE166 Derivatives System Units (Vol. 1 of 2) Table Of Contents Table Of Contents This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For your convenience this table of contents (and also the keyword and register index) lists both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]). Summary Of Chapters . 0-1 [1] Table Of Contents . 0-2 [1] 1 Introduction . 1-1 [1] 1.1 Members of the 16-bit Microcontroller Family . 1-3 [1] 1.2 Summary of Basic Features . 1-5 [1] 1.3 Abbreviations . 1-9 [1] 1.4 Naming Conventions . 1-10 [1] 2 Architectural Overview . 2-1 [1] 2.1 Basic CPU Concepts and Optimizations . 2-2 [1] 2.1.1 High Instruction Bandwidth/Fast Execution . 2-4 [1] 2.1.2 Powerful Execution Units . 2-5 [1] 2.1.3 High Performance Branch-, Call-, and Loop-Processing . 2-6 [1] 2.1.4 Consistent and Optimized Instruction Formats . 2-7 [1] 2.1.5 Programmable Multiple Priority Interrupt System . 2-8 [1] 2.1.6 Interfaces to System Resources . 2-9 [1] 2.2 On-Chip System Resources . 2-10 [1] 2.3 On-Chip Peripheral Blocks . 2-15 [1] 2.4 Clock Generation . 2-32 [1] 2.5 Power Management . 2-33 [1] 2.6 On-Chip Debug Support (OCDS) . 2-34 [1] 3 Memory Organization . 3-1 [1] 3.1 Address Mapping . 3-3 [1] 3.2 Special Function Register Areas . 3-5 [1] 3.3 Data Memory Areas . 3-9 [1] 3.4 Program Memory Areas . 3-11 [1] 3.4.1 Program/Data SRAM (PSRAM) . 3-12 [1] 3.4.2 Non-Volatile Program Memory (Flash) . 3-13 [1] 3.5 System Stack . 3-14 [1] 3.6 IO Areas . 3-15 [1] 3.7 External Memory Space . 3-16 [1] 3.8 Crossing Memory Boundaries . 3-17 [1] 3.9 Embedded Flash Memory . 3-18 [1] 3.9.1 Definitions . 3-18 [1] User’s Manual L-2 V2.1, 2008-08 XE166 Derivatives System Units (Vol. 1 of 2) Table Of Contents 3.9.2 Operating Modes . 3-20 [1] 3.9.3 Operations . 3-22 [1] 3.9.4 Details of Command Sequences . 3-25 [1] 3.9.5 Data Integrity . 3-35 [1] 3.9.6 Protection Handling Details . 3-38 [1] 3.9.7 Protection Handling Examples . 3-45 [1] 3.9.8 EEPROM Emulation . 3-47 [1] 3.9.9 Interrupt Generation . 3-49 [1] 3.9.10 Recommendations for Optimized Flash Usage . 3-49 [1] 3.10 On-Chip Program Memory Control . 3-51 [1] 3.10.1 Overview . 3-51 [1] 3.10.2 Register Interface . 3-53 [1] 3.10.3 Error Reporting Summary . 3-64 [1] 3.11 Data Retention Memories . 3-65 [1] 4 Central Processing Unit (CPU) . 4-1 [1] 4.1 Components of the CPU . 4-4 [1] 4.2 Instruction Fetch and Program Flow Control . 4-5 [1] 4.2.1 Branch Detection and Branch Prediction Rules . 4-7 [1] 4.2.2 Correctly Predicted Instruction Flow . 4-7 [1] 4.2.3 Incorrectly Predicted Instruction Flow . 4-9 [1] 4.3 Instruction Processing Pipeline . 4-11 [1] 4.3.1 Pipeline Conflicts Using General Purpose Registers . 4-13 [1] 4.3.2 Pipeline Conflicts Using Indirect Addressing Modes . 4-15 [1] 4.3.3 Pipeline Conflicts Due to Memory Bandwidth . 4-17 [1] 4.3.4 Pipeline Conflicts Caused by CPU-SFR Updates . ..

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